xref: /openbmc/linux/arch/arm/mach-pxa/pxa3xx-regs.h (revision e6acc406)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
4  *
5  * PXA3xx specific register definitions
6  *
7  * Copyright (C) 2007 Marvell International Ltd.
8  */
9 
10 #ifndef __ASM_ARCH_PXA3XX_REGS_H
11 #define __ASM_ARCH_PXA3XX_REGS_H
12 
13 #include "pxa-regs.h"
14 
15 /*
16  * Oscillator Configuration Register (OSCC)
17  */
18 #define OSCC           io_p2v(0x41350000)  /* Oscillator Configuration Register */
19 
20 #define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
21 
22 
23 /*
24  * Service Power Management Unit (MPMU)
25  */
26 #define PMCR		__REG(0x40F50000)	/* Power Manager Control Register */
27 #define PSR		__REG(0x40F50004)	/* Power Manager S2 Status Register */
28 #define PSPR		__REG(0x40F50008)	/* Power Manager Scratch Pad Register */
29 #define PCFR		__REG(0x40F5000C)	/* Power Manager General Configuration Register */
30 #define PWER		__REG(0x40F50010)	/* Power Manager Wake-up Enable Register */
31 #define PWSR		__REG(0x40F50014)	/* Power Manager Wake-up Status Register */
32 #define PECR		__REG(0x40F50018)	/* Power Manager EXT_WAKEUP[1:0] Control Register */
33 #define DCDCSR		__REG(0x40F50080)	/* DC-DC Controller Status Register */
34 #define PVCR		__REG(0x40F50100)	/* Power Manager Voltage Change Control Register */
35 #define PCMD(x)		__REG(0x40F50110 + ((x) << 2))
36 
37 /*
38  * Slave Power Management Unit
39  */
40 #define ASCR		__REG(0x40f40000)	/* Application Subsystem Power Status/Configuration */
41 #define ARSR		__REG(0x40f40004)	/* Application Subsystem Reset Status */
42 #define AD3ER		__REG(0x40f40008)	/* Application Subsystem Wake-Up from D3 Enable */
43 #define AD3SR		__REG(0x40f4000c)	/* Application Subsystem Wake-Up from D3 Status */
44 #define AD2D0ER		__REG(0x40f40010)	/* Application Subsystem Wake-Up from D2 to D0 Enable */
45 #define AD2D0SR		__REG(0x40f40014)	/* Application Subsystem Wake-Up from D2 to D0 Status */
46 #define AD2D1ER		__REG(0x40f40018)	/* Application Subsystem Wake-Up from D2 to D1 Enable */
47 #define AD2D1SR		__REG(0x40f4001c)	/* Application Subsystem Wake-Up from D2 to D1 Status */
48 #define AD1D0ER		__REG(0x40f40020)	/* Application Subsystem Wake-Up from D1 to D0 Enable */
49 #define AD1D0SR		__REG(0x40f40024)	/* Application Subsystem Wake-Up from D1 to D0 Status */
50 #define AGENP		__REG(0x40f4002c)	/* Application Subsystem General Purpose */
51 #define AD3R		__REG(0x40f40030)	/* Application Subsystem D3 Configuration */
52 #define AD2R		__REG(0x40f40034)	/* Application Subsystem D2 Configuration */
53 #define AD1R		__REG(0x40f40038)	/* Application Subsystem D1 Configuration */
54 
55 /*
56  * Application Subsystem Configuration bits.
57  */
58 #define ASCR_RDH		(1 << 31)
59 #define ASCR_D1S		(1 << 2)
60 #define ASCR_D2S		(1 << 1)
61 #define ASCR_D3S		(1 << 0)
62 
63 /*
64  * Application Reset Status bits.
65  */
66 #define ARSR_GPR		(1 << 3)
67 #define ARSR_LPMR		(1 << 2)
68 #define ARSR_WDT		(1 << 1)
69 #define ARSR_HWR		(1 << 0)
70 
71 /*
72  * Application Subsystem Wake-Up bits.
73  */
74 #define ADXER_WRTC		(1 << 31)	/* RTC */
75 #define ADXER_WOST		(1 << 30)	/* OS Timer */
76 #define ADXER_WTSI		(1 << 29)	/* Touchscreen */
77 #define ADXER_WUSBH		(1 << 28)	/* USB host */
78 #define ADXER_WUSB2		(1 << 26)	/* USB client 2.0 */
79 #define ADXER_WMSL0		(1 << 24)	/* MSL port 0*/
80 #define ADXER_WDMUX3		(1 << 23)	/* USB EDMUX3 */
81 #define ADXER_WDMUX2		(1 << 22)	/* USB EDMUX2 */
82 #define ADXER_WKP		(1 << 21)	/* Keypad */
83 #define ADXER_WUSIM1		(1 << 20)	/* USIM Port 1 */
84 #define ADXER_WUSIM0		(1 << 19)	/* USIM Port 0 */
85 #define ADXER_WOTG		(1 << 16)	/* USBOTG input */
86 #define ADXER_MFP_WFLASH	(1 << 15)	/* MFP: Data flash busy */
87 #define ADXER_MFP_GEN12		(1 << 14)	/* MFP: MMC3/GPIO/OST inputs */
88 #define ADXER_MFP_WMMC2		(1 << 13)	/* MFP: MMC2 */
89 #define ADXER_MFP_WMMC1		(1 << 12)	/* MFP: MMC1 */
90 #define ADXER_MFP_WI2C		(1 << 11)	/* MFP: I2C */
91 #define ADXER_MFP_WSSP4		(1 << 10)	/* MFP: SSP4 */
92 #define ADXER_MFP_WSSP3		(1 << 9)	/* MFP: SSP3 */
93 #define ADXER_MFP_WMAXTRIX	(1 << 8)	/* MFP: matrix keypad */
94 #define ADXER_MFP_WUART3	(1 << 7)	/* MFP: UART3 */
95 #define ADXER_MFP_WUART2	(1 << 6)	/* MFP: UART2 */
96 #define ADXER_MFP_WUART1	(1 << 5)	/* MFP: UART1 */
97 #define ADXER_MFP_WSSP2		(1 << 4)	/* MFP: SSP2 */
98 #define ADXER_MFP_WSSP1		(1 << 3)	/* MFP: SSP1 */
99 #define ADXER_MFP_WAC97		(1 << 2)	/* MFP: AC97 */
100 #define ADXER_WEXTWAKE1		(1 << 1)	/* External Wake 1 */
101 #define ADXER_WEXTWAKE0		(1 << 0)	/* External Wake 0 */
102 
103 /*
104  * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
105  */
106 #define ADXR_L2			(1 << 8)
107 #define ADXR_R5			(1 << 5)
108 #define ADXR_R4			(1 << 4)
109 #define ADXR_R3			(1 << 3)
110 #define ADXR_R2			(1 << 2)
111 #define ADXR_R1			(1 << 1)
112 #define ADXR_R0			(1 << 0)
113 
114 /*
115  * Values for PWRMODE CP15 register
116  */
117 #define PXA3xx_PM_S3D4C4	0x07	/* aka deep sleep */
118 #define PXA3xx_PM_S2D3C4	0x06	/* aka sleep */
119 #define PXA3xx_PM_S0D2C2	0x03	/* aka standby */
120 #define PXA3xx_PM_S0D1C2	0x02	/* aka LCD refresh */
121 #define PXA3xx_PM_S0D0C1	0x01
122 
123 /*
124  * Application Subsystem Clock
125  */
126 #define ACCR		__REG(0x41340000)	/* Application Subsystem Clock Configuration Register */
127 #define ACSR		__REG(0x41340004)	/* Application Subsystem Clock Status Register */
128 #define AICSR		__REG(0x41340008)	/* Application Subsystem Interrupt Control/Status Register */
129 #define CKENA		__REG(0x4134000C)	/* A Clock Enable Register */
130 #define CKENB		__REG(0x41340010)	/* B Clock Enable Register */
131 #define CKENC		__REG(0x41340024)	/* C Clock Enable Register */
132 #define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */
133 
134 #endif /* __ASM_ARCH_PXA3XX_REGS_H */
135