1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Analog Devices ADV7511 HDMI transmitter driver
4 *
5 * Copyright 2012 Analog Devices Inc.
6 */
7
8 #ifndef __DRM_I2C_ADV7511_H__
9 #define __DRM_I2C_ADV7511_H__
10
11 #include <linux/hdmi.h>
12 #include <linux/i2c.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15
16 #include <drm/drm_bridge.h>
17 #include <drm/drm_connector.h>
18 #include <drm/drm_mipi_dsi.h>
19 #include <drm/drm_modes.h>
20
21 #define ADV7511_REG_CHIP_REVISION 0x00
22 #define ADV7511_REG_N0 0x01
23 #define ADV7511_REG_N1 0x02
24 #define ADV7511_REG_N2 0x03
25 #define ADV7511_REG_SPDIF_FREQ 0x04
26 #define ADV7511_REG_CTS_AUTOMATIC1 0x05
27 #define ADV7511_REG_CTS_AUTOMATIC2 0x06
28 #define ADV7511_REG_CTS_MANUAL0 0x07
29 #define ADV7511_REG_CTS_MANUAL1 0x08
30 #define ADV7511_REG_CTS_MANUAL2 0x09
31 #define ADV7511_REG_AUDIO_SOURCE 0x0a
32 #define ADV7511_REG_AUDIO_CONFIG 0x0b
33 #define ADV7511_REG_I2S_CONFIG 0x0c
34 #define ADV7511_REG_I2S_WIDTH 0x0d
35 #define ADV7511_REG_AUDIO_SUB_SRC0 0x0e
36 #define ADV7511_REG_AUDIO_SUB_SRC1 0x0f
37 #define ADV7511_REG_AUDIO_SUB_SRC2 0x10
38 #define ADV7511_REG_AUDIO_SUB_SRC3 0x11
39 #define ADV7511_REG_AUDIO_CFG1 0x12
40 #define ADV7511_REG_AUDIO_CFG2 0x13
41 #define ADV7511_REG_AUDIO_CFG3 0x14
42 #define ADV7511_REG_I2C_FREQ_ID_CFG 0x15
43 #define ADV7511_REG_VIDEO_INPUT_CFG1 0x16
44 #define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)
45 #define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)
46 #define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))
47 #define ADV7511_REG_DE_GENERATOR (0x35 + (x))
48 #define ADV7511_REG_PIXEL_REPETITION 0x3b
49 #define ADV7511_REG_VIC_MANUAL 0x3c
50 #define ADV7511_REG_VIC_SEND 0x3d
51 #define ADV7511_REG_VIC_DETECTED 0x3e
52 #define ADV7511_REG_AUX_VIC_DETECTED 0x3f
53 #define ADV7511_REG_PACKET_ENABLE0 0x40
54 #define ADV7511_REG_POWER 0x41
55 #define ADV7511_REG_STATUS 0x42
56 #define ADV7511_REG_EDID_I2C_ADDR 0x43
57 #define ADV7511_REG_PACKET_ENABLE1 0x44
58 #define ADV7511_REG_PACKET_I2C_ADDR 0x45
59 #define ADV7511_REG_DSD_ENABLE 0x46
60 #define ADV7511_REG_VIDEO_INPUT_CFG2 0x48
61 #define ADV7511_REG_INFOFRAME_UPDATE 0x4a
62 #define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
63 #define ADV7511_REG_AVI_INFOFRAME_VERSION 0x52
64 #define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x53
65 #define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x54
66 #define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
67 #define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
68 #define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x71
69 #define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
70 #define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
71 #define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))
72 #define ADV7511_REG_INT(x) (0x96 + (x))
73 #define ADV7511_REG_INPUT_CLK_DIV 0x9d
74 #define ADV7511_REG_PLL_STATUS 0x9e
75 #define ADV7511_REG_HDMI_POWER 0xa1
76 #define ADV7511_REG_HDCP_HDMI_CFG 0xaf
77 #define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
78 #define ADV7511_REG_HDCP_STATUS 0xb8
79 #define ADV7511_REG_BCAPS 0xbe
80 #define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
81 #define ADV7511_REG_EDID_SEGMENT 0xc4
82 #define ADV7511_REG_DDC_STATUS 0xc8
83 #define ADV7511_REG_EDID_READ_CTRL 0xc9
84 #define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
85 #define ADV7511_REG_TIMING_GEN_SEQ 0xd0
86 #define ADV7511_REG_POWER2 0xd6
87 #define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa
88
89 #define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
90 #define ADV7511_REG_TMDS_CLOCK_INV 0xde
91 #define ADV7511_REG_ARC_CTRL 0xdf
92 #define ADV7511_REG_CEC_I2C_ADDR 0xe1
93 #define ADV7511_REG_CEC_CTRL 0xe2
94 #define ADV7511_REG_CHIP_ID_HIGH 0xf5
95 #define ADV7511_REG_CHIP_ID_LOW 0xf6
96
97 /* Hardware defined default addresses for I2C register maps */
98 #define ADV7511_CEC_I2C_ADDR_DEFAULT 0x3c
99 #define ADV7511_EDID_I2C_ADDR_DEFAULT 0x3f
100 #define ADV7511_PACKET_I2C_ADDR_DEFAULT 0x38
101
102 #define ADV7511_CSC_ENABLE BIT(7)
103 #define ADV7511_CSC_UPDATE_MODE BIT(5)
104
105 #define ADV7511_INT0_HPD BIT(7)
106 #define ADV7511_INT0_VSYNC BIT(5)
107 #define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
108 #define ADV7511_INT0_EDID_READY BIT(2)
109 #define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
110
111 #define ADV7511_INT1_DDC_ERROR BIT(7)
112 #define ADV7511_INT1_BKSV BIT(6)
113 #define ADV7511_INT1_CEC_TX_READY BIT(5)
114 #define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)
115 #define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
116 #define ADV7511_INT1_CEC_RX_READY3 BIT(2)
117 #define ADV7511_INT1_CEC_RX_READY2 BIT(1)
118 #define ADV7511_INT1_CEC_RX_READY1 BIT(0)
119
120 #define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)
121
122 #define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)
123
124 #define ADV7511_POWER_POWER_DOWN BIT(6)
125
126 #define ADV7511_HDMI_CFG_MODE_MASK 0x2
127 #define ADV7511_HDMI_CFG_MODE_DVI 0x0
128 #define ADV7511_HDMI_CFG_MODE_HDMI 0x2
129
130 #define ADV7511_AUDIO_SELECT_I2C 0x0
131 #define ADV7511_AUDIO_SELECT_SPDIF 0x1
132 #define ADV7511_AUDIO_SELECT_DSD 0x2
133 #define ADV7511_AUDIO_SELECT_HBR 0x3
134 #define ADV7511_AUDIO_SELECT_DST 0x4
135
136 #define ADV7511_I2S_SAMPLE_LEN_16 0x2
137 #define ADV7511_I2S_SAMPLE_LEN_20 0x3
138 #define ADV7511_I2S_SAMPLE_LEN_18 0x4
139 #define ADV7511_I2S_SAMPLE_LEN_22 0x5
140 #define ADV7511_I2S_SAMPLE_LEN_19 0x8
141 #define ADV7511_I2S_SAMPLE_LEN_23 0x9
142 #define ADV7511_I2S_SAMPLE_LEN_24 0xb
143 #define ADV7511_I2S_SAMPLE_LEN_17 0xc
144 #define ADV7511_I2S_SAMPLE_LEN_21 0xd
145
146 #define ADV7511_SAMPLE_FREQ_44100 0x0
147 #define ADV7511_SAMPLE_FREQ_48000 0x2
148 #define ADV7511_SAMPLE_FREQ_32000 0x3
149 #define ADV7511_SAMPLE_FREQ_88200 0x8
150 #define ADV7511_SAMPLE_FREQ_96000 0xa
151 #define ADV7511_SAMPLE_FREQ_176400 0xc
152 #define ADV7511_SAMPLE_FREQ_192000 0xe
153
154 #define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)
155 #define ADV7511_STATUS_HPD BIT(6)
156 #define ADV7511_STATUS_MONITOR_SENSE BIT(5)
157 #define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)
158
159 #define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)
160 #define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
161 #define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
162 #define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
163 #define ADV7511_PACKET_ENABLE_GC BIT(7)
164 #define ADV7511_PACKET_ENABLE_SPD BIT(6)
165 #define ADV7511_PACKET_ENABLE_MPEG BIT(5)
166 #define ADV7511_PACKET_ENABLE_ACP BIT(4)
167 #define ADV7511_PACKET_ENABLE_ISRC BIT(3)
168 #define ADV7511_PACKET_ENABLE_GM BIT(2)
169 #define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
170 #define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
171
172 #define ADV7535_REG_POWER2_HPD_OVERRIDE BIT(6)
173 #define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
174 #define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
175 #define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
176 #define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
177 #define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
178 #define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
179 #define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
180
181 #define ADV7511_LOW_REFRESH_RATE_NONE 0x0
182 #define ADV7511_LOW_REFRESH_RATE_24HZ 0x1
183 #define ADV7511_LOW_REFRESH_RATE_25HZ 0x2
184 #define ADV7511_LOW_REFRESH_RATE_30HZ 0x3
185
186 #define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f
187 #define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
188
189 #define ADV7511_AUDIO_SOURCE_I2S 0
190 #define ADV7511_AUDIO_SOURCE_SPDIF 1
191
192 #define ADV7511_I2S_FORMAT_I2S 0
193 #define ADV7511_I2S_FORMAT_RIGHT_J 1
194 #define ADV7511_I2S_FORMAT_LEFT_J 2
195 #define ADV7511_I2S_IEC958_DIRECT 3
196
197 #define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))
198 #define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)
199 #define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)
200 #define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)
201 #define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)
202 #define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)
203 #define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)
204 #define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)
205
206 #define ADV7511_REG_CEC_TX_FRAME_HDR 0x00
207 #define ADV7511_REG_CEC_TX_FRAME_DATA0 0x01
208 #define ADV7511_REG_CEC_TX_FRAME_LEN 0x10
209 #define ADV7511_REG_CEC_TX_ENABLE 0x11
210 #define ADV7511_REG_CEC_TX_RETRY 0x12
211 #define ADV7511_REG_CEC_TX_LOW_DRV_CNT 0x14
212 #define ADV7511_REG_CEC_RX1_FRAME_HDR 0x15
213 #define ADV7511_REG_CEC_RX1_FRAME_DATA0 0x16
214 #define ADV7511_REG_CEC_RX1_FRAME_LEN 0x25
215 #define ADV7511_REG_CEC_RX_STATUS 0x26
216 #define ADV7511_REG_CEC_RX2_FRAME_HDR 0x27
217 #define ADV7511_REG_CEC_RX2_FRAME_DATA0 0x28
218 #define ADV7511_REG_CEC_RX2_FRAME_LEN 0x37
219 #define ADV7511_REG_CEC_RX3_FRAME_HDR 0x38
220 #define ADV7511_REG_CEC_RX3_FRAME_DATA0 0x39
221 #define ADV7511_REG_CEC_RX3_FRAME_LEN 0x48
222 #define ADV7511_REG_CEC_RX_BUFFERS 0x4a
223 #define ADV7511_REG_CEC_LOG_ADDR_MASK 0x4b
224 #define ADV7511_REG_CEC_LOG_ADDR_0_1 0x4c
225 #define ADV7511_REG_CEC_LOG_ADDR_2 0x4d
226 #define ADV7511_REG_CEC_CLK_DIV 0x4e
227 #define ADV7511_REG_CEC_SOFT_RESET 0x50
228
229 #define ADV7533_REG_CEC_OFFSET 0x70
230
231 enum adv7511_input_clock {
232 ADV7511_INPUT_CLOCK_1X,
233 ADV7511_INPUT_CLOCK_2X,
234 ADV7511_INPUT_CLOCK_DDR,
235 };
236
237 enum adv7511_input_justification {
238 ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
239 ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
240 ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
241 };
242
243 enum adv7511_input_sync_pulse {
244 ADV7511_INPUT_SYNC_PULSE_DE = 0,
245 ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
246 ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
247 ADV7511_INPUT_SYNC_PULSE_NONE = 3,
248 };
249
250 /**
251 * enum adv7511_sync_polarity - Polarity for the input sync signals
252 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
253 * the currently configured mode.
254 * @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low
255 * @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high
256 *
257 * If the polarity is set to either LOW or HIGH the driver will configure the
258 * ADV7511 to internally invert the sync signal if required to match the sync
259 * polarity setting for the currently selected output mode.
260 *
261 * If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
262 * unchanged. This is used when the upstream graphics core already generates
263 * the sync signals with the correct polarity.
264 */
265 enum adv7511_sync_polarity {
266 ADV7511_SYNC_POLARITY_PASSTHROUGH,
267 ADV7511_SYNC_POLARITY_LOW,
268 ADV7511_SYNC_POLARITY_HIGH,
269 };
270
271 /**
272 * struct adv7511_link_config - Describes adv7511 hardware configuration
273 * @input_color_depth: Number of bits per color component (8, 10 or 12)
274 * @input_colorspace: The input colorspace (RGB, YUV444, YUV422)
275 * @input_clock: The input video clock style (1x, 2x, DDR)
276 * @input_style: The input component arrangement variant
277 * @input_justification: Video input format bit justification
278 * @clock_delay: Clock delay for the input clock (in ps)
279 * @embedded_sync: Video input uses BT.656-style embedded sync
280 * @sync_pulse: Select the sync pulse
281 * @vsync_polarity: vsync input signal configuration
282 * @hsync_polarity: hsync input signal configuration
283 */
284 struct adv7511_link_config {
285 unsigned int input_color_depth;
286 enum hdmi_colorspace input_colorspace;
287 enum adv7511_input_clock input_clock;
288 unsigned int input_style;
289 enum adv7511_input_justification input_justification;
290
291 int clock_delay;
292
293 bool embedded_sync;
294 enum adv7511_input_sync_pulse sync_pulse;
295 enum adv7511_sync_polarity vsync_polarity;
296 enum adv7511_sync_polarity hsync_polarity;
297 };
298
299 /**
300 * enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
301 * @ADV7511_CSC_SCALING_1: CSC results are not scaled
302 * @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
303 * @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
304 */
305 enum adv7511_csc_scaling {
306 ADV7511_CSC_SCALING_1 = 0,
307 ADV7511_CSC_SCALING_2 = 1,
308 ADV7511_CSC_SCALING_4 = 2,
309 };
310
311 /**
312 * struct adv7511_video_config - Describes adv7511 hardware configuration
313 * @csc_enable: Whether to enable color space conversion
314 * @csc_scaling_factor: Color space conversion scaling factor
315 * @csc_coefficents: Color space conversion coefficents
316 * @hdmi_mode: Whether to use HDMI or DVI output mode
317 * @avi_infoframe: HDMI infoframe
318 */
319 struct adv7511_video_config {
320 bool csc_enable;
321 enum adv7511_csc_scaling csc_scaling_factor;
322 const uint16_t *csc_coefficents;
323
324 bool hdmi_mode;
325 struct hdmi_avi_infoframe avi_infoframe;
326 };
327
328 enum adv7511_type {
329 ADV7511,
330 ADV7533,
331 ADV7535,
332 };
333
334 #define ADV7511_MAX_ADDRS 3
335
336 struct adv7511 {
337 struct i2c_client *i2c_main;
338 struct i2c_client *i2c_edid;
339 struct i2c_client *i2c_packet;
340 struct i2c_client *i2c_cec;
341
342 struct regmap *regmap;
343 struct regmap *regmap_cec;
344 unsigned int reg_cec_offset;
345 enum drm_connector_status status;
346 bool powered;
347
348 struct drm_display_mode curr_mode;
349
350 unsigned int f_tmds;
351 unsigned int f_audio;
352 unsigned int audio_source;
353
354 unsigned int current_edid_segment;
355 uint8_t edid_buf[256];
356 bool edid_read;
357
358 wait_queue_head_t wq;
359 struct work_struct hpd_work;
360
361 struct drm_bridge bridge;
362 struct drm_connector connector;
363
364 bool embedded_sync;
365 enum adv7511_sync_polarity vsync_polarity;
366 enum adv7511_sync_polarity hsync_polarity;
367 bool rgb;
368
369 struct gpio_desc *gpio_pd;
370
371 struct regulator_bulk_data *supplies;
372 unsigned int num_supplies;
373
374 /* ADV7533 DSI RX related params */
375 struct device_node *host_node;
376 struct mipi_dsi_device *dsi;
377 u8 num_dsi_lanes;
378 bool use_timing_gen;
379
380 enum adv7511_type type;
381 struct platform_device *audio_pdev;
382
383 struct cec_adapter *cec_adap;
384 u8 cec_addr[ADV7511_MAX_ADDRS];
385 u8 cec_valid_addrs;
386 bool cec_enabled_adap;
387 struct clk *cec_clk;
388 u32 cec_clk_freq;
389 };
390
391 #ifdef CONFIG_DRM_I2C_ADV7511_CEC
392 int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
393 void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
394 #else
adv7511_cec_init(struct device * dev,struct adv7511 * adv7511)395 static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
396 {
397 regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
398 ADV7511_CEC_CTRL_POWER_DOWN);
399 return 0;
400 }
401 #endif
402
403 void adv7533_dsi_power_on(struct adv7511 *adv);
404 void adv7533_dsi_power_off(struct adv7511 *adv);
405 enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
406 const struct drm_display_mode *mode);
407 int adv7533_patch_registers(struct adv7511 *adv);
408 int adv7533_patch_cec_registers(struct adv7511 *adv);
409 int adv7533_attach_dsi(struct adv7511 *adv);
410 int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
411
412 #ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
413 int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);
414 void adv7511_audio_exit(struct adv7511 *adv7511);
415 #else /*CONFIG_DRM_I2C_ADV7511_AUDIO */
adv7511_audio_init(struct device * dev,struct adv7511 * adv7511)416 static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)
417 {
418 return 0;
419 }
adv7511_audio_exit(struct adv7511 * adv7511)420 static inline void adv7511_audio_exit(struct adv7511 *adv7511)
421 {
422 }
423 #endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */
424
425 #endif /* __DRM_I2C_ADV7511_H__ */
426