1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2020 Intel Corporation */
3 #ifndef ADF_GEN4_HW_CSR_DATA_H_
4 #define ADF_GEN4_HW_CSR_DATA_H_
5 
6 #include "adf_accel_devices.h"
7 #include "adf_cfg_common.h"
8 
9 /* Transport access */
10 #define ADF_BANK_INT_SRC_SEL_MASK	0x44UL
11 #define ADF_RING_CSR_RING_CONFIG	0x1000
12 #define ADF_RING_CSR_RING_LBASE		0x1040
13 #define ADF_RING_CSR_RING_UBASE		0x1080
14 #define ADF_RING_CSR_RING_HEAD		0x0C0
15 #define ADF_RING_CSR_RING_TAIL		0x100
16 #define ADF_RING_CSR_E_STAT		0x14C
17 #define ADF_RING_CSR_INT_FLAG		0x170
18 #define ADF_RING_CSR_INT_SRCSEL		0x174
19 #define ADF_RING_CSR_INT_COL_CTL	0x180
20 #define ADF_RING_CSR_INT_FLAG_AND_COL	0x184
21 #define ADF_RING_CSR_INT_COL_CTL_ENABLE	0x80000000
22 #define ADF_RING_CSR_INT_COL_EN		0x17C
23 #define ADF_RING_CSR_ADDR_OFFSET	0x100000
24 #define ADF_RING_BUNDLE_SIZE		0x2000
25 
26 #define BUILD_RING_BASE_ADDR(addr, size) \
27 	((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)
28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
29 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
30 		   ADF_RING_BUNDLE_SIZE * (bank) + \
31 		   ADF_RING_CSR_RING_HEAD + ((ring) << 2))
32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
33 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
34 		   ADF_RING_BUNDLE_SIZE * (bank) + \
35 		   ADF_RING_CSR_RING_TAIL + ((ring) << 2))
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \
37 	ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
38 		   ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
40 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
41 		   ADF_RING_BUNDLE_SIZE * (bank) + \
42 		   ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value)	\
44 do { \
45 	void __iomem *_csr_base_addr = csr_base_addr; \
46 	u32 _bank = bank;						\
47 	u32 _ring = ring;						\
48 	dma_addr_t _value = value;					\
49 	u32 l_base = 0, u_base = 0;					\
50 	l_base = lower_32_bits(_value);					\
51 	u_base = upper_32_bits(_value);					\
52 	ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET,		\
53 		   ADF_RING_BUNDLE_SIZE * (_bank) +			\
54 		   ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base);	\
55 	ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET,		\
56 		   ADF_RING_BUNDLE_SIZE * (_bank) +			\
57 		   ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base);	\
58 } while (0)
59 
60 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
61 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
62 		   ADF_RING_BUNDLE_SIZE * (bank) + \
63 		   ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
64 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
65 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
66 		   ADF_RING_BUNDLE_SIZE * (bank) + \
67 		   ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
68 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
69 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
70 		   ADF_RING_BUNDLE_SIZE * (bank) + \
71 		   ADF_RING_CSR_INT_FLAG, (value))
72 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
73 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
74 		   ADF_RING_BUNDLE_SIZE * (bank) + \
75 		   ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK)
76 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
77 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
78 		   ADF_RING_BUNDLE_SIZE * (bank) + \
79 		   ADF_RING_CSR_INT_COL_EN, (value))
80 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
81 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
82 		   ADF_RING_BUNDLE_SIZE * (bank) + \
83 		   ADF_RING_CSR_INT_COL_CTL, \
84 		   ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
85 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
86 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
87 		   ADF_RING_BUNDLE_SIZE * (bank) + \
88 		   ADF_RING_CSR_INT_FLAG_AND_COL, (value))
89 
90 /* Arbiter configuration */
91 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
92 
93 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
94 	ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
95 		   ADF_RING_BUNDLE_SIZE * (bank) + \
96 		   ADF_RING_CSR_RING_SRV_ARB_EN, (value))
97 
98 /* Default ring mapping */
99 #define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
100 	(ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
101 	  SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
102 	 ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
103 	  SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
104 
105 /* WDT timers
106  *
107  * Timeout is in cycles. Clock speed may vary across products but this
108  * value should be a few milli-seconds.
109  */
110 #define ADF_SSM_WDT_DEFAULT_VALUE	0x7000000ULL
111 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE	0x8000000
112 #define ADF_SSMWDTL_OFFSET		0x54
113 #define ADF_SSMWDTH_OFFSET		0x5C
114 #define ADF_SSMWDTPKEL_OFFSET		0x58
115 #define ADF_SSMWDTPKEH_OFFSET		0x60
116 
117 /* Ring reset */
118 #define ADF_RPRESET_POLL_TIMEOUT_US	(5 * USEC_PER_SEC)
119 #define ADF_RPRESET_POLL_DELAY_US	20
120 #define ADF_WQM_CSR_RPRESETCTL_RESET	BIT(0)
121 #define ADF_WQM_CSR_RPRESETCTL(bank)	(0x6000 + ((bank) << 3))
122 #define ADF_WQM_CSR_RPRESETSTS_STATUS	BIT(0)
123 #define ADF_WQM_CSR_RPRESETSTS(bank)	(ADF_WQM_CSR_RPRESETCTL(bank) + 4)
124 
125 /* Error source registers */
126 #define ADF_GEN4_ERRSOU0	(0x41A200)
127 #define ADF_GEN4_ERRSOU1	(0x41A204)
128 #define ADF_GEN4_ERRSOU2	(0x41A208)
129 #define ADF_GEN4_ERRSOU3	(0x41A20C)
130 
131 /* Error source mask registers */
132 #define ADF_GEN4_ERRMSK0	(0x41A210)
133 #define ADF_GEN4_ERRMSK1	(0x41A214)
134 #define ADF_GEN4_ERRMSK2	(0x41A218)
135 #define ADF_GEN4_ERRMSK3	(0x41A21C)
136 
137 #define ADF_GEN4_VFLNOTIFY	BIT(7)
138 
139 /* Number of heartbeat counter pairs */
140 #define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
141 
142 void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
143 void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
144 int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
145 #endif
146