1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef ADF_DH895x_HW_DATA_H_ 4 #define ADF_DH895x_HW_DATA_H_ 5 6 #include <linux/units.h> 7 8 /* PCIe configuration space */ 9 #define ADF_DH895XCC_SRAM_BAR 0 10 #define ADF_DH895XCC_PMISC_BAR 1 11 #define ADF_DH895XCC_ETR_BAR 2 12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000 13 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20 14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0 15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1 16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2 17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3 18 #define ADF_DH895XCC_MAX_ACCELERATORS 6 19 #define ADF_DH895XCC_MAX_ACCELENGINES 12 20 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13 21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F 22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF 23 #define ADF_DH895XCC_ETR_MAX_BANKS 32 24 25 /* Masks for VF2PF interrupts */ 26 #define ADF_DH895XCC_ERR_REG_VF2PF_L(vf_src) (((vf_src) & 0x01FFFE00) >> 9) 27 #define ADF_DH895XCC_ERR_MSK_VF2PF_L(vf_mask) (((vf_mask) & 0xFFFF) << 9) 28 #define ADF_DH895XCC_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16) 29 #define ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask) ((vf_mask) >> 16) 30 31 /* AE to function mapping */ 32 #define ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS 96 33 #define ADF_DH895XCC_AE2FUNC_MAP_GRP_B_NUM_REGS 12 34 35 /* Clocks frequency */ 36 #define ADF_DH895X_AE_FREQ (933 * HZ_PER_MHZ) 37 38 /* FW names */ 39 #define ADF_DH895XCC_FW "qat_895xcc.bin" 40 #define ADF_DH895XCC_MMP "qat_895xcc_mmp.bin" 41 42 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 43 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 44 #endif 45