xref: /openbmc/linux/drivers/iio/adc/ad7091r-base.c (revision e4e845c8)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * AD7091RX Analog to Digital converter driver
4  *
5  * Copyright 2014-2019 Analog Devices Inc.
6  */
7 
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/iio/events.h>
11 #include <linux/iio/iio.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 
17 #include "ad7091r-base.h"
18 
19 #define AD7091R_REG_RESULT  0
20 #define AD7091R_REG_CHANNEL 1
21 #define AD7091R_REG_CONF    2
22 #define AD7091R_REG_ALERT   3
23 #define AD7091R_REG_CH_LOW_LIMIT(ch) ((ch) * 3 + 4)
24 #define AD7091R_REG_CH_HIGH_LIMIT(ch) ((ch) * 3 + 5)
25 #define AD7091R_REG_CH_HYSTERESIS(ch) ((ch) * 3 + 6)
26 
27 /* AD7091R_REG_RESULT */
28 #define AD7091R_REG_RESULT_CH_ID(x)	    (((x) >> 13) & 0x3)
29 #define AD7091R_REG_RESULT_CONV_RESULT(x)   ((x) & 0xfff)
30 
31 /* AD7091R_REG_CONF */
32 #define AD7091R_REG_CONF_ALERT_EN   BIT(4)
33 #define AD7091R_REG_CONF_AUTO   BIT(8)
34 #define AD7091R_REG_CONF_CMD    BIT(10)
35 
36 #define AD7091R_REG_CONF_MODE_MASK  \
37 	(AD7091R_REG_CONF_AUTO | AD7091R_REG_CONF_CMD)
38 
39 enum ad7091r_mode {
40 	AD7091R_MODE_SAMPLE,
41 	AD7091R_MODE_COMMAND,
42 	AD7091R_MODE_AUTOCYCLE,
43 };
44 
45 struct ad7091r_state {
46 	struct device *dev;
47 	struct regmap *map;
48 	struct regulator *vref;
49 	const struct ad7091r_chip_info *chip_info;
50 	enum ad7091r_mode mode;
51 	struct mutex lock; /*lock to prevent concurent reads */
52 };
53 
54 const struct iio_event_spec ad7091r_events[] = {
55 	{
56 		.type = IIO_EV_TYPE_THRESH,
57 		.dir = IIO_EV_DIR_RISING,
58 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
59 				 BIT(IIO_EV_INFO_ENABLE),
60 	},
61 	{
62 		.type = IIO_EV_TYPE_THRESH,
63 		.dir = IIO_EV_DIR_FALLING,
64 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
65 				 BIT(IIO_EV_INFO_ENABLE),
66 	},
67 	{
68 		.type = IIO_EV_TYPE_THRESH,
69 		.dir = IIO_EV_DIR_EITHER,
70 		.mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
71 	},
72 };
73 EXPORT_SYMBOL_NS_GPL(ad7091r_events, IIO_AD7091R);
74 
ad7091r_set_mode(struct ad7091r_state * st,enum ad7091r_mode mode)75 static int ad7091r_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)
76 {
77 	int ret, conf;
78 
79 	switch (mode) {
80 	case AD7091R_MODE_SAMPLE:
81 		conf = 0;
82 		break;
83 	case AD7091R_MODE_COMMAND:
84 		conf = AD7091R_REG_CONF_CMD;
85 		break;
86 	case AD7091R_MODE_AUTOCYCLE:
87 		conf = AD7091R_REG_CONF_AUTO;
88 		break;
89 	default:
90 		return -EINVAL;
91 	}
92 
93 	ret = regmap_update_bits(st->map, AD7091R_REG_CONF,
94 				 AD7091R_REG_CONF_MODE_MASK, conf);
95 	if (ret)
96 		return ret;
97 
98 	st->mode = mode;
99 
100 	return 0;
101 }
102 
ad7091r_set_channel(struct ad7091r_state * st,unsigned int channel)103 static int ad7091r_set_channel(struct ad7091r_state *st, unsigned int channel)
104 {
105 	unsigned int dummy;
106 	int ret;
107 
108 	/* AD7091R_REG_CHANNEL specified which channels to be converted */
109 	ret = regmap_write(st->map, AD7091R_REG_CHANNEL,
110 			BIT(channel) | (BIT(channel) << 8));
111 	if (ret)
112 		return ret;
113 
114 	/*
115 	 * There is a latency of one conversion before the channel conversion
116 	 * sequence is updated
117 	 */
118 	return regmap_read(st->map, AD7091R_REG_RESULT, &dummy);
119 }
120 
ad7091r_read_one(struct iio_dev * iio_dev,unsigned int channel,unsigned int * read_val)121 static int ad7091r_read_one(struct iio_dev *iio_dev,
122 		unsigned int channel, unsigned int *read_val)
123 {
124 	struct ad7091r_state *st = iio_priv(iio_dev);
125 	unsigned int val;
126 	int ret;
127 
128 	ret = ad7091r_set_channel(st, channel);
129 	if (ret)
130 		return ret;
131 
132 	ret = regmap_read(st->map, AD7091R_REG_RESULT, &val);
133 	if (ret)
134 		return ret;
135 
136 	if (AD7091R_REG_RESULT_CH_ID(val) != channel)
137 		return -EIO;
138 
139 	*read_val = AD7091R_REG_RESULT_CONV_RESULT(val);
140 
141 	return 0;
142 }
143 
ad7091r_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)144 static int ad7091r_read_raw(struct iio_dev *iio_dev,
145 			   struct iio_chan_spec const *chan,
146 			   int *val, int *val2, long m)
147 {
148 	struct ad7091r_state *st = iio_priv(iio_dev);
149 	unsigned int read_val;
150 	int ret;
151 
152 	mutex_lock(&st->lock);
153 
154 	switch (m) {
155 	case IIO_CHAN_INFO_RAW:
156 		if (st->mode != AD7091R_MODE_COMMAND) {
157 			ret = -EBUSY;
158 			goto unlock;
159 		}
160 
161 		ret = ad7091r_read_one(iio_dev, chan->channel, &read_val);
162 		if (ret)
163 			goto unlock;
164 
165 		*val = read_val;
166 		ret = IIO_VAL_INT;
167 		break;
168 
169 	case IIO_CHAN_INFO_SCALE:
170 		if (st->vref) {
171 			ret = regulator_get_voltage(st->vref);
172 			if (ret < 0)
173 				goto unlock;
174 
175 			*val = ret / 1000;
176 		} else {
177 			*val = st->chip_info->vref_mV;
178 		}
179 
180 		*val2 = chan->scan_type.realbits;
181 		ret = IIO_VAL_FRACTIONAL_LOG2;
182 		break;
183 
184 	default:
185 		ret = -EINVAL;
186 		break;
187 	}
188 
189 unlock:
190 	mutex_unlock(&st->lock);
191 	return ret;
192 }
193 
ad7091r_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)194 static int ad7091r_read_event_config(struct iio_dev *indio_dev,
195 				     const struct iio_chan_spec *chan,
196 				     enum iio_event_type type,
197 				     enum iio_event_direction dir)
198 {
199 	struct ad7091r_state *st = iio_priv(indio_dev);
200 	int val, ret;
201 
202 	switch (dir) {
203 	case IIO_EV_DIR_RISING:
204 		ret = regmap_read(st->map,
205 				  AD7091R_REG_CH_HIGH_LIMIT(chan->channel),
206 				  &val);
207 		if (ret)
208 			return ret;
209 		return val != AD7091R_HIGH_LIMIT;
210 	case IIO_EV_DIR_FALLING:
211 		ret = regmap_read(st->map,
212 				  AD7091R_REG_CH_LOW_LIMIT(chan->channel),
213 				  &val);
214 		if (ret)
215 			return ret;
216 		return val != AD7091R_LOW_LIMIT;
217 	default:
218 		return -EINVAL;
219 	}
220 }
221 
ad7091r_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)222 static int ad7091r_write_event_config(struct iio_dev *indio_dev,
223 				      const struct iio_chan_spec *chan,
224 				      enum iio_event_type type,
225 				      enum iio_event_direction dir, int state)
226 {
227 	struct ad7091r_state *st = iio_priv(indio_dev);
228 
229 	if (state) {
230 		return regmap_set_bits(st->map, AD7091R_REG_CONF,
231 				       AD7091R_REG_CONF_ALERT_EN);
232 	} else {
233 		/*
234 		 * Set thresholds either to 0 or to 2^12 - 1 as appropriate to
235 		 * prevent alerts and thus disable event generation.
236 		 */
237 		switch (dir) {
238 		case IIO_EV_DIR_RISING:
239 			return regmap_write(st->map,
240 					    AD7091R_REG_CH_HIGH_LIMIT(chan->channel),
241 					    AD7091R_HIGH_LIMIT);
242 		case IIO_EV_DIR_FALLING:
243 			return regmap_write(st->map,
244 					    AD7091R_REG_CH_LOW_LIMIT(chan->channel),
245 					    AD7091R_LOW_LIMIT);
246 		default:
247 			return -EINVAL;
248 		}
249 	}
250 }
251 
ad7091r_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)252 static int ad7091r_read_event_value(struct iio_dev *indio_dev,
253 				    const struct iio_chan_spec *chan,
254 				    enum iio_event_type type,
255 				    enum iio_event_direction dir,
256 				    enum iio_event_info info, int *val, int *val2)
257 {
258 	struct ad7091r_state *st = iio_priv(indio_dev);
259 	int ret;
260 
261 	switch (info) {
262 	case IIO_EV_INFO_VALUE:
263 		switch (dir) {
264 		case IIO_EV_DIR_RISING:
265 			ret = regmap_read(st->map,
266 					  AD7091R_REG_CH_HIGH_LIMIT(chan->channel),
267 					  val);
268 			if (ret)
269 				return ret;
270 			return IIO_VAL_INT;
271 		case IIO_EV_DIR_FALLING:
272 			ret = regmap_read(st->map,
273 					  AD7091R_REG_CH_LOW_LIMIT(chan->channel),
274 					  val);
275 			if (ret)
276 				return ret;
277 			return IIO_VAL_INT;
278 		default:
279 			return -EINVAL;
280 		}
281 	case IIO_EV_INFO_HYSTERESIS:
282 		ret = regmap_read(st->map,
283 				  AD7091R_REG_CH_HYSTERESIS(chan->channel),
284 				  val);
285 		if (ret)
286 			return ret;
287 		return IIO_VAL_INT;
288 	default:
289 		return -EINVAL;
290 	}
291 }
292 
ad7091r_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)293 static int ad7091r_write_event_value(struct iio_dev *indio_dev,
294 				     const struct iio_chan_spec *chan,
295 				     enum iio_event_type type,
296 				     enum iio_event_direction dir,
297 				     enum iio_event_info info, int val, int val2)
298 {
299 	struct ad7091r_state *st = iio_priv(indio_dev);
300 
301 	switch (info) {
302 	case IIO_EV_INFO_VALUE:
303 		switch (dir) {
304 		case IIO_EV_DIR_RISING:
305 			return regmap_write(st->map,
306 					    AD7091R_REG_CH_HIGH_LIMIT(chan->channel),
307 					    val);
308 		case IIO_EV_DIR_FALLING:
309 			return regmap_write(st->map,
310 					    AD7091R_REG_CH_LOW_LIMIT(chan->channel),
311 					    val);
312 		default:
313 			return -EINVAL;
314 		}
315 	case IIO_EV_INFO_HYSTERESIS:
316 		return regmap_write(st->map,
317 				    AD7091R_REG_CH_HYSTERESIS(chan->channel),
318 				    val);
319 	default:
320 		return -EINVAL;
321 	}
322 }
323 
324 static const struct iio_info ad7091r_info = {
325 	.read_raw = ad7091r_read_raw,
326 	.read_event_config = &ad7091r_read_event_config,
327 	.write_event_config = &ad7091r_write_event_config,
328 	.read_event_value = &ad7091r_read_event_value,
329 	.write_event_value = &ad7091r_write_event_value,
330 };
331 
ad7091r_event_handler(int irq,void * private)332 static irqreturn_t ad7091r_event_handler(int irq, void *private)
333 {
334 	struct iio_dev *iio_dev = private;
335 	struct ad7091r_state *st = iio_priv(iio_dev);
336 	unsigned int i, read_val;
337 	int ret;
338 	s64 timestamp = iio_get_time_ns(iio_dev);
339 
340 	ret = regmap_read(st->map, AD7091R_REG_ALERT, &read_val);
341 	if (ret)
342 		return IRQ_HANDLED;
343 
344 	for (i = 0; i < st->chip_info->num_channels; i++) {
345 		if (read_val & BIT(i * 2))
346 			iio_push_event(iio_dev,
347 					IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
348 						IIO_EV_TYPE_THRESH,
349 						IIO_EV_DIR_RISING), timestamp);
350 		if (read_val & BIT(i * 2 + 1))
351 			iio_push_event(iio_dev,
352 					IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
353 						IIO_EV_TYPE_THRESH,
354 						IIO_EV_DIR_FALLING), timestamp);
355 	}
356 
357 	return IRQ_HANDLED;
358 }
359 
ad7091r_remove(void * data)360 static void ad7091r_remove(void *data)
361 {
362 	struct ad7091r_state *st = data;
363 
364 	regulator_disable(st->vref);
365 }
366 
ad7091r_probe(struct device * dev,const char * name,const struct ad7091r_chip_info * chip_info,struct regmap * map,int irq)367 int ad7091r_probe(struct device *dev, const char *name,
368 		const struct ad7091r_chip_info *chip_info,
369 		struct regmap *map, int irq)
370 {
371 	struct iio_dev *iio_dev;
372 	struct ad7091r_state *st;
373 	int ret;
374 
375 	iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
376 	if (!iio_dev)
377 		return -ENOMEM;
378 
379 	st = iio_priv(iio_dev);
380 	st->dev = dev;
381 	st->chip_info = chip_info;
382 	st->map = map;
383 
384 	iio_dev->name = name;
385 	iio_dev->info = &ad7091r_info;
386 	iio_dev->modes = INDIO_DIRECT_MODE;
387 
388 	iio_dev->num_channels = chip_info->num_channels;
389 	iio_dev->channels = chip_info->channels;
390 
391 	if (irq) {
392 		ret = regmap_update_bits(st->map, AD7091R_REG_CONF,
393 					 AD7091R_REG_CONF_ALERT_EN, BIT(4));
394 		if (ret)
395 			return ret;
396 
397 		ret = devm_request_threaded_irq(dev, irq, NULL,
398 				ad7091r_event_handler,
399 				IRQF_TRIGGER_FALLING | IRQF_ONESHOT, name, iio_dev);
400 		if (ret)
401 			return ret;
402 	}
403 
404 	st->vref = devm_regulator_get_optional(dev, "vref");
405 	if (IS_ERR(st->vref)) {
406 		if (PTR_ERR(st->vref) == -EPROBE_DEFER)
407 			return -EPROBE_DEFER;
408 
409 		st->vref = NULL;
410 		/* Enable internal vref */
411 		ret = regmap_set_bits(st->map, AD7091R_REG_CONF,
412 				      AD7091R_REG_CONF_INT_VREF);
413 		if (ret)
414 			return dev_err_probe(st->dev, ret,
415 					     "Error on enable internal reference\n");
416 	} else {
417 		ret = regulator_enable(st->vref);
418 		if (ret)
419 			return ret;
420 		ret = devm_add_action_or_reset(dev, ad7091r_remove, st);
421 		if (ret)
422 			return ret;
423 	}
424 
425 	/* Use command mode by default to convert only desired channels*/
426 	ret = ad7091r_set_mode(st, AD7091R_MODE_COMMAND);
427 	if (ret)
428 		return ret;
429 
430 	return devm_iio_device_register(dev, iio_dev);
431 }
432 EXPORT_SYMBOL_NS_GPL(ad7091r_probe, IIO_AD7091R);
433 
ad7091r_writeable_reg(struct device * dev,unsigned int reg)434 static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)
435 {
436 	switch (reg) {
437 	case AD7091R_REG_RESULT:
438 	case AD7091R_REG_ALERT:
439 		return false;
440 	default:
441 		return true;
442 	}
443 }
444 
ad7091r_volatile_reg(struct device * dev,unsigned int reg)445 static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)
446 {
447 	switch (reg) {
448 	case AD7091R_REG_RESULT:
449 	case AD7091R_REG_ALERT:
450 		return true;
451 	default:
452 		return false;
453 	}
454 }
455 
456 const struct regmap_config ad7091r_regmap_config = {
457 	.reg_bits = 8,
458 	.val_bits = 16,
459 	.writeable_reg = ad7091r_writeable_reg,
460 	.volatile_reg = ad7091r_volatile_reg,
461 };
462 EXPORT_SYMBOL_NS_GPL(ad7091r_regmap_config, IIO_AD7091R);
463 
464 MODULE_AUTHOR("Beniamin Bia <beniamin.bia@analog.com>");
465 MODULE_DESCRIPTION("Analog Devices AD7091Rx multi-channel converters");
466 MODULE_LICENSE("GPL v2");
467