xref: /openbmc/linux/sound/soc/amd/ps/acp63.h (revision 322a163e)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * AMD ALSA SoC PDM Driver
4  *
5  * Copyright (C) 2022, 2023 Advanced Micro Devices, Inc. All rights reserved.
6  */
7 
8 #include <sound/acp63_chip_offset_byte.h>
9 
10 #define ACP_DEVICE_ID 0x15E2
11 #define ACP63_REG_START		0x1240000
12 #define ACP63_REG_END		0x1250200
13 #define ACP63_DEVS		5
14 
15 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001
16 #define ACP_PGFSM_CNTL_POWER_ON_MASK	1
17 #define ACP_PGFSM_CNTL_POWER_OFF_MASK	0
18 #define ACP_PGFSM_STATUS_MASK		3
19 #define ACP_POWERED_ON			0
20 #define ACP_POWER_ON_IN_PROGRESS	1
21 #define ACP_POWERED_OFF		2
22 #define ACP_POWER_OFF_IN_PROGRESS	3
23 
24 #define ACP_ERROR_MASK 0x20000000
25 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
26 #define PDM_DMA_STAT 0x10
27 
28 #define PDM_DMA_INTR_MASK	0x10000
29 #define ACP_ERROR_STAT	29
30 #define PDM_DECIMATION_FACTOR	2
31 #define ACP_PDM_CLK_FREQ_MASK	7
32 #define ACP_WOV_GAIN_CONTROL	GENMASK(4, 3)
33 #define ACP_PDM_ENABLE		1
34 #define ACP_PDM_DISABLE		0
35 #define ACP_PDM_DMA_EN_STATUS	2
36 #define TWO_CH		2
37 #define DELAY_US	5
38 #define ACP_COUNTER	20000
39 
40 #define ACP_SRAM_PTE_OFFSET	0x03800000
41 #define PAGE_SIZE_4K_ENABLE	2
42 #define PDM_PTE_OFFSET		0
43 #define PDM_MEM_WINDOW_START	0x4000000
44 
45 #define CAPTURE_MIN_NUM_PERIODS     4
46 #define CAPTURE_MAX_NUM_PERIODS     4
47 #define CAPTURE_MAX_PERIOD_SIZE     8192
48 #define CAPTURE_MIN_PERIOD_SIZE     4096
49 
50 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
51 #define MIN_BUFFER MAX_BUFFER
52 
53 /* time in ms for runtime suspend delay */
54 #define ACP_SUSPEND_DELAY_MS	2000
55 
56 #define ACP_DMIC_DEV	2
57 
58 /* ACP63_PDM_MODE_DEVS corresponds to platform devices count for ACP PDM configuration */
59 #define ACP63_PDM_MODE_DEVS		3
60 
61 /*
62  * ACP63_SDW0_MODE_DEVS corresponds to platform devices count for
63  * SW0 SoundWire manager instance configuration
64  */
65 #define ACP63_SDW0_MODE_DEVS		2
66 
67 /*
68  * ACP63_SDW0_SDW1_MODE_DEVS corresponds to platform devices count for SW0 + SW1 SoundWire manager
69  * instances configuration
70  */
71 #define ACP63_SDW0_SDW1_MODE_DEVS	3
72 
73 /*
74  * ACP63_SDW0_PDM_MODE_DEVS corresponds to platform devices count for SW0 manager
75  * instance + ACP PDM controller configuration
76  */
77 #define ACP63_SDW0_PDM_MODE_DEVS	4
78 
79 /*
80  * ACP63_SDW0_SDW1_PDM_MODE_DEVS corresponds to platform devices count for
81  * SW0 + SW1 SoundWire manager instances + ACP PDM controller configuration
82  */
83 #define ACP63_SDW0_SDW1_PDM_MODE_DEVS   5
84 #define ACP63_DMIC_ADDR			2
85 #define ACP63_SDW_ADDR			5
86 #define AMD_SDW_MAX_MANAGERS		2
87 
88 /* time in ms for acp timeout */
89 #define ACP_TIMEOUT		500
90 
91 /* ACP63_PDM_DEV_CONFIG corresponds to platform device configuration for ACP PDM controller */
92 #define ACP63_PDM_DEV_CONFIG		BIT(0)
93 
94 /* ACP63_SDW_DEV_CONFIG corresponds to platform device configuration for SDW manager instances */
95 #define ACP63_SDW_DEV_CONFIG		BIT(1)
96 
97 /*
98  * ACP63_SDW_PDM_DEV_CONFIG corresponds to platform device configuration for ACP PDM + SoundWire
99  * manager instance combination.
100  */
101 #define ACP63_SDW_PDM_DEV_CONFIG	GENMASK(1, 0)
102 #define ACP_SDW0_STAT			BIT(21)
103 #define ACP_SDW1_STAT			BIT(2)
104 #define ACP_ERROR_IRQ			BIT(29)
105 
106 #define ACP_AUDIO0_TX_THRESHOLD		0x1c
107 #define ACP_AUDIO1_TX_THRESHOLD		0x1a
108 #define ACP_AUDIO2_TX_THRESHOLD		0x18
109 #define ACP_AUDIO0_RX_THRESHOLD		0x1b
110 #define ACP_AUDIO1_RX_THRESHOLD		0x19
111 #define ACP_AUDIO2_RX_THRESHOLD		0x17
112 #define ACP_P1_AUDIO1_TX_THRESHOLD	BIT(6)
113 #define ACP_P1_AUDIO1_RX_THRESHOLD	BIT(5)
114 #define ACP_SDW_DMA_IRQ_MASK		0x1F800000
115 #define ACP_P1_SDW_DMA_IRQ_MASK		0x60
116 #define ACP63_SDW0_DMA_MAX_STREAMS	6
117 #define ACP63_SDW1_DMA_MAX_STREAMS	2
118 #define ACP_P1_AUDIO_TX_THRESHOLD	6
119 
120 /*
121  * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping
122  * in ACP_EXTENAL_INTR_CNTL register.
123  * Stream id		IRQ Bit
124  * 0 (SDW0_AUDIO0_TX)	28
125  * 1 (SDW0_AUDIO1_TX)	26
126  * 2 (SDW0_AUDIO2_TX)	24
127  * 3 (SDW0_AUDIO0_RX)	27
128  * 4 (SDW0_AUDIO1_RX)	25
129  * 5 (SDW0_AUDIO2_RX)	23
130  */
131 #define SDW0_DMA_TX_IRQ_MASK(i)	(ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
132 #define SDW0_DMA_RX_IRQ_MASK(i)	(ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
133 
134 /*
135  * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
136  * in ACP_EXTENAL_INTR_CNTL1 register.
137  * Stream id		IRQ Bit
138  * 0 (SDW1_AUDIO1_TX)	6
139  * 1 (SDW1_AUDIO1_RX)	5
140  */
141 #define SDW1_DMA_IRQ_MASK(i)	(ACP_P1_AUDIO_TX_THRESHOLD - (i))
142 
143 #define ACP_DELAY_US		5
144 #define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024)
145 #define SDW0_MEM_WINDOW_START	0x4800000
146 #define ACP_SDW_SRAM_PTE_OFFSET	0x03800400
147 #define SDW0_PTE_OFFSET		0x400
148 #define SDW_FIFO_SIZE		0x100
149 #define SDW_DMA_SIZE		0x40
150 #define ACP_SDW0_FIFO_OFFSET	0x100
151 #define ACP_SDW_PTE_OFFSET	0x100
152 #define SDW_FIFO_OFFSET		0x100
153 #define SDW_PTE_OFFSET(i)	(SDW0_PTE_OFFSET + ((i) * 0x600))
154 #define ACP_SDW_FIFO_OFFSET(i)	(ACP_SDW0_FIFO_OFFSET + ((i) * 0x500))
155 #define SDW_MEM_WINDOW_START(i)	(SDW0_MEM_WINDOW_START + ((i) * 0xC0000))
156 
157 #define SDW_PLAYBACK_MIN_NUM_PERIODS    2
158 #define SDW_PLAYBACK_MAX_NUM_PERIODS    8
159 #define SDW_PLAYBACK_MAX_PERIOD_SIZE    8192
160 #define SDW_PLAYBACK_MIN_PERIOD_SIZE    1024
161 #define SDW_CAPTURE_MIN_NUM_PERIODS     2
162 #define SDW_CAPTURE_MAX_NUM_PERIODS     8
163 #define SDW_CAPTURE_MAX_PERIOD_SIZE     8192
164 #define SDW_CAPTURE_MIN_PERIOD_SIZE     1024
165 
166 #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS)
167 #define SDW_MIN_BUFFER SDW_MAX_BUFFER
168 
169 enum acp_config {
170 	ACP_CONFIG_0 = 0,
171 	ACP_CONFIG_1,
172 	ACP_CONFIG_2,
173 	ACP_CONFIG_3,
174 	ACP_CONFIG_4,
175 	ACP_CONFIG_5,
176 	ACP_CONFIG_6,
177 	ACP_CONFIG_7,
178 	ACP_CONFIG_8,
179 	ACP_CONFIG_9,
180 	ACP_CONFIG_10,
181 	ACP_CONFIG_11,
182 	ACP_CONFIG_12,
183 	ACP_CONFIG_13,
184 	ACP_CONFIG_14,
185 	ACP_CONFIG_15,
186 };
187 
188 enum amd_sdw0_channel {
189 	ACP_SDW0_AUDIO0_TX = 0,
190 	ACP_SDW0_AUDIO1_TX,
191 	ACP_SDW0_AUDIO2_TX,
192 	ACP_SDW0_AUDIO0_RX,
193 	ACP_SDW0_AUDIO1_RX,
194 	ACP_SDW0_AUDIO2_RX,
195 };
196 
197 enum amd_sdw1_channel {
198 	ACP_SDW1_AUDIO1_TX,
199 	ACP_SDW1_AUDIO1_RX,
200 };
201 
202 struct pdm_stream_instance {
203 	u16 num_pages;
204 	u16 channels;
205 	dma_addr_t dma_addr;
206 	u64 bytescount;
207 	void __iomem *acp63_base;
208 };
209 
210 struct pdm_dev_data {
211 	u32 pdm_irq;
212 	void __iomem *acp63_base;
213 	struct mutex *acp_lock;
214 	struct snd_pcm_substream *capture_stream;
215 };
216 
217 struct sdw_dma_dev_data {
218 	void __iomem *acp_base;
219 	struct mutex *acp_lock; /* used to protect acp common register access */
220 	struct snd_pcm_substream *sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];
221 	struct snd_pcm_substream *sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];
222 };
223 
224 struct acp_sdw_dma_stream {
225 	u16 num_pages;
226 	u16 channels;
227 	u32 stream_id;
228 	u32 instance;
229 	dma_addr_t dma_addr;
230 	u64 bytescount;
231 };
232 
233 union acp_sdw_dma_count {
234 	struct {
235 		u32 low;
236 		u32 high;
237 	} bcount;
238 	u64 bytescount;
239 };
240 
241 struct sdw_dma_ring_buf_reg {
242 	u32 reg_dma_size;
243 	u32 reg_fifo_addr;
244 	u32 reg_fifo_size;
245 	u32 reg_ring_buf_size;
246 	u32 reg_ring_buf_addr;
247 	u32 water_mark_size_reg;
248 	u32 pos_low_reg;
249 	u32 pos_high_reg;
250 };
251 
252 /**
253  * struct acp63_dev_data - acp pci driver context
254  * @acp63_base: acp mmio base
255  * @res: resource
256  * @pdev: array of child platform device node structures
257  * @acp_lock: used to protect acp common registers
258  * @sdw_fw_node: SoundWire controller fw node handle
259  * @pdev_config: platform device configuration
260  * @pdev_count: platform devices count
261  * @pdm_dev_index: pdm platform device index
262  * @sdw_manager_count: SoundWire manager instance count
263  * @sdw0_dev_index: SoundWire Manager-0 platform device index
264  * @sdw1_dev_index: SoundWire Manager-1 platform device index
265  * @sdw_dma_dev_index: SoundWire DMA controller platform device index
266  * @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance
267  * @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance
268  * @acp_reset: flag set to true when bus reset is applied across all
269  * the active SoundWire manager instances
270  */
271 
272 struct acp63_dev_data {
273 	void __iomem *acp63_base;
274 	struct resource *res;
275 	struct platform_device *pdev[ACP63_DEVS];
276 	struct mutex acp_lock; /* protect shared registers */
277 	struct fwnode_handle *sdw_fw_node;
278 	u16 pdev_config;
279 	u16 pdev_count;
280 	u16 pdm_dev_index;
281 	u8 sdw_manager_count;
282 	u16 sdw0_dev_index;
283 	u16 sdw1_dev_index;
284 	u16 sdw_dma_dev_index;
285 	u16 sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS];
286 	u16 sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS];
287 	bool acp_reset;
288 };
289 
290 int snd_amd_acp_find_config(struct pci_dev *pci);
291