1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
5 *
6 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 */
8 #ifndef __ASM_INSN_H
9 #define __ASM_INSN_H
10 #include <linux/build_bug.h>
11 #include <linux/types.h>
12
13 #include <asm/insn-def.h>
14
15 #ifndef __ASSEMBLY__
16
17 enum aarch64_insn_hint_cr_op {
18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
24
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
29 AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
30 AARCH64_INSN_HINT_PACIAZ = 0x18 << 5,
31 AARCH64_INSN_HINT_PACIASP = 0x19 << 5,
32 AARCH64_INSN_HINT_PACIBZ = 0x1A << 5,
33 AARCH64_INSN_HINT_PACIBSP = 0x1B << 5,
34 AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5,
35 AARCH64_INSN_HINT_AUTIASP = 0x1D << 5,
36 AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5,
37 AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5,
38
39 AARCH64_INSN_HINT_ESB = 0x10 << 5,
40 AARCH64_INSN_HINT_PSB = 0x11 << 5,
41 AARCH64_INSN_HINT_TSB = 0x12 << 5,
42 AARCH64_INSN_HINT_CSDB = 0x14 << 5,
43 AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
44
45 AARCH64_INSN_HINT_BTI = 0x20 << 5,
46 AARCH64_INSN_HINT_BTIC = 0x22 << 5,
47 AARCH64_INSN_HINT_BTIJ = 0x24 << 5,
48 AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
49 };
50
51 enum aarch64_insn_imm_type {
52 AARCH64_INSN_IMM_ADR,
53 AARCH64_INSN_IMM_26,
54 AARCH64_INSN_IMM_19,
55 AARCH64_INSN_IMM_16,
56 AARCH64_INSN_IMM_14,
57 AARCH64_INSN_IMM_12,
58 AARCH64_INSN_IMM_9,
59 AARCH64_INSN_IMM_7,
60 AARCH64_INSN_IMM_6,
61 AARCH64_INSN_IMM_S,
62 AARCH64_INSN_IMM_R,
63 AARCH64_INSN_IMM_N,
64 AARCH64_INSN_IMM_MAX
65 };
66
67 enum aarch64_insn_register_type {
68 AARCH64_INSN_REGTYPE_RT,
69 AARCH64_INSN_REGTYPE_RN,
70 AARCH64_INSN_REGTYPE_RT2,
71 AARCH64_INSN_REGTYPE_RM,
72 AARCH64_INSN_REGTYPE_RD,
73 AARCH64_INSN_REGTYPE_RA,
74 AARCH64_INSN_REGTYPE_RS,
75 };
76
77 enum aarch64_insn_register {
78 AARCH64_INSN_REG_0 = 0,
79 AARCH64_INSN_REG_1 = 1,
80 AARCH64_INSN_REG_2 = 2,
81 AARCH64_INSN_REG_3 = 3,
82 AARCH64_INSN_REG_4 = 4,
83 AARCH64_INSN_REG_5 = 5,
84 AARCH64_INSN_REG_6 = 6,
85 AARCH64_INSN_REG_7 = 7,
86 AARCH64_INSN_REG_8 = 8,
87 AARCH64_INSN_REG_9 = 9,
88 AARCH64_INSN_REG_10 = 10,
89 AARCH64_INSN_REG_11 = 11,
90 AARCH64_INSN_REG_12 = 12,
91 AARCH64_INSN_REG_13 = 13,
92 AARCH64_INSN_REG_14 = 14,
93 AARCH64_INSN_REG_15 = 15,
94 AARCH64_INSN_REG_16 = 16,
95 AARCH64_INSN_REG_17 = 17,
96 AARCH64_INSN_REG_18 = 18,
97 AARCH64_INSN_REG_19 = 19,
98 AARCH64_INSN_REG_20 = 20,
99 AARCH64_INSN_REG_21 = 21,
100 AARCH64_INSN_REG_22 = 22,
101 AARCH64_INSN_REG_23 = 23,
102 AARCH64_INSN_REG_24 = 24,
103 AARCH64_INSN_REG_25 = 25,
104 AARCH64_INSN_REG_26 = 26,
105 AARCH64_INSN_REG_27 = 27,
106 AARCH64_INSN_REG_28 = 28,
107 AARCH64_INSN_REG_29 = 29,
108 AARCH64_INSN_REG_FP = 29, /* Frame pointer */
109 AARCH64_INSN_REG_30 = 30,
110 AARCH64_INSN_REG_LR = 30, /* Link register */
111 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
112 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
113 };
114
115 enum aarch64_insn_special_register {
116 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
117 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
118 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
119 AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
120 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
121 AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
122 AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
123 AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
124 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
125 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
126 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
127 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
128 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
129 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
130 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
131 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
132 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
133 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
134 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
135 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
136 };
137
138 enum aarch64_insn_variant {
139 AARCH64_INSN_VARIANT_32BIT,
140 AARCH64_INSN_VARIANT_64BIT
141 };
142
143 enum aarch64_insn_condition {
144 AARCH64_INSN_COND_EQ = 0x0, /* == */
145 AARCH64_INSN_COND_NE = 0x1, /* != */
146 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
147 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
148 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
149 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
150 AARCH64_INSN_COND_VS = 0x6, /* overflow */
151 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
152 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
153 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
154 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
155 AARCH64_INSN_COND_LT = 0xb, /* signed < */
156 AARCH64_INSN_COND_GT = 0xc, /* signed > */
157 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
158 AARCH64_INSN_COND_AL = 0xe, /* always */
159 };
160
161 enum aarch64_insn_branch_type {
162 AARCH64_INSN_BRANCH_NOLINK,
163 AARCH64_INSN_BRANCH_LINK,
164 AARCH64_INSN_BRANCH_RETURN,
165 AARCH64_INSN_BRANCH_COMP_ZERO,
166 AARCH64_INSN_BRANCH_COMP_NONZERO,
167 };
168
169 enum aarch64_insn_size_type {
170 AARCH64_INSN_SIZE_8,
171 AARCH64_INSN_SIZE_16,
172 AARCH64_INSN_SIZE_32,
173 AARCH64_INSN_SIZE_64,
174 };
175
176 enum aarch64_insn_ldst_type {
177 AARCH64_INSN_LDST_LOAD_REG_OFFSET,
178 AARCH64_INSN_LDST_STORE_REG_OFFSET,
179 AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
180 AARCH64_INSN_LDST_STORE_IMM_OFFSET,
181 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
182 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
183 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
184 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
185 AARCH64_INSN_LDST_LOAD_EX,
186 AARCH64_INSN_LDST_LOAD_ACQ_EX,
187 AARCH64_INSN_LDST_STORE_EX,
188 AARCH64_INSN_LDST_STORE_REL_EX,
189 AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,
190 AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET,
191 };
192
193 enum aarch64_insn_adsb_type {
194 AARCH64_INSN_ADSB_ADD,
195 AARCH64_INSN_ADSB_SUB,
196 AARCH64_INSN_ADSB_ADD_SETFLAGS,
197 AARCH64_INSN_ADSB_SUB_SETFLAGS
198 };
199
200 enum aarch64_insn_movewide_type {
201 AARCH64_INSN_MOVEWIDE_ZERO,
202 AARCH64_INSN_MOVEWIDE_KEEP,
203 AARCH64_INSN_MOVEWIDE_INVERSE
204 };
205
206 enum aarch64_insn_bitfield_type {
207 AARCH64_INSN_BITFIELD_MOVE,
208 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
209 AARCH64_INSN_BITFIELD_MOVE_SIGNED
210 };
211
212 enum aarch64_insn_data1_type {
213 AARCH64_INSN_DATA1_REVERSE_16,
214 AARCH64_INSN_DATA1_REVERSE_32,
215 AARCH64_INSN_DATA1_REVERSE_64,
216 };
217
218 enum aarch64_insn_data2_type {
219 AARCH64_INSN_DATA2_UDIV,
220 AARCH64_INSN_DATA2_SDIV,
221 AARCH64_INSN_DATA2_LSLV,
222 AARCH64_INSN_DATA2_LSRV,
223 AARCH64_INSN_DATA2_ASRV,
224 AARCH64_INSN_DATA2_RORV,
225 };
226
227 enum aarch64_insn_data3_type {
228 AARCH64_INSN_DATA3_MADD,
229 AARCH64_INSN_DATA3_MSUB,
230 };
231
232 enum aarch64_insn_logic_type {
233 AARCH64_INSN_LOGIC_AND,
234 AARCH64_INSN_LOGIC_BIC,
235 AARCH64_INSN_LOGIC_ORR,
236 AARCH64_INSN_LOGIC_ORN,
237 AARCH64_INSN_LOGIC_EOR,
238 AARCH64_INSN_LOGIC_EON,
239 AARCH64_INSN_LOGIC_AND_SETFLAGS,
240 AARCH64_INSN_LOGIC_BIC_SETFLAGS
241 };
242
243 enum aarch64_insn_prfm_type {
244 AARCH64_INSN_PRFM_TYPE_PLD,
245 AARCH64_INSN_PRFM_TYPE_PLI,
246 AARCH64_INSN_PRFM_TYPE_PST,
247 };
248
249 enum aarch64_insn_prfm_target {
250 AARCH64_INSN_PRFM_TARGET_L1,
251 AARCH64_INSN_PRFM_TARGET_L2,
252 AARCH64_INSN_PRFM_TARGET_L3,
253 };
254
255 enum aarch64_insn_prfm_policy {
256 AARCH64_INSN_PRFM_POLICY_KEEP,
257 AARCH64_INSN_PRFM_POLICY_STRM,
258 };
259
260 enum aarch64_insn_adr_type {
261 AARCH64_INSN_ADR_TYPE_ADRP,
262 AARCH64_INSN_ADR_TYPE_ADR,
263 };
264
265 enum aarch64_insn_mem_atomic_op {
266 AARCH64_INSN_MEM_ATOMIC_ADD,
267 AARCH64_INSN_MEM_ATOMIC_CLR,
268 AARCH64_INSN_MEM_ATOMIC_EOR,
269 AARCH64_INSN_MEM_ATOMIC_SET,
270 AARCH64_INSN_MEM_ATOMIC_SWP,
271 };
272
273 enum aarch64_insn_mem_order_type {
274 AARCH64_INSN_MEM_ORDER_NONE,
275 AARCH64_INSN_MEM_ORDER_ACQ,
276 AARCH64_INSN_MEM_ORDER_REL,
277 AARCH64_INSN_MEM_ORDER_ACQREL,
278 };
279
280 enum aarch64_insn_mb_type {
281 AARCH64_INSN_MB_SY,
282 AARCH64_INSN_MB_ST,
283 AARCH64_INSN_MB_LD,
284 AARCH64_INSN_MB_ISH,
285 AARCH64_INSN_MB_ISHST,
286 AARCH64_INSN_MB_ISHLD,
287 AARCH64_INSN_MB_NSH,
288 AARCH64_INSN_MB_NSHST,
289 AARCH64_INSN_MB_NSHLD,
290 AARCH64_INSN_MB_OSH,
291 AARCH64_INSN_MB_OSHST,
292 AARCH64_INSN_MB_OSHLD,
293 };
294
295 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \
296 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
297 { \
298 BUILD_BUG_ON(~(mask) & (val)); \
299 return (code & (mask)) == (val); \
300 } \
301 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
302 { \
303 return (val); \
304 }
305
306 /*
307 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
308 * Section C3.1 "A64 instruction index by encoding":
309 * AArch64 main encoding table
310 * Bit position
311 * 28 27 26 25 Encoding Group
312 * 0 0 - - Unallocated
313 * 1 0 0 - Data processing, immediate
314 * 1 0 1 - Branch, exception generation and system instructions
315 * - 1 - 0 Loads and stores
316 * - 1 0 1 Data processing - register
317 * 0 1 1 1 Data processing - SIMD and floating point
318 * 1 1 1 1 Data processing - SIMD and floating point
319 * "-" means "don't care"
320 */
321 __AARCH64_INSN_FUNCS(class_branch_sys, 0x1c000000, 0x14000000)
322
323 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
324 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
325 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
326 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
327 __AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
328 __AARCH64_INSN_FUNCS(load_imm, 0x3FC00000, 0x39400000)
329 __AARCH64_INSN_FUNCS(signed_load_imm, 0X3FC00000, 0x39800000)
330 __AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
331 __AARCH64_INSN_FUNCS(load_pre, 0x3FE00C00, 0x38400C00)
332 __AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400)
333 __AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
334 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
335 __AARCH64_INSN_FUNCS(str_imm, 0x3FC00000, 0x39000000)
336 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
337 __AARCH64_INSN_FUNCS(ldclr, 0x3F20FC00, 0x38201000)
338 __AARCH64_INSN_FUNCS(ldeor, 0x3F20FC00, 0x38202000)
339 __AARCH64_INSN_FUNCS(ldset, 0x3F20FC00, 0x38203000)
340 __AARCH64_INSN_FUNCS(swp, 0x3F20FC00, 0x38208000)
341 __AARCH64_INSN_FUNCS(cas, 0x3FA07C00, 0x08A07C00)
342 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
343 __AARCH64_INSN_FUNCS(signed_ldr_reg, 0X3FE0FC00, 0x38A0E800)
344 __AARCH64_INSN_FUNCS(ldr_imm, 0x3FC00000, 0x39400000)
345 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
346 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
347 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
348 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
349 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
350 __AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000)
351 __AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)
352 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
353 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
354 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
355 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
356 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
357 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
358 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
359 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
360 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
361 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
362 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
363 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
364 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
365 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
366 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
367 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
368 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
369 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
370 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
371 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
372 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
373 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
374 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
375 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
376 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
377 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
378 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
379 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
380 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
381 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
382 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
383 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
384 __AARCH64_INSN_FUNCS(mov_reg, 0x7FE0FFE0, 0x2A0003E0)
385 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
386 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
387 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
388 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
389 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
390 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
391 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
392 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
393 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
394 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
395 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
396 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
397 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
398 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
399 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
400 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
401 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
402 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
403 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
404 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
405 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
406 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
407 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
408 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
409 __AARCH64_INSN_FUNCS(br_auth, 0xFEFFF800, 0xD61F0800)
410 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
411 __AARCH64_INSN_FUNCS(blr_auth, 0xFEFFF800, 0xD63F0800)
412 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
413 __AARCH64_INSN_FUNCS(ret_auth, 0xFFFFFBFF, 0xD65F0BFF)
414 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
415 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
416 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
417 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
418 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
419 __AARCH64_INSN_FUNCS(dmb, 0xFFFFF0FF, 0xD50330BF)
420 __AARCH64_INSN_FUNCS(dsb_base, 0xFFFFF0FF, 0xD503309F)
421 __AARCH64_INSN_FUNCS(dsb_nxs, 0xFFFFF3FF, 0xD503323F)
422 __AARCH64_INSN_FUNCS(isb, 0xFFFFF0FF, 0xD50330DF)
423 __AARCH64_INSN_FUNCS(sb, 0xFFFFFFFF, 0xD50330FF)
424 __AARCH64_INSN_FUNCS(clrex, 0xFFFFF0FF, 0xD503305F)
425 __AARCH64_INSN_FUNCS(ssbb, 0xFFFFFFFF, 0xD503309F)
426 __AARCH64_INSN_FUNCS(pssbb, 0xFFFFFFFF, 0xD503349F)
427 __AARCH64_INSN_FUNCS(bti, 0xFFFFFF3F, 0xD503241f)
428
429 #undef __AARCH64_INSN_FUNCS
430
aarch64_insn_is_steppable_hint(u32 insn)431 static __always_inline bool aarch64_insn_is_steppable_hint(u32 insn)
432 {
433 if (!aarch64_insn_is_hint(insn))
434 return false;
435
436 switch (insn & 0xFE0) {
437 case AARCH64_INSN_HINT_XPACLRI:
438 case AARCH64_INSN_HINT_PACIA_1716:
439 case AARCH64_INSN_HINT_PACIB_1716:
440 case AARCH64_INSN_HINT_PACIAZ:
441 case AARCH64_INSN_HINT_PACIASP:
442 case AARCH64_INSN_HINT_PACIBZ:
443 case AARCH64_INSN_HINT_PACIBSP:
444 case AARCH64_INSN_HINT_BTI:
445 case AARCH64_INSN_HINT_BTIC:
446 case AARCH64_INSN_HINT_BTIJ:
447 case AARCH64_INSN_HINT_BTIJC:
448 case AARCH64_INSN_HINT_NOP:
449 return true;
450 default:
451 return false;
452 }
453 }
454
aarch64_insn_is_branch(u32 insn)455 static __always_inline bool aarch64_insn_is_branch(u32 insn)
456 {
457 /* b, bl, cb*, tb*, ret*, b.cond, br*, blr* */
458
459 return aarch64_insn_is_b(insn) ||
460 aarch64_insn_is_bl(insn) ||
461 aarch64_insn_is_cbz(insn) ||
462 aarch64_insn_is_cbnz(insn) ||
463 aarch64_insn_is_tbz(insn) ||
464 aarch64_insn_is_tbnz(insn) ||
465 aarch64_insn_is_ret(insn) ||
466 aarch64_insn_is_ret_auth(insn) ||
467 aarch64_insn_is_br(insn) ||
468 aarch64_insn_is_br_auth(insn) ||
469 aarch64_insn_is_blr(insn) ||
470 aarch64_insn_is_blr_auth(insn) ||
471 aarch64_insn_is_bcond(insn);
472 }
473
aarch64_insn_is_branch_imm(u32 insn)474 static __always_inline bool aarch64_insn_is_branch_imm(u32 insn)
475 {
476 return aarch64_insn_is_b(insn) ||
477 aarch64_insn_is_bl(insn) ||
478 aarch64_insn_is_tbz(insn) ||
479 aarch64_insn_is_tbnz(insn) ||
480 aarch64_insn_is_cbz(insn) ||
481 aarch64_insn_is_cbnz(insn) ||
482 aarch64_insn_is_bcond(insn);
483 }
484
aarch64_insn_is_adr_adrp(u32 insn)485 static __always_inline bool aarch64_insn_is_adr_adrp(u32 insn)
486 {
487 return aarch64_insn_is_adr(insn) ||
488 aarch64_insn_is_adrp(insn);
489 }
490
aarch64_insn_is_dsb(u32 insn)491 static __always_inline bool aarch64_insn_is_dsb(u32 insn)
492 {
493 return aarch64_insn_is_dsb_base(insn) ||
494 aarch64_insn_is_dsb_nxs(insn);
495 }
496
aarch64_insn_is_barrier(u32 insn)497 static __always_inline bool aarch64_insn_is_barrier(u32 insn)
498 {
499 return aarch64_insn_is_dmb(insn) ||
500 aarch64_insn_is_dsb(insn) ||
501 aarch64_insn_is_isb(insn) ||
502 aarch64_insn_is_sb(insn) ||
503 aarch64_insn_is_clrex(insn) ||
504 aarch64_insn_is_ssbb(insn) ||
505 aarch64_insn_is_pssbb(insn);
506 }
507
aarch64_insn_is_store_single(u32 insn)508 static __always_inline bool aarch64_insn_is_store_single(u32 insn)
509 {
510 return aarch64_insn_is_store_imm(insn) ||
511 aarch64_insn_is_store_pre(insn) ||
512 aarch64_insn_is_store_post(insn);
513 }
514
aarch64_insn_is_store_pair(u32 insn)515 static __always_inline bool aarch64_insn_is_store_pair(u32 insn)
516 {
517 return aarch64_insn_is_stp(insn) ||
518 aarch64_insn_is_stp_pre(insn) ||
519 aarch64_insn_is_stp_post(insn);
520 }
521
aarch64_insn_is_load_single(u32 insn)522 static __always_inline bool aarch64_insn_is_load_single(u32 insn)
523 {
524 return aarch64_insn_is_load_imm(insn) ||
525 aarch64_insn_is_load_pre(insn) ||
526 aarch64_insn_is_load_post(insn);
527 }
528
aarch64_insn_is_load_pair(u32 insn)529 static __always_inline bool aarch64_insn_is_load_pair(u32 insn)
530 {
531 return aarch64_insn_is_ldp(insn) ||
532 aarch64_insn_is_ldp_pre(insn) ||
533 aarch64_insn_is_ldp_post(insn);
534 }
535
aarch64_insn_uses_literal(u32 insn)536 static __always_inline bool aarch64_insn_uses_literal(u32 insn)
537 {
538 /* ldr/ldrsw (literal), prfm */
539
540 return aarch64_insn_is_ldr_lit(insn) ||
541 aarch64_insn_is_ldrsw_lit(insn) ||
542 aarch64_insn_is_adr_adrp(insn) ||
543 aarch64_insn_is_prfm_lit(insn);
544 }
545
546 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
547 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
548 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
549 u32 insn, u64 imm);
550 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
551 u32 insn);
552 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
553 enum aarch64_insn_branch_type type);
554 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
555 enum aarch64_insn_register reg,
556 enum aarch64_insn_variant variant,
557 enum aarch64_insn_branch_type type);
558 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
559 enum aarch64_insn_condition cond);
560
561 static __always_inline u32
aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)562 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
563 {
564 return aarch64_insn_get_hint_value() | op;
565 }
566
aarch64_insn_gen_nop(void)567 static __always_inline u32 aarch64_insn_gen_nop(void)
568 {
569 return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
570 }
571
572 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
573 enum aarch64_insn_branch_type type);
574 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
575 enum aarch64_insn_register base,
576 enum aarch64_insn_register offset,
577 enum aarch64_insn_size_type size,
578 enum aarch64_insn_ldst_type type);
579 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
580 enum aarch64_insn_register base,
581 unsigned int imm,
582 enum aarch64_insn_size_type size,
583 enum aarch64_insn_ldst_type type);
584 u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
585 enum aarch64_insn_register reg,
586 bool is64bit);
587 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
588 enum aarch64_insn_register reg2,
589 enum aarch64_insn_register base,
590 int offset,
591 enum aarch64_insn_variant variant,
592 enum aarch64_insn_ldst_type type);
593 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
594 enum aarch64_insn_register base,
595 enum aarch64_insn_register state,
596 enum aarch64_insn_size_type size,
597 enum aarch64_insn_ldst_type type);
598 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
599 enum aarch64_insn_register src,
600 int imm, enum aarch64_insn_variant variant,
601 enum aarch64_insn_adsb_type type);
602 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
603 enum aarch64_insn_register reg,
604 enum aarch64_insn_adr_type type);
605 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
606 enum aarch64_insn_register src,
607 int immr, int imms,
608 enum aarch64_insn_variant variant,
609 enum aarch64_insn_bitfield_type type);
610 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
611 int imm, int shift,
612 enum aarch64_insn_variant variant,
613 enum aarch64_insn_movewide_type type);
614 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
615 enum aarch64_insn_register src,
616 enum aarch64_insn_register reg,
617 int shift,
618 enum aarch64_insn_variant variant,
619 enum aarch64_insn_adsb_type type);
620 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
621 enum aarch64_insn_register src,
622 enum aarch64_insn_variant variant,
623 enum aarch64_insn_data1_type type);
624 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
625 enum aarch64_insn_register src,
626 enum aarch64_insn_register reg,
627 enum aarch64_insn_variant variant,
628 enum aarch64_insn_data2_type type);
629 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
630 enum aarch64_insn_register src,
631 enum aarch64_insn_register reg1,
632 enum aarch64_insn_register reg2,
633 enum aarch64_insn_variant variant,
634 enum aarch64_insn_data3_type type);
635 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
636 enum aarch64_insn_register src,
637 enum aarch64_insn_register reg,
638 int shift,
639 enum aarch64_insn_variant variant,
640 enum aarch64_insn_logic_type type);
641 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
642 enum aarch64_insn_register src,
643 enum aarch64_insn_variant variant);
644 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
645 enum aarch64_insn_variant variant,
646 enum aarch64_insn_register Rn,
647 enum aarch64_insn_register Rd,
648 u64 imm);
649 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
650 enum aarch64_insn_register Rm,
651 enum aarch64_insn_register Rn,
652 enum aarch64_insn_register Rd,
653 u8 lsb);
654 #ifdef CONFIG_ARM64_LSE_ATOMICS
655 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
656 enum aarch64_insn_register address,
657 enum aarch64_insn_register value,
658 enum aarch64_insn_size_type size,
659 enum aarch64_insn_mem_atomic_op op,
660 enum aarch64_insn_mem_order_type order);
661 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
662 enum aarch64_insn_register address,
663 enum aarch64_insn_register value,
664 enum aarch64_insn_size_type size,
665 enum aarch64_insn_mem_order_type order);
666 #else
667 static inline
aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_atomic_op op,enum aarch64_insn_mem_order_type order)668 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
669 enum aarch64_insn_register address,
670 enum aarch64_insn_register value,
671 enum aarch64_insn_size_type size,
672 enum aarch64_insn_mem_atomic_op op,
673 enum aarch64_insn_mem_order_type order)
674 {
675 return AARCH64_BREAK_FAULT;
676 }
677
678 static inline
aarch64_insn_gen_cas(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_order_type order)679 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
680 enum aarch64_insn_register address,
681 enum aarch64_insn_register value,
682 enum aarch64_insn_size_type size,
683 enum aarch64_insn_mem_order_type order)
684 {
685 return AARCH64_BREAK_FAULT;
686 }
687 #endif
688 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
689
690 s32 aarch64_get_branch_offset(u32 insn);
691 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
692
693 s32 aarch64_insn_adrp_get_offset(u32 insn);
694 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
695
696 bool aarch32_insn_is_wide(u32 insn);
697
698 #define A32_RN_OFFSET 16
699 #define A32_RT_OFFSET 12
700 #define A32_RT2_OFFSET 0
701
702 u32 aarch64_insn_extract_system_reg(u32 insn);
703 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
704 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
705 u32 aarch32_insn_mcr_extract_crm(u32 insn);
706
707 typedef bool (pstate_check_t)(unsigned long);
708 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
709
710 #endif /* __ASSEMBLY__ */
711
712 #endif /* __ASM_INSN_H */
713