1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _nbif_6_1_SH_MASK_HEADER 22 #define _nbif_6_1_SH_MASK_HEADER 23 24 25 // addressBlock: bif_cfg_dev0_epf0_bifcfgdecp 26 //VENDOR_ID 27 #define VENDOR_ID__VENDOR_ID__SHIFT 0x0 28 //DEVICE_ID 29 #define DEVICE_ID__DEVICE_ID__SHIFT 0x0 30 //COMMAND 31 #define COMMAND__IO_ACCESS_EN__SHIFT 0x0 32 #define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 33 #define COMMAND__BUS_MASTER_EN__SHIFT 0x2 34 #define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 35 #define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 36 #define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 37 #define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 38 #define COMMAND__AD_STEPPING__SHIFT 0x7 39 #define COMMAND__SERR_EN__SHIFT 0x8 40 #define COMMAND__FAST_B2B_EN__SHIFT 0x9 41 #define COMMAND__INT_DIS__SHIFT 0xa 42 //STATUS 43 #define STATUS__INT_STATUS__SHIFT 0x3 44 #define STATUS__CAP_LIST__SHIFT 0x4 45 #define STATUS__PCI_66_EN__SHIFT 0x5 46 #define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 47 #define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 48 #define STATUS__DEVSEL_TIMING__SHIFT 0x9 49 #define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 50 #define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 51 #define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 52 #define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe 53 #define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 54 //REVISION_ID 55 #define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 56 #define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 57 //PROG_INTERFACE 58 #define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 59 //SUB_CLASS 60 #define SUB_CLASS__SUB_CLASS__SHIFT 0x0 61 //BASE_CLASS 62 #define BASE_CLASS__BASE_CLASS__SHIFT 0x0 63 //CACHE_LINE 64 #define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 65 //LATENCY 66 #define LATENCY__LATENCY_TIMER__SHIFT 0x0 67 //HEADER 68 #define HEADER__HEADER_TYPE__SHIFT 0x0 69 #define HEADER__DEVICE_TYPE__SHIFT 0x7 70 //BIST 71 #define BIST__BIST_COMP__SHIFT 0x0 72 #define BIST__BIST_STRT__SHIFT 0x6 73 #define BIST__BIST_CAP__SHIFT 0x7 74 //BASE_ADDR_1 75 #define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 76 //BASE_ADDR_2 77 #define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 78 //BASE_ADDR_3 79 #define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 80 //BASE_ADDR_4 81 #define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 82 //BASE_ADDR_5 83 #define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 84 //BASE_ADDR_6 85 #define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 86 //ADAPTER_ID 87 #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 88 #define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 89 //ROM_BASE_ADDR 90 #define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 91 //CAP_PTR 92 #define CAP_PTR__CAP_PTR__SHIFT 0x0 93 //INTERRUPT_LINE 94 #define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 95 //INTERRUPT_PIN 96 #define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 97 //MIN_GRANT 98 #define MIN_GRANT__MIN_GNT__SHIFT 0x0 99 //MAX_LATENCY 100 #define MAX_LATENCY__MAX_LAT__SHIFT 0x0 101 //VENDOR_CAP_LIST 102 #define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 103 #define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 104 #define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 105 //ADAPTER_ID_W 106 #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 107 #define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 108 //PMI_CAP_LIST 109 #define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 110 #define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 111 //PMI_CAP 112 #define PMI_CAP__VERSION__SHIFT 0x0 113 #define PMI_CAP__PME_CLOCK__SHIFT 0x3 114 #define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 115 #define PMI_CAP__AUX_CURRENT__SHIFT 0x6 116 #define PMI_CAP__D1_SUPPORT__SHIFT 0x9 117 #define PMI_CAP__D2_SUPPORT__SHIFT 0xa 118 #define PMI_CAP__PME_SUPPORT__SHIFT 0xb 119 //PMI_STATUS_CNTL 120 #define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 121 #define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 122 #define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 123 #define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 124 #define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd 125 #define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf 126 #define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 127 #define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 128 #define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 129 //PCIE_CAP_LIST 130 #define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 131 #define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 132 //PCIE_CAP 133 #define PCIE_CAP__VERSION__SHIFT 0x0 134 #define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 135 #define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 136 #define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 137 //DEVICE_CAP 138 #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 139 #define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 140 #define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 141 #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 142 #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 143 #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf 144 #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 145 #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a 146 #define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c 147 //DEVICE_CNTL 148 #define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 149 #define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 150 #define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 151 #define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 152 #define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 153 #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 154 #define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 155 #define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 156 #define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 157 #define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb 158 #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc 159 #define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf 160 //DEVICE_STATUS 161 #define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 162 #define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 163 #define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 164 #define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 165 #define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 166 #define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 167 //LINK_CAP 168 #define LINK_CAP__LINK_SPEED__SHIFT 0x0 169 #define LINK_CAP__LINK_WIDTH__SHIFT 0x4 170 #define LINK_CAP__PM_SUPPORT__SHIFT 0xa 171 #define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc 172 #define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf 173 #define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 174 #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 175 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 176 #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 177 #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 178 #define LINK_CAP__PORT_NUMBER__SHIFT 0x18 179 //LINK_CNTL 180 #define LINK_CNTL__PM_CONTROL__SHIFT 0x0 181 #define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 182 #define LINK_CNTL__LINK_DIS__SHIFT 0x4 183 #define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 184 #define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 185 #define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 186 #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 187 #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 188 #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 189 #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb 190 //LINK_STATUS 191 #define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 192 #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 193 #define LINK_STATUS__LINK_TRAINING__SHIFT 0xb 194 #define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc 195 #define LINK_STATUS__DL_ACTIVE__SHIFT 0xd 196 #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe 197 #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf 198 //DEVICE_CAP2 199 #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 200 #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 201 #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 202 #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 203 #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 204 #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 205 #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 206 #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 207 #define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb 208 #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc 209 #define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 210 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 211 #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 212 #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 213 //DEVICE_CNTL2 214 #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 215 #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 216 #define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 217 #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 218 #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 219 #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 220 #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 221 #define DEVICE_CNTL2__LTR_EN__SHIFT 0xa 222 #define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd 223 #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf 224 //DEVICE_STATUS2 225 #define DEVICE_STATUS2__RESERVED__SHIFT 0x0 226 //LINK_CAP2 227 #define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 228 #define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 229 #define LINK_CAP2__RESERVED__SHIFT 0x9 230 //LINK_CNTL2 231 #define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 232 #define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 233 #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 234 #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 235 #define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 236 #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 237 #define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb 238 #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc 239 //LINK_STATUS2 240 #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 241 #define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 242 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 243 #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 244 #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 245 #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 246 //SLOT_CAP2 247 #define SLOT_CAP2__RESERVED__SHIFT 0x0 248 //SLOT_CNTL2 249 #define SLOT_CNTL2__RESERVED__SHIFT 0x0 250 //SLOT_STATUS2 251 #define SLOT_STATUS2__RESERVED__SHIFT 0x0 252 //MSI_CAP_LIST 253 #define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 254 #define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 255 //MSI_MSG_CNTL 256 #define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 257 #define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 258 #define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 259 #define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 260 #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 261 //MSI_MSG_ADDR_LO 262 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 263 //MSI_MSG_ADDR_HI 264 #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 265 //MSI_MSG_DATA 266 #define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 267 //MSI_MSG_DATA_64 268 #define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 269 //MSI_MASK 270 #define MSI_MASK__MSI_MASK__SHIFT 0x0 271 //MSI_PENDING 272 #define MSI_PENDING__MSI_PENDING__SHIFT 0x0 273 //MSI_MASK_64 274 #define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 275 //MSI_PENDING_64 276 #define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 277 //MSIX_CAP_LIST 278 #define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 279 #define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 280 //MSIX_MSG_CNTL 281 #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 282 #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe 283 #define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf 284 //MSIX_TABLE 285 #define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 286 #define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 287 //MSIX_PBA 288 #define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 289 #define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 290 //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 291 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 292 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 293 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 294 //PCIE_VENDOR_SPECIFIC_HDR 295 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 296 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 297 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 298 //PCIE_VENDOR_SPECIFIC1 299 #define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 300 //PCIE_VENDOR_SPECIFIC2 301 #define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 302 //PCIE_VC_ENH_CAP_LIST 303 #define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 304 #define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 305 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 306 //PCIE_PORT_VC_CAP_REG1 307 #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 308 #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 309 #define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 310 #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa 311 //PCIE_PORT_VC_CAP_REG2 312 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 313 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 314 //PCIE_PORT_VC_CNTL 315 #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 316 #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 317 //PCIE_PORT_VC_STATUS 318 #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 319 //PCIE_VC0_RESOURCE_CAP 320 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 321 #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 322 #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 323 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 324 //PCIE_VC0_RESOURCE_CNTL 325 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 326 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 327 #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 328 #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 329 #define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 330 #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 331 //PCIE_VC0_RESOURCE_STATUS 332 #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 333 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 334 //PCIE_VC1_RESOURCE_CAP 335 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 336 #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 337 #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 338 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 339 //PCIE_VC1_RESOURCE_CNTL 340 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 341 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 342 #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 343 #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 344 #define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 345 #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 346 //PCIE_VC1_RESOURCE_STATUS 347 #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 348 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 349 //PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 350 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 351 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 352 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 353 //PCIE_DEV_SERIAL_NUM_DW1 354 #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 355 //PCIE_DEV_SERIAL_NUM_DW2 356 #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 357 //PCIE_ADV_ERR_RPT_ENH_CAP_LIST 358 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 359 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 360 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 361 //PCIE_UNCORR_ERR_STATUS 362 #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 363 #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 364 #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc 365 #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd 366 #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe 367 #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf 368 #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 369 #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 370 #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 371 #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 372 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 373 #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 374 #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 375 #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 376 #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 377 #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 378 //PCIE_UNCORR_ERR_MASK 379 #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 380 #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 381 #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc 382 #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd 383 #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe 384 #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf 385 #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 386 #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 387 #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 388 #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 389 #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 390 #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 391 #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 392 #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 393 #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 394 #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 395 //PCIE_UNCORR_ERR_SEVERITY 396 #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 397 #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 398 #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc 399 #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd 400 #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe 401 #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf 402 #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 403 #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 404 #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 405 #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 406 #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 407 #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 408 #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 409 #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 410 #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 411 #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 412 //PCIE_CORR_ERR_STATUS 413 #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 414 #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 415 #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 416 #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 417 #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc 418 #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd 419 #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe 420 #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf 421 //PCIE_CORR_ERR_MASK 422 #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 423 #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 424 #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 425 #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 426 #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc 427 #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd 428 #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe 429 #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf 430 //PCIE_ADV_ERR_CAP_CNTL 431 #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 432 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 433 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 434 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 435 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 436 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 437 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa 438 #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb 439 //PCIE_HDR_LOG0 440 #define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 441 //PCIE_HDR_LOG1 442 #define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 443 //PCIE_HDR_LOG2 444 #define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 445 //PCIE_HDR_LOG3 446 #define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 447 //PCIE_ROOT_ERR_CMD 448 #define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 449 #define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 450 #define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 451 //PCIE_ROOT_ERR_STATUS 452 #define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 453 #define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 454 #define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 455 #define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 456 #define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 457 #define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 458 #define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 459 #define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b 460 //PCIE_ERR_SRC_ID 461 #define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 462 #define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 463 //PCIE_TLP_PREFIX_LOG0 464 #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 465 //PCIE_TLP_PREFIX_LOG1 466 #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 467 //PCIE_TLP_PREFIX_LOG2 468 #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 469 //PCIE_TLP_PREFIX_LOG3 470 #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 471 //PCIE_BAR_ENH_CAP_LIST 472 #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 473 #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 474 #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 475 //PCIE_BAR1_CAP 476 #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 477 //PCIE_BAR1_CNTL 478 #define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 479 #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 480 #define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 481 //PCIE_BAR2_CAP 482 #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 483 //PCIE_BAR2_CNTL 484 #define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 485 #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 486 #define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 487 //PCIE_BAR3_CAP 488 #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 489 //PCIE_BAR3_CNTL 490 #define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 491 #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 492 #define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 493 //PCIE_BAR4_CAP 494 #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 495 //PCIE_BAR4_CNTL 496 #define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 497 #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 498 #define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 499 //PCIE_BAR5_CAP 500 #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 501 //PCIE_BAR5_CNTL 502 #define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 503 #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 504 #define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 505 //PCIE_BAR6_CAP 506 #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 507 //PCIE_BAR6_CNTL 508 #define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 509 #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 510 #define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 511 //PCIE_PWR_BUDGET_ENH_CAP_LIST 512 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 513 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 514 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 515 //PCIE_PWR_BUDGET_DATA_SELECT 516 #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 517 //PCIE_PWR_BUDGET_DATA 518 #define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 519 #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 520 #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa 521 #define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd 522 #define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf 523 #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 524 //PCIE_PWR_BUDGET_CAP 525 #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 526 //PCIE_DPA_ENH_CAP_LIST 527 #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 528 #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 529 #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 530 //PCIE_DPA_CAP 531 #define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 532 #define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 533 #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 534 #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 535 #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 536 //PCIE_DPA_LATENCY_INDICATOR 537 #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 538 //PCIE_DPA_STATUS 539 #define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 540 #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 541 //PCIE_DPA_CNTL 542 #define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 543 //PCIE_DPA_SUBSTATE_PWR_ALLOC_0 544 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 545 //PCIE_DPA_SUBSTATE_PWR_ALLOC_1 546 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 547 //PCIE_DPA_SUBSTATE_PWR_ALLOC_2 548 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 549 //PCIE_DPA_SUBSTATE_PWR_ALLOC_3 550 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 551 //PCIE_DPA_SUBSTATE_PWR_ALLOC_4 552 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 553 //PCIE_DPA_SUBSTATE_PWR_ALLOC_5 554 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 555 //PCIE_DPA_SUBSTATE_PWR_ALLOC_6 556 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 557 //PCIE_DPA_SUBSTATE_PWR_ALLOC_7 558 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 559 //PCIE_SECONDARY_ENH_CAP_LIST 560 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 561 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 562 #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 563 //PCIE_LINK_CNTL3 564 #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 565 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 566 #define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 567 //PCIE_LANE_ERROR_STATUS 568 #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 569 #define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 570 //PCIE_LANE_0_EQUALIZATION_CNTL 571 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 572 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 573 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 574 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 575 #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 576 //PCIE_LANE_1_EQUALIZATION_CNTL 577 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 578 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 579 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 580 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 581 #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 582 //PCIE_LANE_2_EQUALIZATION_CNTL 583 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 584 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 585 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 586 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 587 #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 588 //PCIE_LANE_3_EQUALIZATION_CNTL 589 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 590 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 591 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 592 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 593 #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 594 //PCIE_LANE_4_EQUALIZATION_CNTL 595 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 596 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 597 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 598 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 599 #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 600 //PCIE_LANE_5_EQUALIZATION_CNTL 601 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 602 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 603 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 604 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 605 #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 606 //PCIE_LANE_6_EQUALIZATION_CNTL 607 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 608 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 609 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 610 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 611 #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 612 //PCIE_LANE_7_EQUALIZATION_CNTL 613 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 614 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 615 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 616 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 617 #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 618 //PCIE_LANE_8_EQUALIZATION_CNTL 619 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 620 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 621 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 622 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 623 #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 624 //PCIE_LANE_9_EQUALIZATION_CNTL 625 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 626 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 627 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 628 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 629 #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 630 //PCIE_LANE_10_EQUALIZATION_CNTL 631 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 632 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 633 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 634 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 635 #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 636 //PCIE_LANE_11_EQUALIZATION_CNTL 637 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 638 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 639 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 640 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 641 #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 642 //PCIE_LANE_12_EQUALIZATION_CNTL 643 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 644 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 645 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 646 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 647 #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 648 //PCIE_LANE_13_EQUALIZATION_CNTL 649 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 650 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 651 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 652 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 653 #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 654 //PCIE_LANE_14_EQUALIZATION_CNTL 655 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 656 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 657 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 658 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 659 #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 660 //PCIE_LANE_15_EQUALIZATION_CNTL 661 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 662 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 663 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 664 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 665 #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 666 //PCIE_ACS_ENH_CAP_LIST 667 #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 668 #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 669 #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 670 //PCIE_ACS_CAP 671 #define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 672 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 673 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 674 #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 675 #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 676 #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 677 #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 678 #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 679 //PCIE_ACS_CNTL 680 #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 681 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 682 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 683 #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 684 #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 685 #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 686 #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 687 //PCIE_ATS_ENH_CAP_LIST 688 #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 689 #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 690 #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 691 //PCIE_ATS_CAP 692 #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 693 #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 694 #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 695 //PCIE_ATS_CNTL 696 #define PCIE_ATS_CNTL__STU__SHIFT 0x0 697 #define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf 698 //PCIE_PAGE_REQ_ENH_CAP_LIST 699 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 700 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 701 #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 702 //PCIE_PAGE_REQ_CNTL 703 #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 704 #define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 705 //PCIE_PAGE_REQ_STATUS 706 #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 707 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 708 #define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 709 #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf 710 //PCIE_OUTSTAND_PAGE_REQ_CAPACITY 711 #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 712 //PCIE_OUTSTAND_PAGE_REQ_ALLOC 713 #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 714 //PCIE_PASID_ENH_CAP_LIST 715 #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 716 #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 717 #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 718 //PCIE_PASID_CAP 719 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 720 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 721 #define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 722 //PCIE_PASID_CNTL 723 #define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 724 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 725 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 726 //PCIE_TPH_REQR_ENH_CAP_LIST 727 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 728 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 729 #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 730 //PCIE_TPH_REQR_CAP 731 #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 732 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 733 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 734 #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 735 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 736 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 737 //PCIE_TPH_REQR_CNTL 738 #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 739 #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 740 //PCIE_MC_ENH_CAP_LIST 741 #define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 742 #define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 743 #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 744 //PCIE_MC_CAP 745 #define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 746 #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 747 #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf 748 //PCIE_MC_CNTL 749 #define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 750 #define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf 751 //PCIE_MC_ADDR0 752 #define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 753 #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc 754 //PCIE_MC_ADDR1 755 #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 756 //PCIE_MC_RCV0 757 #define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 758 //PCIE_MC_RCV1 759 #define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 760 //PCIE_MC_BLOCK_ALL0 761 #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 762 //PCIE_MC_BLOCK_ALL1 763 #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 764 //PCIE_MC_BLOCK_UNTRANSLATED_0 765 #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 766 //PCIE_MC_BLOCK_UNTRANSLATED_1 767 #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 768 //PCIE_LTR_ENH_CAP_LIST 769 #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 770 #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 771 #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 772 //PCIE_LTR_CAP 773 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 774 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa 775 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 776 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a 777 //PCIE_ARI_ENH_CAP_LIST 778 #define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 779 #define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 780 #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 781 //PCIE_ARI_CAP 782 #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 783 #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 784 #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 785 //PCIE_ARI_CNTL 786 #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 787 #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 788 #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 789 //PCIE_SRIOV_ENH_CAP_LIST 790 #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 791 #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 792 #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 793 //PCIE_SRIOV_CAP 794 #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 795 #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 796 #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 797 //PCIE_SRIOV_CONTROL 798 #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 799 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 800 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 801 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 802 #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 803 //PCIE_SRIOV_STATUS 804 #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 805 //PCIE_SRIOV_INITIAL_VFS 806 #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 807 //PCIE_SRIOV_TOTAL_VFS 808 #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 809 //PCIE_SRIOV_NUM_VFS 810 #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 811 //PCIE_SRIOV_FUNC_DEP_LINK 812 #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 813 //PCIE_SRIOV_FIRST_VF_OFFSET 814 #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 815 //PCIE_SRIOV_VF_STRIDE 816 #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 817 //PCIE_SRIOV_VF_DEVICE_ID 818 #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 819 //PCIE_SRIOV_SUPPORTED_PAGE_SIZE 820 #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 821 //PCIE_SRIOV_SYSTEM_PAGE_SIZE 822 #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 823 //PCIE_SRIOV_VF_BASE_ADDR_0 824 #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 825 //PCIE_SRIOV_VF_BASE_ADDR_1 826 #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 827 //PCIE_SRIOV_VF_BASE_ADDR_2 828 #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 829 //PCIE_SRIOV_VF_BASE_ADDR_3 830 #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 831 //PCIE_SRIOV_VF_BASE_ADDR_4 832 #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 833 //PCIE_SRIOV_VF_BASE_ADDR_5 834 #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 835 //PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 836 #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 837 #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 838 //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 839 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 840 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 841 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 842 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 843 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 844 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 845 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 846 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 847 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 848 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 849 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 850 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 851 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 852 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 853 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 854 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 855 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 856 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa 857 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb 858 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 859 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 860 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 861 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 862 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 863 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 864 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 865 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 866 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 867 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 868 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 869 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 870 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 871 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa 872 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb 873 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 874 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 875 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 876 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 877 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 878 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 879 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 880 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 881 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 882 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 883 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 884 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf 885 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 886 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 887 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 888 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 889 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 890 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 891 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 892 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 893 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 894 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 895 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 896 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 897 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 898 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa 899 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb 900 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc 901 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd 902 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe 903 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf 904 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 905 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 906 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 907 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 908 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 909 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 910 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 911 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 912 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 913 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 914 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a 915 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b 916 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c 917 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d 918 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e 919 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f 920 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 921 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 922 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 923 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 924 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 925 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 926 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa 927 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 928 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 929 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 930 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 931 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 932 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 933 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 934 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 935 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 936 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 937 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 938 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 939 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 940 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 941 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 942 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 943 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 944 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 945 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 946 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 947 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 948 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 949 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 950 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 951 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 952 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 953 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 954 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 955 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 956 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 957 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 958 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 959 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 960 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 961 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 962 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 963 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 964 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 965 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 966 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 967 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 968 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 969 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 970 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 971 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 972 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 973 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 974 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 975 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 976 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 977 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 978 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 979 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 980 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 981 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 982 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 983 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 984 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 985 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 986 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 987 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 988 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 989 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 990 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 991 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 992 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 993 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 994 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 995 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 996 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 997 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 998 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 999 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 1000 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 1001 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 1002 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 1003 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 1004 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 1005 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 1006 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 1007 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 1008 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 1009 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 1010 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 1011 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 1012 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 1013 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 1014 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 1015 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 1016 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 1017 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 1018 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 1019 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 1020 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 1021 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 1022 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 1023 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 1024 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 1025 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 1026 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 1027 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 1028 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 1029 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 1030 1031 1032 // addressBlock: bif_cfg_dev0_swds_bifcfgdecp 1033 //SUB_BUS_NUMBER_LATENCY 1034 #define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 1035 #define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 1036 #define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 1037 #define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 1038 //IO_BASE_LIMIT 1039 #define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 1040 #define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 1041 #define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 1042 #define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc 1043 //SECONDARY_STATUS 1044 #define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 1045 #define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 1046 #define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 1047 #define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 1048 #define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 1049 #define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 1050 #define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 1051 #define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 1052 #define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe 1053 #define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 1054 //MEM_BASE_LIMIT 1055 #define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 1056 #define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 1057 #define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 1058 #define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 1059 //PREF_BASE_LIMIT 1060 #define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 1061 #define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 1062 #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 1063 #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 1064 //PREF_BASE_UPPER 1065 #define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 1066 //PREF_LIMIT_UPPER 1067 #define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 1068 //IO_BASE_LIMIT_HI 1069 #define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 1070 #define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 1071 //IRQ_BRIDGE_CNTL 1072 #define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 1073 #define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 1074 #define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 1075 #define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 1076 #define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 1077 #define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 1078 #define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 1079 #define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 1080 //SLOT_CAP 1081 #define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 1082 #define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 1083 #define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 1084 #define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 1085 #define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 1086 #define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 1087 #define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 1088 #define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 1089 #define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf 1090 #define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 1091 #define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 1092 #define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 1093 //SLOT_CNTL 1094 #define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 1095 #define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 1096 #define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 1097 #define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 1098 #define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 1099 #define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 1100 #define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 1101 #define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 1102 #define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa 1103 #define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb 1104 #define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc 1105 //SLOT_STATUS 1106 #define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 1107 #define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 1108 #define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 1109 #define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 1110 #define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 1111 #define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 1112 #define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 1113 #define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 1114 #define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 1115 //SSID_CAP_LIST 1116 #define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 1117 #define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 1118 //SSID_CAP 1119 #define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 1120 #define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 1121 1122 1123 // addressBlock: rcc_shadow_reg_shadowdec 1124 //SHADOW_COMMAND 1125 #define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 1126 #define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 1127 //SHADOW_BASE_ADDR_1 1128 #define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 1129 //SHADOW_BASE_ADDR_2 1130 #define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 1131 //SHADOW_SUB_BUS_NUMBER_LATENCY 1132 #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 1133 #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 1134 //SHADOW_IO_BASE_LIMIT 1135 #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 1136 #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc 1137 //SHADOW_MEM_BASE_LIMIT 1138 #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 1139 #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 1140 #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 1141 #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 1142 //SHADOW_PREF_BASE_LIMIT 1143 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 1144 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 1145 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 1146 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 1147 //SHADOW_PREF_BASE_UPPER 1148 #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 1149 //SHADOW_PREF_LIMIT_UPPER 1150 #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 1151 //SHADOW_IO_BASE_LIMIT_HI 1152 #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 1153 #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 1154 //SHADOW_IRQ_BRIDGE_CNTL 1155 #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 1156 #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 1157 #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 1158 #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 1159 //SUC_INDEX 1160 #define SUC_INDEX__SUC_INDEX__SHIFT 0x0 1161 //SUC_DATA 1162 #define SUC_DATA__SUC_DATA__SHIFT 0x0 1163 1164 1165 // addressBlock: bif_bx_pf_SUMDEC 1166 //SUM_INDEX 1167 #define SUM_INDEX__SUM_INDEX__SHIFT 0x0 1168 //SUM_DATA 1169 #define SUM_DATA__SUM_DATA__SHIFT 0x0 1170 1171 1172 // addressBlock: gdc_GDCDEC 1173 //A2S_CNTL_CL0 1174 #define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 1175 #define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 1176 #define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 1177 #define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1178 #define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1179 #define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa 1180 #define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc 1181 #define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe 1182 #define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 1183 #define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 1184 #define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 1185 //A2S_CNTL_CL1 1186 #define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 1187 #define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 1188 #define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 1189 #define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1190 #define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1191 #define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa 1192 #define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc 1193 #define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe 1194 #define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 1195 #define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 1196 #define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 1197 //A2S_CNTL_CL2 1198 #define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0 1199 #define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2 1200 #define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4 1201 #define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1202 #define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1203 #define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa 1204 #define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc 1205 #define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe 1206 #define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10 1207 #define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12 1208 #define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14 1209 //A2S_CNTL_CL3 1210 #define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0 1211 #define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2 1212 #define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4 1213 #define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1214 #define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1215 #define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa 1216 #define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc 1217 #define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe 1218 #define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10 1219 #define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12 1220 #define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14 1221 //A2S_CNTL_CL4 1222 #define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0 1223 #define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2 1224 #define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4 1225 #define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1226 #define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1227 #define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa 1228 #define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc 1229 #define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe 1230 #define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10 1231 #define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12 1232 #define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14 1233 //A2S_CNTL_SW0 1234 #define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0 1235 #define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3 1236 #define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 1237 #define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7 1238 #define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8 1239 #define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 1240 #define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1241 #define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1242 #define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1243 #define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 1244 #define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 1245 //A2S_CNTL_SW1 1246 #define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0 1247 #define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3 1248 #define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 1249 #define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7 1250 #define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8 1251 #define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 1252 #define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1253 #define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1254 #define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1255 #define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 1256 #define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 1257 //A2S_CNTL_SW2 1258 #define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0 1259 #define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3 1260 #define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 1261 #define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7 1262 #define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8 1263 #define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 1264 #define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1265 #define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1266 #define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1267 #define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 1268 #define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 1269 //NGDC_MGCG_CTRL 1270 #define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 1271 #define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 1272 #define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 1273 //A2S_MISC_CNTL 1274 #define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 1275 #define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 1276 //NGDC_SDP_PORT_CTRL 1277 #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 1278 //NGDC_RESERVED_0 1279 #define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 1280 //NGDC_RESERVED_1 1281 #define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 1282 //BIF_SDMA0_DOORBELL_RANGE 1283 #define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1284 #define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 1285 //BIF_SDMA1_DOORBELL_RANGE 1286 #define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1287 #define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 1288 //BIF_IH_DOORBELL_RANGE 1289 #define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1290 #define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 1291 //BIF_MMSCH0_DOORBELL_RANGE 1292 #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1293 #define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 1294 //BIF_DOORBELL_FENCE_CNTL 1295 #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 1296 //S2A_MISC_CNTL 1297 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 1298 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 1299 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 1300 //A2S_CNTL2_SEC_CL0 1301 #define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0 1302 //A2S_CNTL2_SEC_CL1 1303 #define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0 1304 //A2S_CNTL2_SEC_CL2 1305 #define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0 1306 //A2S_CNTL2_SEC_CL3 1307 #define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0 1308 //A2S_CNTL2_SEC_CL4 1309 #define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0 1310 1311 1312 // addressBlock: nbif_sion_SIONDEC 1313 //SION_CL0_RdRsp_BurstTarget_REG0 1314 #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1315 //SION_CL0_RdRsp_BurstTarget_REG1 1316 #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1317 //SION_CL0_RdRsp_TimeSlot_REG0 1318 #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1319 //SION_CL0_RdRsp_TimeSlot_REG1 1320 #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1321 //SION_CL0_WrRsp_BurstTarget_REG0 1322 #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1323 //SION_CL0_WrRsp_BurstTarget_REG1 1324 #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1325 //SION_CL0_WrRsp_TimeSlot_REG0 1326 #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1327 //SION_CL0_WrRsp_TimeSlot_REG1 1328 #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1329 //SION_CL0_Req_BurstTarget_REG0 1330 #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1331 //SION_CL0_Req_BurstTarget_REG1 1332 #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1333 //SION_CL0_Req_TimeSlot_REG0 1334 #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1335 //SION_CL0_Req_TimeSlot_REG1 1336 #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1337 //SION_CL0_ReqPoolCredit_Alloc_REG0 1338 #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1339 //SION_CL0_ReqPoolCredit_Alloc_REG1 1340 #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1341 //SION_CL0_DataPoolCredit_Alloc_REG0 1342 #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1343 //SION_CL0_DataPoolCredit_Alloc_REG1 1344 #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1345 //SION_CL0_RdRspPoolCredit_Alloc_REG0 1346 #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1347 //SION_CL0_RdRspPoolCredit_Alloc_REG1 1348 #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1349 //SION_CL0_WrRspPoolCredit_Alloc_REG0 1350 #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1351 //SION_CL0_WrRspPoolCredit_Alloc_REG1 1352 #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1353 //SION_CL1_RdRsp_BurstTarget_REG0 1354 #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1355 //SION_CL1_RdRsp_BurstTarget_REG1 1356 #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1357 //SION_CL1_RdRsp_TimeSlot_REG0 1358 #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1359 //SION_CL1_RdRsp_TimeSlot_REG1 1360 #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1361 //SION_CL1_WrRsp_BurstTarget_REG0 1362 #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1363 //SION_CL1_WrRsp_BurstTarget_REG1 1364 #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1365 //SION_CL1_WrRsp_TimeSlot_REG0 1366 #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1367 //SION_CL1_WrRsp_TimeSlot_REG1 1368 #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1369 //SION_CL1_Req_BurstTarget_REG0 1370 #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1371 //SION_CL1_Req_BurstTarget_REG1 1372 #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1373 //SION_CL1_Req_TimeSlot_REG0 1374 #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1375 //SION_CL1_Req_TimeSlot_REG1 1376 #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1377 //SION_CL1_ReqPoolCredit_Alloc_REG0 1378 #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1379 //SION_CL1_ReqPoolCredit_Alloc_REG1 1380 #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1381 //SION_CL1_DataPoolCredit_Alloc_REG0 1382 #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1383 //SION_CL1_DataPoolCredit_Alloc_REG1 1384 #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1385 //SION_CL1_RdRspPoolCredit_Alloc_REG0 1386 #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1387 //SION_CL1_RdRspPoolCredit_Alloc_REG1 1388 #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1389 //SION_CL1_WrRspPoolCredit_Alloc_REG0 1390 #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1391 //SION_CL1_WrRspPoolCredit_Alloc_REG1 1392 #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1393 //SION_CL2_RdRsp_BurstTarget_REG0 1394 #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1395 //SION_CL2_RdRsp_BurstTarget_REG1 1396 #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1397 //SION_CL2_RdRsp_TimeSlot_REG0 1398 #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1399 //SION_CL2_RdRsp_TimeSlot_REG1 1400 #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1401 //SION_CL2_WrRsp_BurstTarget_REG0 1402 #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1403 //SION_CL2_WrRsp_BurstTarget_REG1 1404 #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1405 //SION_CL2_WrRsp_TimeSlot_REG0 1406 #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1407 //SION_CL2_WrRsp_TimeSlot_REG1 1408 #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1409 //SION_CL2_Req_BurstTarget_REG0 1410 #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1411 //SION_CL2_Req_BurstTarget_REG1 1412 #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1413 //SION_CL2_Req_TimeSlot_REG0 1414 #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1415 //SION_CL2_Req_TimeSlot_REG1 1416 #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1417 //SION_CL2_ReqPoolCredit_Alloc_REG0 1418 #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1419 //SION_CL2_ReqPoolCredit_Alloc_REG1 1420 #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1421 //SION_CL2_DataPoolCredit_Alloc_REG0 1422 #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1423 //SION_CL2_DataPoolCredit_Alloc_REG1 1424 #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1425 //SION_CL2_RdRspPoolCredit_Alloc_REG0 1426 #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1427 //SION_CL2_RdRspPoolCredit_Alloc_REG1 1428 #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1429 //SION_CL2_WrRspPoolCredit_Alloc_REG0 1430 #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1431 //SION_CL2_WrRspPoolCredit_Alloc_REG1 1432 #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1433 //SION_CL3_RdRsp_BurstTarget_REG0 1434 #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1435 //SION_CL3_RdRsp_BurstTarget_REG1 1436 #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1437 //SION_CL3_RdRsp_TimeSlot_REG0 1438 #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1439 //SION_CL3_RdRsp_TimeSlot_REG1 1440 #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1441 //SION_CL3_WrRsp_BurstTarget_REG0 1442 #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1443 //SION_CL3_WrRsp_BurstTarget_REG1 1444 #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1445 //SION_CL3_WrRsp_TimeSlot_REG0 1446 #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1447 //SION_CL3_WrRsp_TimeSlot_REG1 1448 #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1449 //SION_CL3_Req_BurstTarget_REG0 1450 #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1451 //SION_CL3_Req_BurstTarget_REG1 1452 #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1453 //SION_CL3_Req_TimeSlot_REG0 1454 #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1455 //SION_CL3_Req_TimeSlot_REG1 1456 #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1457 //SION_CL3_ReqPoolCredit_Alloc_REG0 1458 #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1459 //SION_CL3_ReqPoolCredit_Alloc_REG1 1460 #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1461 //SION_CL3_DataPoolCredit_Alloc_REG0 1462 #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1463 //SION_CL3_DataPoolCredit_Alloc_REG1 1464 #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1465 //SION_CL3_RdRspPoolCredit_Alloc_REG0 1466 #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1467 //SION_CL3_RdRspPoolCredit_Alloc_REG1 1468 #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1469 //SION_CL3_WrRspPoolCredit_Alloc_REG0 1470 #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1471 //SION_CL3_WrRspPoolCredit_Alloc_REG1 1472 #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1473 //SION_CL4_RdRsp_BurstTarget_REG0 1474 #define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1475 //SION_CL4_RdRsp_BurstTarget_REG1 1476 #define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1477 //SION_CL4_RdRsp_TimeSlot_REG0 1478 #define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1479 //SION_CL4_RdRsp_TimeSlot_REG1 1480 #define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1481 //SION_CL4_WrRsp_BurstTarget_REG0 1482 #define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1483 //SION_CL4_WrRsp_BurstTarget_REG1 1484 #define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1485 //SION_CL4_WrRsp_TimeSlot_REG0 1486 #define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1487 //SION_CL4_WrRsp_TimeSlot_REG1 1488 #define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1489 //SION_CL4_Req_BurstTarget_REG0 1490 #define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1491 //SION_CL4_Req_BurstTarget_REG1 1492 #define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1493 //SION_CL4_Req_TimeSlot_REG0 1494 #define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1495 //SION_CL4_Req_TimeSlot_REG1 1496 #define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1497 //SION_CL4_ReqPoolCredit_Alloc_REG0 1498 #define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1499 //SION_CL4_ReqPoolCredit_Alloc_REG1 1500 #define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1501 //SION_CL4_DataPoolCredit_Alloc_REG0 1502 #define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1503 //SION_CL4_DataPoolCredit_Alloc_REG1 1504 #define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1505 //SION_CL4_RdRspPoolCredit_Alloc_REG0 1506 #define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1507 //SION_CL4_RdRspPoolCredit_Alloc_REG1 1508 #define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1509 //SION_CL4_WrRspPoolCredit_Alloc_REG0 1510 #define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1511 //SION_CL4_WrRspPoolCredit_Alloc_REG1 1512 #define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1513 //SION_CL5_RdRsp_BurstTarget_REG0 1514 #define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1515 //SION_CL5_RdRsp_BurstTarget_REG1 1516 #define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1517 //SION_CL5_RdRsp_TimeSlot_REG0 1518 #define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1519 //SION_CL5_RdRsp_TimeSlot_REG1 1520 #define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1521 //SION_CL5_WrRsp_BurstTarget_REG0 1522 #define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1523 //SION_CL5_WrRsp_BurstTarget_REG1 1524 #define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1525 //SION_CL5_WrRsp_TimeSlot_REG0 1526 #define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1527 //SION_CL5_WrRsp_TimeSlot_REG1 1528 #define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1529 //SION_CL5_Req_BurstTarget_REG0 1530 #define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1531 //SION_CL5_Req_BurstTarget_REG1 1532 #define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1533 //SION_CL5_Req_TimeSlot_REG0 1534 #define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1535 //SION_CL5_Req_TimeSlot_REG1 1536 #define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1537 //SION_CL5_ReqPoolCredit_Alloc_REG0 1538 #define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1539 //SION_CL5_ReqPoolCredit_Alloc_REG1 1540 #define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1541 //SION_CL5_DataPoolCredit_Alloc_REG0 1542 #define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1543 //SION_CL5_DataPoolCredit_Alloc_REG1 1544 #define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1545 //SION_CL5_RdRspPoolCredit_Alloc_REG0 1546 #define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1547 //SION_CL5_RdRspPoolCredit_Alloc_REG1 1548 #define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1549 //SION_CL5_WrRspPoolCredit_Alloc_REG0 1550 #define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1551 //SION_CL5_WrRspPoolCredit_Alloc_REG1 1552 #define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1553 //SION_CNTL_REG0 1554 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 1555 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 1556 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 1557 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 1558 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 1559 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 1560 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 1561 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 1562 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 1563 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 1564 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa 1565 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb 1566 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc 1567 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd 1568 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe 1569 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf 1570 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 1571 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 1572 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 1573 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 1574 //SION_CNTL_REG1 1575 #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 1576 #define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 1577 1578 1579 // addressBlock: syshub_mmreg_direct_syshubdirect 1580 //SYSHUB_DS_CTRL_SOCCLK 1581 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 1582 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 1583 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 1584 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 1585 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 1586 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 1587 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 1588 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 1589 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 1590 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 1591 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 1592 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 1593 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 1594 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 1595 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 1596 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 1597 #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 1598 #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f 1599 //SYSHUB_DS_CTRL2_SOCCLK 1600 #define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 1601 //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 1602 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 1603 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 1604 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf 1605 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 1606 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 1607 //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 1608 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 1609 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 1610 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf 1611 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 1612 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 1613 //DMA_CLK0_SW0_SYSHUB_QOS_CNTL 1614 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1615 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1616 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1617 //DMA_CLK0_SW1_SYSHUB_QOS_CNTL 1618 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1619 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1620 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1621 //DMA_CLK0_SW0_CL0_CNTL 1622 #define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1623 #define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1624 #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1625 #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1626 #define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1627 #define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1628 //DMA_CLK0_SW0_CL1_CNTL 1629 #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1630 #define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1631 #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1632 #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1633 #define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1634 #define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1635 //DMA_CLK0_SW0_CL2_CNTL 1636 #define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1637 #define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1638 #define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1639 #define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1640 #define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1641 #define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1642 //DMA_CLK0_SW0_CL3_CNTL 1643 #define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1644 #define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1645 #define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1646 #define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1647 #define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1648 #define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1649 //DMA_CLK0_SW0_CL4_CNTL 1650 #define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1651 #define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1652 #define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1653 #define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1654 #define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1655 #define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1656 //DMA_CLK0_SW0_CL5_CNTL 1657 #define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1658 #define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1659 #define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1660 #define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1661 #define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1662 #define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1663 //DMA_CLK0_SW1_CL0_CNTL 1664 #define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1665 #define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1666 #define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1667 #define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1668 #define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1669 #define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1670 //DMA_CLK0_SW2_CL0_CNTL 1671 #define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1672 #define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1673 #define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1674 #define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1675 #define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1676 #define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1677 //SYSHUB_CG_CNTL 1678 #define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 1679 #define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 1680 #define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 1681 //SYSHUB_TRANS_IDLE 1682 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 1683 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 1684 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 1685 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 1686 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 1687 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 1688 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 1689 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 1690 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 1691 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 1692 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa 1693 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb 1694 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc 1695 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd 1696 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe 1697 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf 1698 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 1699 //SYSHUB_HP_TIMER 1700 #define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 1701 //SYSHUB_SCRATCH 1702 #define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 1703 //SYSHUB_DS_CTRL_SHUBCLK 1704 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 1705 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 1706 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 1707 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 1708 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 1709 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 1710 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 1711 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 1712 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 1713 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 1714 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 1715 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 1716 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 1717 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 1718 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 1719 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 1720 #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 1721 #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f 1722 //SYSHUB_DS_CTRL2_SHUBCLK 1723 #define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 1724 //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 1725 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf 1726 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 1727 //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 1728 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf 1729 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 1730 //DMA_CLK1_SW0_SYSHUB_QOS_CNTL 1731 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1732 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1733 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1734 //DMA_CLK1_SW1_SYSHUB_QOS_CNTL 1735 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1736 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1737 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1738 //DMA_CLK1_SW0_CL0_CNTL 1739 #define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1740 #define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1741 #define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1742 #define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1743 #define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1744 #define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1745 //DMA_CLK1_SW0_CL1_CNTL 1746 #define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1747 #define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1748 #define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1749 #define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1750 #define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1751 #define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1752 //DMA_CLK1_SW0_CL2_CNTL 1753 #define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1754 #define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1755 #define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1756 #define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1757 #define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1758 #define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1759 //DMA_CLK1_SW0_CL3_CNTL 1760 #define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1761 #define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1762 #define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1763 #define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1764 #define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1765 #define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1766 //DMA_CLK1_SW0_CL4_CNTL 1767 #define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1768 #define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1769 #define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1770 #define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1771 #define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1772 #define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1773 //DMA_CLK1_SW1_CL0_CNTL 1774 #define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1775 #define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1776 #define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1777 #define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1778 #define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1779 #define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1780 //DMA_CLK1_SW1_CL1_CNTL 1781 #define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1782 #define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1783 #define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1784 #define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1785 #define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1786 #define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1787 //DMA_CLK1_SW1_CL2_CNTL 1788 #define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1789 #define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1790 #define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1791 #define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1792 #define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1793 #define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1794 //DMA_CLK1_SW1_CL3_CNTL 1795 #define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1796 #define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1797 #define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1798 #define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1799 #define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1800 #define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1801 //DMA_CLK1_SW1_CL4_CNTL 1802 #define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1803 #define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1804 #define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1805 #define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1806 #define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1807 #define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1808 1809 1810 // addressBlock: gdc_ras_gdc_ras_regblk 1811 //GDC_RAS_LEAF0_CTRL 1812 #define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 1813 #define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1814 #define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 1815 #define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 1816 #define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1817 #define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 1818 #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1819 #define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 1820 #define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 1821 #define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 1822 #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1823 #define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 1824 //GDC_RAS_LEAF1_CTRL 1825 #define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 1826 #define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1827 #define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 1828 #define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 1829 #define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1830 #define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 1831 #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1832 #define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 1833 #define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 1834 #define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 1835 #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1836 #define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 1837 //GDC_RAS_LEAF2_CTRL 1838 #define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 1839 #define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1840 #define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 1841 #define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 1842 #define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1843 #define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 1844 #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1845 #define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 1846 #define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 1847 #define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 1848 #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1849 #define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 1850 //GDC_RAS_LEAF3_CTRL 1851 #define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 1852 #define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1853 #define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 1854 #define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 1855 #define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1856 #define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 1857 #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1858 #define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 1859 #define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 1860 #define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 1861 #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1862 #define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 1863 //GDC_RAS_LEAF4_CTRL 1864 #define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 1865 #define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1866 #define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 1867 #define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 1868 #define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1869 #define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 1870 #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1871 #define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 1872 #define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 1873 #define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 1874 #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1875 #define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 1876 //GDC_RAS_LEAF5_CTRL 1877 #define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 1878 #define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1879 #define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 1880 #define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 1881 #define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1882 #define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 1883 #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1884 #define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 1885 #define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 1886 #define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 1887 #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1888 #define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 1889 1890 1891 // addressBlock: gdc_rst_GDCRST_DEC 1892 //SHUB_PF_FLR_RST 1893 #define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0 1894 #define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1 1895 #define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2 1896 #define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3 1897 #define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4 1898 #define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5 1899 #define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6 1900 #define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7 1901 //SHUB_GFX_DRV_MODE1_RST 1902 #define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 1903 //SHUB_LINK_RESET 1904 #define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0 1905 //SHUB_PF0_VF_FLR_RST 1906 #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 1907 #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 1908 #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 1909 #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 1910 #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 1911 #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 1912 #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 1913 #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 1914 #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 1915 #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 1916 #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa 1917 #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb 1918 #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc 1919 #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd 1920 #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe 1921 #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf 1922 #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f 1923 //SHUB_HARD_RST_CTRL 1924 #define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 1925 #define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 1926 #define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 1927 #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 1928 #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 1929 //SHUB_SOFT_RST_CTRL 1930 #define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 1931 #define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 1932 #define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 1933 #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 1934 #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 1935 //SHUB_SDP_PORT_RST 1936 #define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 1937 1938 1939 // addressBlock: bif_bx_pf_SYSDEC 1940 //SBIOS_SCRATCH_0 1941 #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 1942 //SBIOS_SCRATCH_1 1943 #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 1944 //SBIOS_SCRATCH_2 1945 #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 1946 //SBIOS_SCRATCH_3 1947 #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 1948 //BIOS_SCRATCH_0 1949 #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 1950 //BIOS_SCRATCH_1 1951 #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 1952 //BIOS_SCRATCH_2 1953 #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 1954 //BIOS_SCRATCH_3 1955 #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 1956 //BIOS_SCRATCH_4 1957 #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 1958 //BIOS_SCRATCH_5 1959 #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 1960 //BIOS_SCRATCH_6 1961 #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 1962 //BIOS_SCRATCH_7 1963 #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 1964 //BIOS_SCRATCH_8 1965 #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 1966 //BIOS_SCRATCH_9 1967 #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 1968 //BIOS_SCRATCH_10 1969 #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 1970 //BIOS_SCRATCH_11 1971 #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 1972 //BIOS_SCRATCH_12 1973 #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 1974 //BIOS_SCRATCH_13 1975 #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 1976 //BIOS_SCRATCH_14 1977 #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 1978 //BIOS_SCRATCH_15 1979 #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 1980 //BIF_RLC_INTR_CNTL 1981 #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 1982 #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 1983 #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 1984 #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 1985 //BIF_VCE_INTR_CNTL 1986 #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 1987 #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 1988 #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 1989 #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 1990 //BIF_UVD_INTR_CNTL 1991 #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 1992 #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 1993 #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 1994 #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 1995 //GFX_MMIOREG_CAM_ADDR0 1996 #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 1997 //GFX_MMIOREG_CAM_REMAP_ADDR0 1998 #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 1999 //GFX_MMIOREG_CAM_ADDR1 2000 #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 2001 //GFX_MMIOREG_CAM_REMAP_ADDR1 2002 #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 2003 //GFX_MMIOREG_CAM_ADDR2 2004 #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 2005 //GFX_MMIOREG_CAM_REMAP_ADDR2 2006 #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 2007 //GFX_MMIOREG_CAM_ADDR3 2008 #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 2009 //GFX_MMIOREG_CAM_REMAP_ADDR3 2010 #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 2011 //GFX_MMIOREG_CAM_ADDR4 2012 #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 2013 //GFX_MMIOREG_CAM_REMAP_ADDR4 2014 #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 2015 //GFX_MMIOREG_CAM_ADDR5 2016 #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 2017 //GFX_MMIOREG_CAM_REMAP_ADDR5 2018 #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 2019 //GFX_MMIOREG_CAM_ADDR6 2020 #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 2021 //GFX_MMIOREG_CAM_REMAP_ADDR6 2022 #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 2023 //GFX_MMIOREG_CAM_ADDR7 2024 #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 2025 //GFX_MMIOREG_CAM_REMAP_ADDR7 2026 #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 2027 //GFX_MMIOREG_CAM_CNTL 2028 #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 2029 //GFX_MMIOREG_CAM_ZERO_CPL 2030 #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 2031 //GFX_MMIOREG_CAM_ONE_CPL 2032 #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 2033 //GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 2034 #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 2035 2036 2037 // addressBlock: bif_bx_pf_SYSPFVFDEC 2038 //MM_INDEX 2039 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 2040 #define MM_INDEX__MM_APER__SHIFT 0x1f 2041 //MM_DATA 2042 #define MM_DATA__MM_DATA__SHIFT 0x0 2043 //MM_INDEX_HI 2044 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 2045 //SYSHUB_INDEX_OVLP 2046 #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 2047 //SYSHUB_DATA_OVLP 2048 #define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 2049 //PCIE_INDEX 2050 #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 2051 //PCIE_DATA 2052 #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 2053 //PCIE_INDEX2 2054 #define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 2055 //PCIE_DATA2 2056 #define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 2057 2058 2059 // addressBlock: rcc_dwn_BIFDEC1 2060 //DN_PCIE_RESERVED 2061 #define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 2062 //DN_PCIE_SCRATCH 2063 #define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 2064 //DN_PCIE_CNTL 2065 #define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 2066 #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 2067 #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 2068 //DN_PCIE_CONFIG_CNTL 2069 #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 2070 //DN_PCIE_RX_CNTL2 2071 #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c 2072 //DN_PCIE_BUS_CNTL 2073 #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2074 #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 2075 //DN_PCIE_CFG_CNTL 2076 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2077 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2078 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2079 //DN_PCIE_STRAP_F0 2080 #define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 2081 #define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 2082 #define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 2083 //DN_PCIE_STRAP_MISC 2084 #define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 2085 #define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 2086 //DN_PCIE_STRAP_MISC2 2087 #define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 2088 2089 2090 // addressBlock: rcc_dwnp_BIFDEC1 2091 //PCIEP_RESERVED 2092 #define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 2093 //PCIEP_SCRATCH 2094 #define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 2095 //PCIE_ERR_CNTL 2096 #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 2097 #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 2098 #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb 2099 #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 2100 //PCIE_RX_CNTL 2101 #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 2102 #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 2103 #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 2104 #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 2105 #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b 2106 //PCIE_LC_SPEED_CNTL 2107 #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 2108 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 2109 //PCIE_LC_CNTL2 2110 #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b 2111 //PCIEP_STRAP_MISC 2112 #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa 2113 //LTR_MSG_INFO_FROM_EP 2114 #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 2115 2116 2117 // addressBlock: rcc_ep_BIFDEC1 2118 //EP_PCIE_SCRATCH 2119 #define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 2120 //EP_PCIE_CNTL 2121 #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 2122 #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 2123 #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 2124 //EP_PCIE_INT_CNTL 2125 #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 2126 #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 2127 #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 2128 #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 2129 #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 2130 #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 2131 //EP_PCIE_INT_STATUS 2132 #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 2133 #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 2134 #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 2135 #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 2136 #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 2137 #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 2138 //EP_PCIE_RX_CNTL2 2139 #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 2140 //EP_PCIE_BUS_CNTL 2141 #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2142 //EP_PCIE_CFG_CNTL 2143 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2144 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2145 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2146 //EP_PCIE_OBFF_CNTL 2147 #define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 2148 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 2149 #define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 2150 #define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 2151 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 2152 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 2153 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc 2154 #define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 2155 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 2156 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 2157 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 2158 #define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 2159 //EP_PCIE_TX_LTR_CNTL 2160 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 2161 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 2162 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 2163 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 2164 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa 2165 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd 2166 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe 2167 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf 2168 #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 2169 //EP_PCIE_STRAP_MISC 2170 #define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 2171 //EP_PCIE_STRAP_MISC2 2172 #define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 2173 //EP_PCIE_STRAP_PI 2174 //EP_PCIE_F0_DPA_CAP 2175 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 2176 #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 2177 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 2178 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 2179 //EP_PCIE_F0_DPA_LATENCY_INDICATOR 2180 #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 2181 //EP_PCIE_F0_DPA_CNTL 2182 #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 2183 #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 2184 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 2185 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2186 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 2187 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2188 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 2189 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2190 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 2191 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2192 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 2193 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2194 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 2195 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2196 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 2197 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2198 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 2199 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2200 //EP_PCIE_PME_CONTROL 2201 #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 2202 //EP_PCIEP_RESERVED 2203 #define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 2204 //EP_PCIE_TX_CNTL 2205 #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa 2206 #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc 2207 #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 2208 #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 2209 #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a 2210 //EP_PCIE_TX_REQUESTER_ID 2211 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 2212 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 2213 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 2214 //EP_PCIE_ERR_CNTL 2215 #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 2216 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 2217 #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 2218 #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 2219 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 2220 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 2221 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a 2222 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b 2223 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c 2224 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d 2225 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e 2226 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f 2227 //EP_PCIE_RX_CNTL 2228 #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 2229 #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 2230 #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 2231 #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 2232 #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 2233 #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 2234 #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 2235 #define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a 2236 //EP_PCIE_LC_SPEED_CNTL 2237 #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 2238 #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 2239 2240 2241 // addressBlock: bif_bx_pf_BIFDEC1 2242 //BIF_MM_INDACCESS_CNTL 2243 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 2244 //BUS_CNTL 2245 #define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 2246 #define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 2247 #define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 2248 #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 2249 #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 2250 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 2251 #define BUS_CNTL__SET_MC_TC__SHIFT 0xd 2252 #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 2253 #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 2254 #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 2255 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 2256 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 2257 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 2258 #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 2259 #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 2260 #define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 2261 //BIF_SCRATCH0 2262 #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 2263 //BIF_SCRATCH1 2264 #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 2265 //BX_RESET_EN 2266 #define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 2267 #define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 2268 #define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 2269 #define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 2270 #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 2271 //MM_CFGREGS_CNTL 2272 #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 2273 #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 2274 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f 2275 //BX_RESET_CNTL 2276 #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 2277 //INTERRUPT_CNTL 2278 #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 2279 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 2280 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 2281 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 2282 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 2283 #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf 2284 //INTERRUPT_CNTL2 2285 #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 2286 //CLKREQB_PAD_CNTL 2287 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 2288 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 2289 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 2290 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 2291 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 2292 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 2293 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 2294 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 2295 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 2296 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 2297 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb 2298 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc 2299 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd 2300 #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 2301 //CLKREQB_PERF_COUNTER 2302 #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 2303 //BIF_CLK_CTRL 2304 #define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 2305 #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 2306 //BIF_FEATURES_CONTROL_MISC 2307 #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 2308 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 2309 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 2310 #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 2311 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 2312 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 2313 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb 2314 #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc 2315 #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd 2316 #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf 2317 #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 2318 #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 2319 #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 2320 //BIF_DOORBELL_CNTL 2321 #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 2322 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 2323 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 2324 #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 2325 #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 2326 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 2327 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 2328 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a 2329 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b 2330 //BIF_DOORBELL_INT_CNTL 2331 #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 2332 #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 2333 #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 2334 #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 2335 //BIF_SLVARB_MODE 2336 #define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 2337 //BIF_FB_EN 2338 #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 2339 #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 2340 //BIF_BUSY_DELAY_CNTR 2341 #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 2342 //BIF_PERFMON_CNTL 2343 #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 2344 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 2345 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 2346 #define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 2347 #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd 2348 //BIF_PERFCOUNTER0_RESULT 2349 #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 2350 //BIF_PERFCOUNTER1_RESULT 2351 #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 2352 //BIF_MST_TRANS_PENDING_VF 2353 #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 2354 //BIF_SLV_TRANS_PENDING_VF 2355 #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 2356 //BACO_CNTL 2357 #define BACO_CNTL__BACO_EN__SHIFT 0x0 2358 #define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 2359 #define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 2360 #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 2361 #define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 2362 #define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 2363 #define BACO_CNTL__BACO_MODE__SHIFT 0x8 2364 #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 2365 #define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f 2366 //BIF_BACO_EXIT_TIME0 2367 #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 2368 //BIF_BACO_EXIT_TIMER1 2369 #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 2370 #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a 2371 #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b 2372 #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c 2373 #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d 2374 #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f 2375 //BIF_BACO_EXIT_TIMER2 2376 #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 2377 //BIF_BACO_EXIT_TIMER3 2378 #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 2379 //BIF_BACO_EXIT_TIMER4 2380 #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 2381 //MEM_TYPE_CNTL 2382 #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 2383 //SMU_BIF_VDDGFX_PWR_STATUS 2384 #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 2385 //BIF_VDDGFX_GFX0_LOWER 2386 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 2387 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e 2388 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f 2389 //BIF_VDDGFX_GFX0_UPPER 2390 #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 2391 //BIF_VDDGFX_GFX1_LOWER 2392 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 2393 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e 2394 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f 2395 //BIF_VDDGFX_GFX1_UPPER 2396 #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 2397 //BIF_VDDGFX_GFX2_LOWER 2398 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 2399 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e 2400 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f 2401 //BIF_VDDGFX_GFX2_UPPER 2402 #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 2403 //BIF_VDDGFX_GFX3_LOWER 2404 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 2405 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e 2406 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f 2407 //BIF_VDDGFX_GFX3_UPPER 2408 #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 2409 //BIF_VDDGFX_GFX4_LOWER 2410 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 2411 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e 2412 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f 2413 //BIF_VDDGFX_GFX4_UPPER 2414 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 2415 //BIF_VDDGFX_GFX5_LOWER 2416 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 2417 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e 2418 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f 2419 //BIF_VDDGFX_GFX5_UPPER 2420 #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 2421 //BIF_VDDGFX_RSV1_LOWER 2422 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 2423 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e 2424 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f 2425 //BIF_VDDGFX_RSV1_UPPER 2426 #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 2427 //BIF_VDDGFX_RSV2_LOWER 2428 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 2429 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e 2430 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f 2431 //BIF_VDDGFX_RSV2_UPPER 2432 #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 2433 //BIF_VDDGFX_RSV3_LOWER 2434 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 2435 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e 2436 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f 2437 //BIF_VDDGFX_RSV3_UPPER 2438 #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 2439 //BIF_VDDGFX_RSV4_LOWER 2440 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 2441 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e 2442 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f 2443 //BIF_VDDGFX_RSV4_UPPER 2444 #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 2445 //BIF_VDDGFX_FB_CMP 2446 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 2447 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 2448 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 2449 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 2450 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 2451 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 2452 //BIF_DOORBELL_GBLAPER1_LOWER 2453 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 2454 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f 2455 //BIF_DOORBELL_GBLAPER1_UPPER 2456 #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 2457 //BIF_DOORBELL_GBLAPER2_LOWER 2458 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 2459 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f 2460 //BIF_DOORBELL_GBLAPER2_UPPER 2461 #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 2462 //REMAP_HDP_MEM_FLUSH_CNTL 2463 #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 2464 //REMAP_HDP_REG_FLUSH_CNTL 2465 #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 2466 //BIF_RB_CNTL 2467 #define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 2468 #define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 2469 #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 2470 #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 2471 #define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 2472 #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 2473 //BIF_RB_BASE 2474 #define BIF_RB_BASE__ADDR__SHIFT 0x0 2475 //BIF_RB_RPTR 2476 #define BIF_RB_RPTR__OFFSET__SHIFT 0x2 2477 //BIF_RB_WPTR 2478 #define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 2479 #define BIF_RB_WPTR__OFFSET__SHIFT 0x2 2480 //BIF_RB_WPTR_ADDR_HI 2481 #define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 2482 //BIF_RB_WPTR_ADDR_LO 2483 #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 2484 //MAILBOX_INDEX 2485 #define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 2486 //BIF_GPUIOV_RESET_NOTIFICATION 2487 #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 2488 //BIF_UVD_GPUIOV_CFG_SIZE 2489 #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 2490 //BIF_VCE_GPUIOV_CFG_SIZE 2491 #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 2492 //BIF_GFX_SDMA_GPUIOV_CFG_SIZE 2493 #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 2494 //BIF_GMI_WRR_WEIGHT 2495 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 2496 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 2497 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 2498 //NBIF_STRAP_WRITE_CTRL 2499 #define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 2500 //BIF_PERSTB_PAD_CNTL 2501 #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 2502 //BIF_PX_EN_PAD_CNTL 2503 #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 2504 //BIF_REFPADKIN_PAD_CNTL 2505 #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 2506 //BIF_CLKREQB_PAD_CNTL 2507 #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 2508 2509 2510 // addressBlock: rcc_pf_0_BIFDEC1 2511 //RCC_BACO_CNTL_MISC 2512 #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 2513 #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 2514 //RCC_RESET_EN 2515 #define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf 2516 //RCC_VDM_SUPPORT 2517 #define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 2518 #define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 2519 #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 2520 #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 2521 #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 2522 //RCC_PEER_REG_RANGE0 2523 #define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 2524 #define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 2525 //RCC_PEER_REG_RANGE1 2526 #define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 2527 #define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 2528 //RCC_BUS_CNTL 2529 #define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 2530 #define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 2531 #define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 2532 #define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 2533 #define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 2534 #define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 2535 #define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 2536 #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc 2537 #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd 2538 #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 2539 #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 2540 #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 2541 #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 2542 #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 2543 #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 2544 #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 2545 #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 2546 #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c 2547 #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d 2548 //RCC_CONFIG_CNTL 2549 #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 2550 #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 2551 #define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 2552 //RCC_CONFIG_F0_BASE 2553 #define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 2554 //RCC_CONFIG_APER_SIZE 2555 #define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 2556 //RCC_CONFIG_REG_APER_SIZE 2557 #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 2558 //RCC_XDMA_LO 2559 #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 2560 #define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f 2561 //RCC_XDMA_HI 2562 #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 2563 //RCC_FEATURES_CONTROL_MISC 2564 #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 2565 #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 2566 #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 2567 #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 2568 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 2569 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa 2570 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb 2571 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc 2572 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd 2573 #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe 2574 #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf 2575 #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 2576 #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 2577 #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 2578 //RCC_BUSNUM_CNTL1 2579 #define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 2580 //RCC_BUSNUM_LIST0 2581 #define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 2582 #define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 2583 #define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 2584 #define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 2585 //RCC_BUSNUM_LIST1 2586 #define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 2587 #define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 2588 #define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 2589 #define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 2590 //RCC_BUSNUM_CNTL2 2591 #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 2592 #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 2593 #define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 2594 #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 2595 //RCC_CAPTURE_HOST_BUSNUM 2596 #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 2597 //RCC_HOST_BUSNUM 2598 #define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 2599 //RCC_PEER0_FB_OFFSET_HI 2600 #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 2601 //RCC_PEER0_FB_OFFSET_LO 2602 #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 2603 #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f 2604 //RCC_PEER1_FB_OFFSET_HI 2605 #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 2606 //RCC_PEER1_FB_OFFSET_LO 2607 #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 2608 #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f 2609 //RCC_PEER2_FB_OFFSET_HI 2610 #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 2611 //RCC_PEER2_FB_OFFSET_LO 2612 #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 2613 #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f 2614 //RCC_PEER3_FB_OFFSET_HI 2615 #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 2616 //RCC_PEER3_FB_OFFSET_LO 2617 #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 2618 #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f 2619 //RCC_DEVFUNCNUM_LIST0 2620 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 2621 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 2622 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 2623 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 2624 //RCC_DEVFUNCNUM_LIST1 2625 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 2626 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 2627 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 2628 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 2629 //RCC_DEV0_LINK_CNTL 2630 #define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 2631 #define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 2632 //RCC_CMN_LINK_CNTL 2633 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 2634 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 2635 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 2636 #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 2637 //RCC_EP_REQUESTERID_RESTORE 2638 #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 2639 #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 2640 //RCC_LTR_LSWITCH_CNTL 2641 #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 2642 //RCC_MH_ARB_CNTL 2643 #define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 2644 #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 2645 2646 2647 // addressBlock: rcc_pf_0_BIFDEC2 2648 //GFXMSIX_VECT0_ADDR_LO 2649 #define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2650 //GFXMSIX_VECT0_ADDR_HI 2651 #define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2652 //GFXMSIX_VECT0_MSG_DATA 2653 #define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 2654 //GFXMSIX_VECT0_CONTROL 2655 #define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 2656 //GFXMSIX_VECT1_ADDR_LO 2657 #define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2658 //GFXMSIX_VECT1_ADDR_HI 2659 #define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2660 //GFXMSIX_VECT1_MSG_DATA 2661 #define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 2662 //GFXMSIX_VECT1_CONTROL 2663 #define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 2664 //GFXMSIX_VECT2_ADDR_LO 2665 #define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2666 //GFXMSIX_VECT2_ADDR_HI 2667 #define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2668 //GFXMSIX_VECT2_MSG_DATA 2669 #define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 2670 //GFXMSIX_VECT2_CONTROL 2671 #define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 2672 //GFXMSIX_PBA 2673 #define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 2674 #define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 2675 #define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 2676 2677 2678 // addressBlock: rcc_strap_BIFDEC1 2679 //RCC_DEV0_PORT_STRAP0 2680 #define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 2681 #define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 2682 #define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 2683 #define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 2684 #define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 2685 #define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 2686 #define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 2687 #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 2688 #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c 2689 #define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f 2690 //RCC_DEV0_PORT_STRAP1 2691 #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 2692 #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 2693 //RCC_DEV0_PORT_STRAP2 2694 #define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 2695 #define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 2696 #define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 2697 #define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 2698 #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 2699 #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 2700 #define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 2701 #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 2702 #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 2703 #define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 2704 #define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc 2705 #define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd 2706 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe 2707 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf 2708 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 2709 #define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 2710 #define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 2711 #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 2712 #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 2713 #define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a 2714 #define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d 2715 //RCC_DEV0_PORT_STRAP3 2716 #define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 2717 #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 2718 #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 2719 #define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 2720 #define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 2721 #define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 2722 #define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 2723 #define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 2724 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb 2725 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe 2726 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 2727 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 2728 #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 2729 #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b 2730 #define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d 2731 #define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e 2732 #define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f 2733 //RCC_DEV0_PORT_STRAP4 2734 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 2735 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 2736 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 2737 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 2738 //RCC_DEV0_PORT_STRAP5 2739 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 2740 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 2741 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 2742 #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 2743 #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 2744 #define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 2745 #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 2746 #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 2747 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 2748 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 2749 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 2750 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a 2751 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b 2752 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c 2753 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d 2754 #define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e 2755 #define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f 2756 //RCC_DEV0_PORT_STRAP6 2757 #define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 2758 #define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 2759 //RCC_DEV0_PORT_STRAP7 2760 #define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 2761 #define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 2762 #define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc 2763 #define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 2764 #define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 2765 #define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d 2766 //RCC_DEV0_EPF0_STRAP0 2767 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 2768 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 2769 #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 2770 #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 2771 #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c 2772 #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d 2773 #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e 2774 #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f 2775 //RCC_DEV0_EPF0_STRAP1 2776 #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 2777 #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 2778 //RCC_DEV0_EPF0_STRAP13 2779 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 2780 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 2781 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 2782 //RCC_DEV0_EPF0_STRAP2 2783 #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 2784 #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 2785 #define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 2786 #define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 2787 #define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 2788 #define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 2789 #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe 2790 #define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf 2791 #define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 2792 #define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 2793 #define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 2794 #define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 2795 #define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 2796 #define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 2797 #define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 2798 #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 2799 #define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b 2800 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c 2801 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d 2802 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e 2803 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f 2804 //RCC_DEV0_EPF0_STRAP3 2805 #define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 2806 #define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 2807 #define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 2808 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 2809 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 2810 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 2811 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 2812 #define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 2813 #define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 2814 #define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a 2815 #define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b 2816 //RCC_DEV0_EPF0_STRAP4 2817 #define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 2818 #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 2819 #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 2820 #define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 2821 #define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 2822 #define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c 2823 #define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f 2824 //RCC_DEV0_EPF0_STRAP5 2825 #define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 2826 //RCC_DEV0_EPF0_STRAP8 2827 #define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 2828 #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 2829 #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 2830 #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 2831 #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 2832 #define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 2833 #define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 2834 #define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 2835 #define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc 2836 #define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe 2837 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 2838 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 2839 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 2840 #define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 2841 #define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 2842 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a 2843 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b 2844 #define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e 2845 //RCC_DEV0_EPF0_STRAP9 2846 //RCC_DEV0_EPF1_STRAP0 2847 #define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 2848 #define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 2849 #define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 2850 #define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c 2851 #define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d 2852 #define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e 2853 #define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f 2854 //RCC_DEV0_EPF1_STRAP10 2855 #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 2856 #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2857 //RCC_DEV0_EPF1_STRAP11 2858 #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 2859 #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2860 //RCC_DEV0_EPF1_STRAP12 2861 #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 2862 #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2863 //RCC_DEV0_EPF1_STRAP13 2864 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 2865 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 2866 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 2867 //RCC_DEV0_EPF1_STRAP2 2868 #define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 2869 #define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 2870 #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe 2871 #define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 2872 #define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 2873 #define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 2874 #define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 2875 #define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 2876 #define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 2877 #define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 2878 #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 2879 //RCC_DEV0_EPF1_STRAP3 2880 #define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 2881 #define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 2882 #define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 2883 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 2884 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 2885 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 2886 #define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 2887 #define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 2888 #define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a 2889 #define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b 2890 //RCC_DEV0_EPF1_STRAP4 2891 #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 2892 #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 2893 #define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 2894 #define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 2895 #define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c 2896 #define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f 2897 //RCC_DEV0_EPF1_STRAP5 2898 #define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 2899 //RCC_DEV0_EPF1_STRAP6 2900 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 2901 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 2902 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 2903 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 2904 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 2905 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 2906 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 2907 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 2908 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 2909 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 2910 //RCC_DEV0_EPF1_STRAP7 2911 #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 2912 #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 2913 2914 2915 // addressBlock: bif_bx_pf_BIFPFVFDEC1 2916 //BIF_BME_STATUS 2917 #define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 2918 #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 2919 //BIF_ATOMIC_ERR_LOG 2920 #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 2921 #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 2922 #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 2923 #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 2924 //DOORBELL_SELFRING_GPA_APER_BASE_HIGH 2925 #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 2926 //DOORBELL_SELFRING_GPA_APER_BASE_LOW 2927 #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 2928 //DOORBELL_SELFRING_GPA_APER_CNTL 2929 #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 2930 #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 2931 //HDP_REG_COHERENCY_FLUSH_CNTL 2932 #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 2933 //HDP_MEM_COHERENCY_FLUSH_CNTL 2934 #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 2935 //GPU_HDP_FLUSH_REQ 2936 #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 2937 #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 2938 #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 2939 #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 2940 #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 2941 #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 2942 #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 2943 #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 2944 #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 2945 #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 2946 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 2947 #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb 2948 //GPU_HDP_FLUSH_DONE 2949 #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 2950 #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 2951 #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 2952 #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 2953 #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 2954 #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 2955 #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 2956 #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 2957 #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 2958 #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 2959 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 2960 #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb 2961 //BIF_TRANS_PENDING 2962 #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 2963 #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 2964 //MAILBOX_MSGBUF_TRN_DW0 2965 #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 2966 //MAILBOX_MSGBUF_TRN_DW1 2967 #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 2968 //MAILBOX_MSGBUF_TRN_DW2 2969 #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 2970 //MAILBOX_MSGBUF_TRN_DW3 2971 #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 2972 //MAILBOX_MSGBUF_RCV_DW0 2973 #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 2974 //MAILBOX_MSGBUF_RCV_DW1 2975 #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 2976 //MAILBOX_MSGBUF_RCV_DW2 2977 #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 2978 //MAILBOX_MSGBUF_RCV_DW3 2979 #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 2980 //MAILBOX_CONTROL 2981 #define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 2982 #define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 2983 #define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 2984 #define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 2985 //MAILBOX_INT_CNTL 2986 #define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 2987 #define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 2988 //BIF_VMHV_MAILBOX 2989 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 2990 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 2991 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 2992 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf 2993 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 2994 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 2995 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 2996 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 2997 2998 2999 // addressBlock: rcc_pf_0_BIFPFVFDEC1 3000 //RCC_DOORBELL_APER_EN 3001 #define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 3002 //RCC_CONFIG_MEMSIZE 3003 #define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 3004 //RCC_CONFIG_RESERVED 3005 #define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 3006 //RCC_IOV_FUNC_IDENTIFIER 3007 #define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 3008 #define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f 3009 3010 3011 // addressBlock: syshub_mmreg_ind_syshubdec 3012 //SYSHUB_INDEX 3013 #define SYSHUB_INDEX__INDEX__SHIFT 0x0 3014 //SYSHUB_DATA 3015 #define SYSHUB_DATA__DATA__SHIFT 0x0 3016 3017 3018 // addressBlock: rcc_strap_rcc_strap_internal 3019 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 3020 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 3021 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 3022 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 3023 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 3024 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 3025 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 3026 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 3027 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 3028 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c 3029 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f 3030 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 3031 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 3032 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 3033 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 3034 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 3035 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 3036 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 3037 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 3038 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 3039 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 3040 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 3041 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 3042 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 3043 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 3044 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc 3045 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd 3046 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe 3047 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf 3048 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 3049 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 3050 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 3051 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 3052 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 3053 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a 3054 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d 3055 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 3056 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 3057 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 3058 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 3059 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 3060 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 3061 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 3062 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 3063 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 3064 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb 3065 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe 3066 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 3067 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 3068 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 3069 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b 3070 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d 3071 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e 3072 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f 3073 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 3074 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 3075 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 3076 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 3077 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 3078 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 3079 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 3080 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 3081 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 3082 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 3083 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 3084 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 3085 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 3086 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 3087 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 3088 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 3089 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 3090 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a 3091 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b 3092 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c 3093 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d 3094 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e 3095 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f 3096 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 3097 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 3098 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 3099 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 3100 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 3101 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 3102 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc 3103 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 3104 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 3105 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d 3106 //RCC_DEV1_PORT_STRAP0 3107 #define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1 3108 #define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2 3109 #define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3 3110 #define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4 3111 #define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5 3112 #define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15 3113 #define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18 3114 #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19 3115 #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c 3116 #define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f 3117 //RCC_DEV1_PORT_STRAP1 3118 #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0 3119 #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10 3120 //RCC_DEV1_PORT_STRAP2 3121 #define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0 3122 #define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1 3123 #define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2 3124 #define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3 3125 #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4 3126 #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5 3127 #define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6 3128 #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7 3129 #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8 3130 #define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9 3131 #define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc 3132 #define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd 3133 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe 3134 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf 3135 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10 3136 #define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11 3137 #define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13 3138 #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14 3139 #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17 3140 #define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a 3141 #define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d 3142 //RCC_DEV1_PORT_STRAP3 3143 #define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0 3144 #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1 3145 #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2 3146 #define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3 3147 #define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6 3148 #define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7 3149 #define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8 3150 #define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9 3151 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb 3152 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe 3153 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12 3154 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15 3155 #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19 3156 #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b 3157 #define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d 3158 #define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e 3159 #define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f 3160 //RCC_DEV1_PORT_STRAP4 3161 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0 3162 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8 3163 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10 3164 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18 3165 //RCC_DEV1_PORT_STRAP5 3166 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0 3167 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8 3168 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10 3169 #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11 3170 #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12 3171 #define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13 3172 #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14 3173 #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15 3174 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17 3175 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18 3176 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19 3177 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a 3178 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b 3179 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c 3180 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d 3181 #define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e 3182 #define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f 3183 //RCC_DEV1_PORT_STRAP6 3184 #define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0 3185 #define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1 3186 //RCC_DEV1_PORT_STRAP7 3187 #define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0 3188 #define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8 3189 #define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc 3190 #define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10 3191 #define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18 3192 #define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d 3193 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 3194 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 3195 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 3196 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 3197 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 3198 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c 3199 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d 3200 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e 3201 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f 3202 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 3203 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 3204 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 3205 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 3206 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 3207 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 3208 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 3209 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 3210 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 3211 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 3212 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe 3213 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf 3214 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 3215 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 3216 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 3217 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 3218 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 3219 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 3220 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 3221 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 3222 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b 3223 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c 3224 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d 3225 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e 3226 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f 3227 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 3228 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 3229 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 3230 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 3231 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 3232 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 3233 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 3234 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 3235 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 3236 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 3237 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a 3238 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b 3239 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 3240 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 3241 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 3242 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 3243 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 3244 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 3245 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c 3246 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f 3247 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 3248 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 3249 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 3250 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 3251 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 3252 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 3253 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 3254 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 3255 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 3256 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 3257 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 3258 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc 3259 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe 3260 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 3261 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 3262 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 3263 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 3264 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 3265 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a 3266 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b 3267 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e 3268 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 3269 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 3270 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 3271 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 3272 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 3273 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 3274 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 3275 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 3276 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 3277 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c 3278 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d 3279 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e 3280 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f 3281 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 3282 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 3283 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 3284 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe 3285 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 3286 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 3287 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 3288 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 3289 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 3290 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 3291 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 3292 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 3293 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 3294 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 3295 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 3296 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 3297 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 3298 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 3299 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 3300 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 3301 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 3302 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a 3303 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b 3304 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 3305 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 3306 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 3307 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 3308 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 3309 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c 3310 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f 3311 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 3312 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 3313 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 3314 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 3315 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 3316 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 3317 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 3318 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 3319 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 3320 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 3321 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 3322 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 3323 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 3324 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 3325 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 3326 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 3327 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 3328 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 3329 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3330 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 3331 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 3332 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3333 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 3334 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 3335 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3336 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 3337 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 3338 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 3339 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 3340 //RCC_DEV0_EPF2_STRAP0 3341 #define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 3342 #define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 3343 #define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 3344 #define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c 3345 #define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d 3346 #define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e 3347 #define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f 3348 //RCC_DEV0_EPF2_STRAP2 3349 #define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 3350 #define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 3351 #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe 3352 #define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 3353 #define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 3354 #define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 3355 #define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 3356 #define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 3357 #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 3358 //RCC_DEV0_EPF2_STRAP3 3359 #define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0 3360 #define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1 3361 #define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2 3362 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 3363 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 3364 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 3365 #define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 3366 #define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19 3367 #define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a 3368 #define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b 3369 //RCC_DEV0_EPF2_STRAP4 3370 #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 3371 #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 3372 #define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 3373 #define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 3374 #define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c 3375 #define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f 3376 //RCC_DEV0_EPF2_STRAP5 3377 #define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 3378 #define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18 3379 //RCC_DEV0_EPF2_STRAP6 3380 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 3381 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1 3382 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4 3383 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8 3384 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9 3385 //RCC_DEV0_EPF2_STRAP13 3386 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 3387 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 3388 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 3389 //RCC_DEV0_EPF3_STRAP0 3390 #define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 3391 #define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 3392 #define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 3393 #define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c 3394 #define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d 3395 #define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e 3396 #define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f 3397 //RCC_DEV0_EPF3_STRAP2 3398 #define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 3399 #define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 3400 #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe 3401 #define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 3402 #define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 3403 #define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 3404 #define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 3405 #define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 3406 #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 3407 //RCC_DEV0_EPF3_STRAP3 3408 #define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0 3409 #define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1 3410 #define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2 3411 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 3412 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 3413 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 3414 #define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 3415 #define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19 3416 #define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a 3417 #define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b 3418 //RCC_DEV0_EPF3_STRAP4 3419 #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 3420 #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 3421 #define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 3422 #define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 3423 #define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c 3424 #define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f 3425 //RCC_DEV0_EPF3_STRAP5 3426 #define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 3427 #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10 3428 #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14 3429 //RCC_DEV0_EPF3_STRAP6 3430 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 3431 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1 3432 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4 3433 //RCC_DEV0_EPF3_STRAP13 3434 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 3435 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 3436 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 3437 //RCC_DEV0_EPF4_STRAP0 3438 #define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0 3439 #define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10 3440 #define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14 3441 #define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c 3442 #define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d 3443 #define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e 3444 #define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f 3445 //RCC_DEV0_EPF4_STRAP2 3446 #define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7 3447 #define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8 3448 #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe 3449 #define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10 3450 #define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11 3451 #define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14 3452 #define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15 3453 #define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17 3454 #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18 3455 //RCC_DEV0_EPF4_STRAP3 3456 #define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0 3457 #define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1 3458 #define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2 3459 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12 3460 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13 3461 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14 3462 #define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18 3463 #define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19 3464 #define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a 3465 #define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b 3466 //RCC_DEV0_EPF4_STRAP4 3467 #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14 3468 #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15 3469 #define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16 3470 #define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17 3471 #define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c 3472 #define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f 3473 //RCC_DEV0_EPF4_STRAP5 3474 #define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0 3475 #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10 3476 #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14 3477 //RCC_DEV0_EPF4_STRAP6 3478 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0 3479 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1 3480 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4 3481 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8 3482 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9 3483 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10 3484 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11 3485 //RCC_DEV0_EPF4_STRAP13 3486 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0 3487 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8 3488 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10 3489 //RCC_DEV0_EPF5_STRAP0 3490 #define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0 3491 #define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10 3492 #define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14 3493 #define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c 3494 #define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d 3495 #define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e 3496 #define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f 3497 //RCC_DEV0_EPF5_STRAP2 3498 #define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7 3499 #define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8 3500 #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe 3501 #define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10 3502 #define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11 3503 #define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14 3504 #define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15 3505 #define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17 3506 #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18 3507 //RCC_DEV0_EPF5_STRAP3 3508 #define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0 3509 #define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1 3510 #define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2 3511 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12 3512 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13 3513 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14 3514 #define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18 3515 #define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19 3516 #define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a 3517 #define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b 3518 //RCC_DEV0_EPF5_STRAP4 3519 #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 3520 #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 3521 #define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 3522 #define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 3523 #define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c 3524 #define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f 3525 //RCC_DEV0_EPF5_STRAP5 3526 #define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0 3527 //RCC_DEV0_EPF5_STRAP6 3528 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0 3529 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1 3530 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4 3531 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8 3532 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9 3533 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10 3534 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11 3535 //RCC_DEV0_EPF5_STRAP13 3536 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0 3537 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8 3538 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10 3539 //RCC_DEV0_EPF6_STRAP0 3540 #define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0 3541 #define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10 3542 #define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14 3543 #define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c 3544 #define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d 3545 #define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e 3546 #define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f 3547 //RCC_DEV0_EPF6_STRAP2 3548 #define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7 3549 #define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8 3550 #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe 3551 #define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10 3552 #define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11 3553 #define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14 3554 #define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15 3555 #define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17 3556 #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18 3557 //RCC_DEV0_EPF6_STRAP3 3558 #define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0 3559 #define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1 3560 #define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2 3561 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12 3562 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13 3563 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14 3564 #define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18 3565 #define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19 3566 #define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a 3567 #define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b 3568 //RCC_DEV0_EPF6_STRAP4 3569 #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14 3570 #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15 3571 #define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16 3572 #define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17 3573 #define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c 3574 #define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f 3575 //RCC_DEV0_EPF6_STRAP5 3576 #define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0 3577 //RCC_DEV0_EPF6_STRAP6 3578 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0 3579 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1 3580 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4 3581 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8 3582 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9 3583 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10 3584 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11 3585 //RCC_DEV0_EPF6_STRAP13 3586 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0 3587 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8 3588 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10 3589 //RCC_DEV0_EPF7_STRAP0 3590 #define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0 3591 #define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10 3592 #define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14 3593 #define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c 3594 #define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d 3595 #define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e 3596 #define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f 3597 //RCC_DEV0_EPF7_STRAP2 3598 #define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7 3599 #define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8 3600 #define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe 3601 #define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10 3602 #define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11 3603 #define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14 3604 #define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15 3605 #define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17 3606 #define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18 3607 //RCC_DEV0_EPF7_STRAP3 3608 #define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0 3609 #define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1 3610 #define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2 3611 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12 3612 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13 3613 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14 3614 #define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18 3615 #define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19 3616 #define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a 3617 #define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b 3618 //RCC_DEV0_EPF7_STRAP4 3619 #define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14 3620 #define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15 3621 #define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16 3622 #define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17 3623 #define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c 3624 #define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f 3625 //RCC_DEV0_EPF7_STRAP5 3626 #define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0 3627 //RCC_DEV0_EPF7_STRAP6 3628 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0 3629 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1 3630 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4 3631 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8 3632 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9 3633 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10 3634 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11 3635 //RCC_DEV0_EPF7_STRAP13 3636 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0 3637 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8 3638 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10 3639 //RCC_DEV1_EPF0_STRAP0 3640 #define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0 3641 #define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10 3642 #define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14 3643 #define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c 3644 #define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d 3645 #define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e 3646 #define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f 3647 //RCC_DEV1_EPF0_STRAP2 3648 #define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7 3649 #define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8 3650 #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe 3651 #define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf 3652 #define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10 3653 #define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11 3654 #define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14 3655 #define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15 3656 #define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17 3657 #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18 3658 //RCC_DEV1_EPF0_STRAP3 3659 #define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0 3660 #define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1 3661 #define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2 3662 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12 3663 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13 3664 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14 3665 #define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18 3666 #define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19 3667 #define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a 3668 #define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b 3669 //RCC_DEV1_EPF0_STRAP4 3670 #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14 3671 #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15 3672 #define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16 3673 #define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17 3674 #define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c 3675 #define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f 3676 //RCC_DEV1_EPF0_STRAP5 3677 #define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0 3678 #define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18 3679 //RCC_DEV1_EPF0_STRAP6 3680 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0 3681 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1 3682 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4 3683 //RCC_DEV1_EPF0_STRAP13 3684 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0 3685 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8 3686 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10 3687 //RCC_DEV1_EPF1_STRAP0 3688 #define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0 3689 #define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10 3690 #define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14 3691 #define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c 3692 #define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d 3693 #define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e 3694 #define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f 3695 //RCC_DEV1_EPF1_STRAP2 3696 #define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7 3697 #define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8 3698 #define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe 3699 #define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10 3700 #define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11 3701 #define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14 3702 #define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15 3703 #define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17 3704 #define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18 3705 //RCC_DEV1_EPF1_STRAP3 3706 #define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0 3707 #define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1 3708 #define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2 3709 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12 3710 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13 3711 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14 3712 #define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18 3713 #define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19 3714 #define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a 3715 #define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b 3716 //RCC_DEV1_EPF1_STRAP4 3717 #define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14 3718 #define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15 3719 #define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16 3720 #define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17 3721 #define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c 3722 #define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f 3723 //RCC_DEV1_EPF1_STRAP5 3724 #define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0 3725 //RCC_DEV1_EPF1_STRAP6 3726 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0 3727 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1 3728 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4 3729 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8 3730 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9 3731 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10 3732 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11 3733 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18 3734 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19 3735 //RCC_DEV1_EPF1_STRAP13 3736 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0 3737 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8 3738 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10 3739 //RCC_DEV1_EPF2_STRAP0 3740 #define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0 3741 #define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10 3742 #define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14 3743 #define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c 3744 #define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d 3745 #define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e 3746 #define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f 3747 //RCC_DEV1_EPF2_STRAP2 3748 #define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7 3749 #define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8 3750 #define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe 3751 #define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10 3752 #define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11 3753 #define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14 3754 #define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15 3755 #define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17 3756 #define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18 3757 //RCC_DEV1_EPF2_STRAP3 3758 #define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0 3759 #define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1 3760 #define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2 3761 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12 3762 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13 3763 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14 3764 #define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18 3765 #define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19 3766 #define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a 3767 #define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b 3768 //RCC_DEV1_EPF2_STRAP4 3769 #define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14 3770 #define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15 3771 #define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16 3772 #define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17 3773 #define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c 3774 #define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f 3775 //RCC_DEV1_EPF2_STRAP5 3776 #define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0 3777 //RCC_DEV1_EPF2_STRAP6 3778 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0 3779 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1 3780 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4 3781 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8 3782 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9 3783 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10 3784 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11 3785 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18 3786 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19 3787 //RCC_DEV1_EPF2_STRAP13 3788 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0 3789 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8 3790 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10 3791 3792 3793 // addressBlock: bif_rst_bif_rst_regblk 3794 //HARD_RST_CTRL 3795 #define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 3796 #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 3797 #define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 3798 #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 3799 #define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 3800 #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 3801 #define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 3802 #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 3803 #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c 3804 #define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d 3805 #define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e 3806 #define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f 3807 //RSMU_SOFT_RST_CTRL 3808 #define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 3809 #define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 3810 #define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 3811 #define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 3812 #define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 3813 #define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 3814 #define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 3815 #define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 3816 #define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c 3817 #define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d 3818 #define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e 3819 #define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f 3820 //SELF_SOFT_RST 3821 #define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 3822 #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 3823 #define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 3824 #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 3825 #define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 3826 #define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 3827 #define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 3828 #define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 3829 #define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b 3830 #define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c 3831 #define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d 3832 #define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e 3833 #define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f 3834 //GFX_DRV_MODE1_RST_CTRL 3835 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 3836 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 3837 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 3838 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 3839 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 3840 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 3841 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 3842 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 3843 //BIF_RST_MISC_CTRL 3844 #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 3845 #define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 3846 #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 3847 #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 3848 #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 3849 #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 3850 #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 3851 #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa 3852 #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd 3853 #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf 3854 #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 3855 #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 3856 #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 3857 //BIF_RST_MISC_CTRL2 3858 #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 3859 #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 3860 #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 3861 #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f 3862 //BIF_RST_MISC_CTRL3 3863 #define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 3864 #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 3865 #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 3866 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 3867 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa 3868 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd 3869 //BIF_RST_GFXVF_FLR_IDLE 3870 #define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0 3871 #define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1 3872 #define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2 3873 #define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3 3874 #define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4 3875 #define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5 3876 #define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6 3877 #define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7 3878 #define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8 3879 #define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9 3880 #define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa 3881 #define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb 3882 #define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc 3883 #define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd 3884 #define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe 3885 #define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf 3886 #define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f 3887 //DEV0_PF0_FLR_RST_CTRL 3888 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3889 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3890 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3891 #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3892 #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3893 #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 3894 #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 3895 #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 3896 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 3897 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 3898 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa 3899 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb 3900 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc 3901 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd 3902 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe 3903 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf 3904 #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 3905 #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3906 #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3907 #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3908 #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3909 //DEV0_PF1_FLR_RST_CTRL 3910 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3911 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3912 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3913 #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3914 #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3915 #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3916 #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3917 #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3918 #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3919 //DEV0_PF2_FLR_RST_CTRL 3920 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3921 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3922 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3923 #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3924 #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3925 #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3926 #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3927 #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3928 #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3929 //DEV0_PF3_FLR_RST_CTRL 3930 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3931 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3932 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3933 #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3934 #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3935 #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3936 #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3937 #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3938 #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3939 //DEV0_PF4_FLR_RST_CTRL 3940 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3941 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3942 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3943 #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3944 #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3945 #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3946 #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3947 #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3948 #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3949 //DEV0_PF5_FLR_RST_CTRL 3950 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3951 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3952 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3953 #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3954 #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3955 #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3956 #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3957 #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3958 #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3959 //DEV0_PF6_FLR_RST_CTRL 3960 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3961 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3962 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3963 #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3964 #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3965 #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3966 #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3967 #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3968 #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3969 //DEV0_PF7_FLR_RST_CTRL 3970 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3971 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3972 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3973 #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3974 #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3975 #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3976 #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3977 #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3978 #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3979 //BIF_INST_RESET_INTR_STS 3980 #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 3981 #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 3982 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 3983 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 3984 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 3985 //BIF_PF_FLR_INTR_STS 3986 #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 3987 #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 3988 #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 3989 #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 3990 #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 3991 #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 3992 #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 3993 #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 3994 //BIF_D3HOTD0_INTR_STS 3995 #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 3996 #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 3997 #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 3998 #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 3999 #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 4000 #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 4001 #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 4002 #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 4003 //BIF_POWER_INTR_STS 4004 #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 4005 #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 4006 //BIF_PF_DSTATE_INTR_STS 4007 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 4008 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 4009 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 4010 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 4011 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 4012 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 4013 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 4014 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 4015 //BIF_PF0_VF_FLR_INTR_STS 4016 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0 4017 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1 4018 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2 4019 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3 4020 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4 4021 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5 4022 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6 4023 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7 4024 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8 4025 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9 4026 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa 4027 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb 4028 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc 4029 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd 4030 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe 4031 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf 4032 #define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f 4033 //BIF_INST_RESET_INTR_MASK 4034 #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 4035 #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 4036 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 4037 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 4038 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 4039 //BIF_PF_FLR_INTR_MASK 4040 #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 4041 #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 4042 #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 4043 #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 4044 #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 4045 #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 4046 #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 4047 #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 4048 //BIF_D3HOTD0_INTR_MASK 4049 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 4050 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 4051 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 4052 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 4053 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 4054 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 4055 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 4056 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 4057 //BIF_POWER_INTR_MASK 4058 #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 4059 #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 4060 //BIF_PF_DSTATE_INTR_MASK 4061 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 4062 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 4063 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 4064 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 4065 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 4066 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 4067 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 4068 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 4069 //BIF_PF0_VF_FLR_INTR_MASK 4070 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 4071 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 4072 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 4073 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 4074 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 4075 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 4076 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 4077 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 4078 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8 4079 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9 4080 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa 4081 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb 4082 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc 4083 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd 4084 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe 4085 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf 4086 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f 4087 //BIF_PF_FLR_RST 4088 #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 4089 #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 4090 #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 4091 #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 4092 #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 4093 #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 4094 #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 4095 #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 4096 //BIF_PF0_VF_FLR_RST 4097 #define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 4098 #define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 4099 #define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 4100 #define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 4101 #define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 4102 #define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 4103 #define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 4104 #define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 4105 #define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 4106 #define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 4107 #define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa 4108 #define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb 4109 #define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc 4110 #define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd 4111 #define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe 4112 #define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf 4113 #define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f 4114 //BIF_DEV0_PF0_DSTATE_VALUE 4115 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 4116 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4117 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 4118 //BIF_DEV0_PF1_DSTATE_VALUE 4119 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 4120 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4121 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 4122 //BIF_DEV0_PF2_DSTATE_VALUE 4123 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 4124 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4125 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 4126 //BIF_DEV0_PF3_DSTATE_VALUE 4127 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 4128 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4129 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 4130 //BIF_DEV0_PF4_DSTATE_VALUE 4131 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 4132 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4133 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 4134 //BIF_DEV0_PF5_DSTATE_VALUE 4135 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 4136 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4137 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 4138 //BIF_DEV0_PF6_DSTATE_VALUE 4139 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 4140 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4141 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 4142 //BIF_DEV0_PF7_DSTATE_VALUE 4143 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 4144 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4145 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 4146 //DEV0_PF0_D3HOTD0_RST_CTRL 4147 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4148 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4149 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4150 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4151 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4152 //DEV0_PF1_D3HOTD0_RST_CTRL 4153 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4154 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4155 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4156 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4157 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4158 //DEV0_PF2_D3HOTD0_RST_CTRL 4159 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4160 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4161 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4162 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4163 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4164 //DEV0_PF3_D3HOTD0_RST_CTRL 4165 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4166 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4167 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4168 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4169 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4170 //DEV0_PF4_D3HOTD0_RST_CTRL 4171 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4172 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4173 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4174 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4175 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4176 //DEV0_PF5_D3HOTD0_RST_CTRL 4177 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4178 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4179 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4180 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4181 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4182 //DEV0_PF6_D3HOTD0_RST_CTRL 4183 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4184 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4185 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4186 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4187 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4188 //DEV0_PF7_D3HOTD0_RST_CTRL 4189 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4190 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4191 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4192 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4193 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4194 //BIF_PORT0_DSTATE_VALUE 4195 #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 4196 #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 4197 4198 4199 // addressBlock: bif_misc_bif_misc_regblk 4200 //MISC_SCRATCH 4201 #define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 4202 //INTR_LINE_POLARITY 4203 #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 4204 //INTR_LINE_ENABLE 4205 #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 4206 //OUTSTANDING_VC_ALLOC 4207 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 4208 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 4209 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 4210 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 4211 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 4212 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa 4213 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc 4214 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe 4215 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 4216 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 4217 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a 4218 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c 4219 //BIFC_MISC_CTRL0 4220 #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 4221 #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 4222 #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 4223 #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 4224 #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa 4225 #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 4226 #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 4227 #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 4228 #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 4229 #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a 4230 #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b 4231 #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c 4232 #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f 4233 //BIFC_MISC_CTRL1 4234 #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 4235 #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 4236 #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 4237 #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 4238 #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 4239 #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 4240 #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 4241 #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 4242 #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 4243 #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa 4244 #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc 4245 #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd 4246 #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe 4247 #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf 4248 #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 4249 #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 4250 #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 4251 #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 4252 //BIFC_BME_ERR_LOG 4253 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 4254 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 4255 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 4256 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 4257 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 4258 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 4259 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 4260 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 4261 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 4262 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 4263 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 4264 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 4265 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 4266 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 4267 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 4268 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 4269 //BIFC_RCCBIH_BME_ERR_LOG 4270 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 4271 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 4272 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 4273 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 4274 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 4275 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 4276 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 4277 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 4278 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 4279 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 4280 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 4281 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 4282 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 4283 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 4284 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 4285 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 4286 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 4287 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 4288 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 4289 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 4290 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 4291 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa 4292 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc 4293 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 4294 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 4295 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 4296 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 4297 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a 4298 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c 4299 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 4300 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 4301 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 4302 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 4303 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 4304 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa 4305 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc 4306 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 4307 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 4308 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 4309 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 4310 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a 4311 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c 4312 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 4313 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 4314 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 4315 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 4316 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 4317 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa 4318 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc 4319 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 4320 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 4321 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 4322 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 4323 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a 4324 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c 4325 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 4326 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 4327 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 4328 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 4329 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 4330 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa 4331 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc 4332 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 4333 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 4334 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 4335 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 4336 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a 4337 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c 4338 //NBIF_VWIRE_CTRL 4339 #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 4340 #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 4341 #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 4342 #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a 4343 //NBIF_SMN_VWR_VCHG_DIS_CTRL 4344 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 4345 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 4346 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 4347 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 4348 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 4349 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 4350 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 4351 //NBIF_SMN_VWR_VCHG_RST_CTRL0 4352 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 4353 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 4354 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 4355 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 4356 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 4357 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 4358 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 4359 //NBIF_SMN_VWR_VCHG_TRIG 4360 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 4361 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 4362 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 4363 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 4364 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 4365 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 4366 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 4367 //NBIF_SMN_VWR_WTRIG_CNTL 4368 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 4369 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 4370 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 4371 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 4372 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 4373 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 4374 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 4375 //NBIF_SMN_VWR_VCHG_DIS_CTRL_1 4376 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 4377 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 4378 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 4379 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 4380 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 4381 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 4382 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 4383 //NBIF_MGCG_CTRL 4384 #define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0 4385 #define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1 4386 #define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2 4387 //NBIF_DS_CTRL_LCLK 4388 #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 4389 #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 4390 //SMN_MST_CNTL0 4391 #define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 4392 #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 4393 #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 4394 #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa 4395 #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb 4396 #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 4397 #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 4398 #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 4399 #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c 4400 //SMN_MST_EP_CNTL1 4401 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 4402 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 4403 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 4404 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 4405 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 4406 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 4407 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 4408 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 4409 //SMN_MST_EP_CNTL2 4410 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 4411 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 4412 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 4413 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 4414 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 4415 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 4416 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 4417 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 4418 //NBIF_SDP_VWR_VCHG_DIS_CTRL 4419 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 4420 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 4421 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 4422 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 4423 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 4424 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 4425 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 4426 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 4427 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 4428 //NBIF_SDP_VWR_VCHG_RST_CTRL0 4429 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 4430 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 4431 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 4432 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 4433 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 4434 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 4435 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 4436 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 4437 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 4438 //NBIF_SDP_VWR_VCHG_RST_CTRL1 4439 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 4440 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 4441 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 4442 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 4443 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 4444 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 4445 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 4446 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 4447 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 4448 //NBIF_SDP_VWR_VCHG_TRIG 4449 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 4450 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 4451 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 4452 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 4453 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 4454 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 4455 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 4456 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 4457 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 4458 //BME_DUMMY_CNTL_0 4459 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 4460 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 4461 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 4462 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 4463 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 4464 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa 4465 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc 4466 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe 4467 //BIFC_THT_CNTL 4468 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 4469 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 4470 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 4471 //BIFC_HSTARB_CNTL 4472 #define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 4473 //BIFC_GSI_CNTL 4474 #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 4475 #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 4476 #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 4477 #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 4478 #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 4479 #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 4480 #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 4481 #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa 4482 #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc 4483 //BIFC_PCIEFUNC_CNTL 4484 #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 4485 #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 4486 //BIFC_SDP_CNTL_0 4487 #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 4488 #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6 4489 #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc 4490 #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12 4491 //BIFC_PERF_CNTL_0 4492 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 4493 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 4494 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 4495 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 4496 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 4497 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 4498 //BIFC_PERF_CNTL_1 4499 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 4500 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 4501 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 4502 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 4503 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 4504 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 4505 //BIFC_PERF_CNT_MMIO_RD 4506 #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 4507 //BIFC_PERF_CNT_MMIO_WR 4508 #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 4509 //BIFC_PERF_CNT_DMA_RD 4510 #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 4511 //BIFC_PERF_CNT_DMA_WR 4512 #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 4513 //NBIF_REGIF_ERRSET_CTRL 4514 #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 4515 //SMN_MST_EP_CNTL3 4516 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 4517 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 4518 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 4519 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 4520 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 4521 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 4522 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 4523 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 4524 //SMN_MST_EP_CNTL4 4525 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 4526 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 4527 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 4528 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 4529 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 4530 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 4531 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 4532 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 4533 //BIF_SELFRING_BUFFER_VID 4534 #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 4535 #define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 4536 //BIF_SELFRING_VECTOR_CNTL 4537 #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 4538 4539 4540 // addressBlock: bif_ras_bif_ras_regblk 4541 //BIF_RAS_LEAF0_CTRL 4542 #define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 4543 #define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4544 #define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 4545 #define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 4546 #define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4547 #define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 4548 #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4549 #define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 4550 #define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 4551 #define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 4552 #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4553 #define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 4554 //BIF_RAS_LEAF1_CTRL 4555 #define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 4556 #define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4557 #define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 4558 #define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 4559 #define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4560 #define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 4561 #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4562 #define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 4563 #define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 4564 #define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 4565 #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4566 #define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 4567 //BIF_RAS_LEAF2_CTRL 4568 #define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 4569 #define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4570 #define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 4571 #define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 4572 #define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4573 #define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 4574 #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4575 #define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 4576 #define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 4577 #define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 4578 #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4579 #define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 4580 //BIF_RAS_MISC_CTRL 4581 #define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 4582 //BIF_IOHUB_RAS_IH_CNTL 4583 #define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 4584 //BIF_RAS_VWR_FROM_IOHUB 4585 #define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 4586 4587 4588 // addressBlock: rcc_pfc_amdgfx_RCCPFCDEC 4589 //RCC_PFC_LTR_CNTL 4590 #define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 4591 #define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa 4592 #define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf 4593 #define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 4594 #define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a 4595 #define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f 4596 //RCC_PFC_PME_RESTORE 4597 #define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 4598 #define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 4599 //RCC_PFC_STICKY_RESTORE_0 4600 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 4601 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 4602 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 4603 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 4604 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 4605 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 4606 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 4607 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 4608 //RCC_PFC_STICKY_RESTORE_1 4609 #define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 4610 //RCC_PFC_STICKY_RESTORE_2 4611 #define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 4612 //RCC_PFC_STICKY_RESTORE_3 4613 #define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 4614 //RCC_PFC_STICKY_RESTORE_4 4615 #define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 4616 //RCC_PFC_STICKY_RESTORE_5 4617 #define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 4618 //RCC_PFC_AUXPWR_CNTL 4619 #define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 4620 #define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 4621 4622 4623 // addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC 4624 //RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 4625 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 4626 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa 4627 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf 4628 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 4629 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a 4630 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f 4631 //RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 4632 #define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 4633 #define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 4634 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 4635 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 4636 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 4637 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 4638 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 4639 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 4640 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 4641 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 4642 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 4643 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 4644 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 4645 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 4646 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 4647 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 4648 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 4649 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 4650 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 4651 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 4652 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 4653 //RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 4654 #define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 4655 #define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 4656 4657 4658 // addressBlock: pciemsix_amdgfx_MSIXTDEC 4659 //PCIEMSIX_VECT0_ADDR_LO 4660 #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4661 //PCIEMSIX_VECT0_ADDR_HI 4662 #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4663 //PCIEMSIX_VECT0_MSG_DATA 4664 #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 4665 //PCIEMSIX_VECT0_CONTROL 4666 #define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 4667 //PCIEMSIX_VECT1_ADDR_LO 4668 #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4669 //PCIEMSIX_VECT1_ADDR_HI 4670 #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4671 //PCIEMSIX_VECT1_MSG_DATA 4672 #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 4673 //PCIEMSIX_VECT1_CONTROL 4674 #define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 4675 //PCIEMSIX_VECT2_ADDR_LO 4676 #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4677 //PCIEMSIX_VECT2_ADDR_HI 4678 #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4679 //PCIEMSIX_VECT2_MSG_DATA 4680 #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 4681 //PCIEMSIX_VECT2_CONTROL 4682 #define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 4683 //PCIEMSIX_VECT3_ADDR_LO 4684 #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4685 //PCIEMSIX_VECT3_ADDR_HI 4686 #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4687 //PCIEMSIX_VECT3_MSG_DATA 4688 #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 4689 //PCIEMSIX_VECT3_CONTROL 4690 #define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 4691 //PCIEMSIX_VECT4_ADDR_LO 4692 #define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4693 //PCIEMSIX_VECT4_ADDR_HI 4694 #define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4695 //PCIEMSIX_VECT4_MSG_DATA 4696 #define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 4697 //PCIEMSIX_VECT4_CONTROL 4698 #define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 4699 //PCIEMSIX_VECT5_ADDR_LO 4700 #define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4701 //PCIEMSIX_VECT5_ADDR_HI 4702 #define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4703 //PCIEMSIX_VECT5_MSG_DATA 4704 #define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 4705 //PCIEMSIX_VECT5_CONTROL 4706 #define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 4707 //PCIEMSIX_VECT6_ADDR_LO 4708 #define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4709 //PCIEMSIX_VECT6_ADDR_HI 4710 #define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4711 //PCIEMSIX_VECT6_MSG_DATA 4712 #define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 4713 //PCIEMSIX_VECT6_CONTROL 4714 #define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 4715 //PCIEMSIX_VECT7_ADDR_LO 4716 #define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4717 //PCIEMSIX_VECT7_ADDR_HI 4718 #define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4719 //PCIEMSIX_VECT7_MSG_DATA 4720 #define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 4721 //PCIEMSIX_VECT7_CONTROL 4722 #define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 4723 //PCIEMSIX_VECT8_ADDR_LO 4724 #define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4725 //PCIEMSIX_VECT8_ADDR_HI 4726 #define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4727 //PCIEMSIX_VECT8_MSG_DATA 4728 #define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 4729 //PCIEMSIX_VECT8_CONTROL 4730 #define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 4731 //PCIEMSIX_VECT9_ADDR_LO 4732 #define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4733 //PCIEMSIX_VECT9_ADDR_HI 4734 #define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4735 //PCIEMSIX_VECT9_MSG_DATA 4736 #define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 4737 //PCIEMSIX_VECT9_CONTROL 4738 #define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 4739 //PCIEMSIX_VECT10_ADDR_LO 4740 #define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4741 //PCIEMSIX_VECT10_ADDR_HI 4742 #define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4743 //PCIEMSIX_VECT10_MSG_DATA 4744 #define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 4745 //PCIEMSIX_VECT10_CONTROL 4746 #define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 4747 //PCIEMSIX_VECT11_ADDR_LO 4748 #define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4749 //PCIEMSIX_VECT11_ADDR_HI 4750 #define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4751 //PCIEMSIX_VECT11_MSG_DATA 4752 #define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 4753 //PCIEMSIX_VECT11_CONTROL 4754 #define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 4755 //PCIEMSIX_VECT12_ADDR_LO 4756 #define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4757 //PCIEMSIX_VECT12_ADDR_HI 4758 #define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4759 //PCIEMSIX_VECT12_MSG_DATA 4760 #define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 4761 //PCIEMSIX_VECT12_CONTROL 4762 #define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 4763 //PCIEMSIX_VECT13_ADDR_LO 4764 #define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4765 //PCIEMSIX_VECT13_ADDR_HI 4766 #define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4767 //PCIEMSIX_VECT13_MSG_DATA 4768 #define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 4769 //PCIEMSIX_VECT13_CONTROL 4770 #define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 4771 //PCIEMSIX_VECT14_ADDR_LO 4772 #define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4773 //PCIEMSIX_VECT14_ADDR_HI 4774 #define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4775 //PCIEMSIX_VECT14_MSG_DATA 4776 #define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 4777 //PCIEMSIX_VECT14_CONTROL 4778 #define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 4779 //PCIEMSIX_VECT15_ADDR_LO 4780 #define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4781 //PCIEMSIX_VECT15_ADDR_HI 4782 #define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4783 //PCIEMSIX_VECT15_MSG_DATA 4784 #define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 4785 //PCIEMSIX_VECT15_CONTROL 4786 #define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 4787 //PCIEMSIX_VECT16_ADDR_LO 4788 #define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4789 //PCIEMSIX_VECT16_ADDR_HI 4790 #define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4791 //PCIEMSIX_VECT16_MSG_DATA 4792 #define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 4793 //PCIEMSIX_VECT16_CONTROL 4794 #define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 4795 //PCIEMSIX_VECT17_ADDR_LO 4796 #define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4797 //PCIEMSIX_VECT17_ADDR_HI 4798 #define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4799 //PCIEMSIX_VECT17_MSG_DATA 4800 #define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 4801 //PCIEMSIX_VECT17_CONTROL 4802 #define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 4803 //PCIEMSIX_VECT18_ADDR_LO 4804 #define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4805 //PCIEMSIX_VECT18_ADDR_HI 4806 #define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4807 //PCIEMSIX_VECT18_MSG_DATA 4808 #define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 4809 //PCIEMSIX_VECT18_CONTROL 4810 #define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 4811 //PCIEMSIX_VECT19_ADDR_LO 4812 #define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4813 //PCIEMSIX_VECT19_ADDR_HI 4814 #define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4815 //PCIEMSIX_VECT19_MSG_DATA 4816 #define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 4817 //PCIEMSIX_VECT19_CONTROL 4818 #define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 4819 //PCIEMSIX_VECT20_ADDR_LO 4820 #define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4821 //PCIEMSIX_VECT20_ADDR_HI 4822 #define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4823 //PCIEMSIX_VECT20_MSG_DATA 4824 #define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 4825 //PCIEMSIX_VECT20_CONTROL 4826 #define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 4827 //PCIEMSIX_VECT21_ADDR_LO 4828 #define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4829 //PCIEMSIX_VECT21_ADDR_HI 4830 #define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4831 //PCIEMSIX_VECT21_MSG_DATA 4832 #define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 4833 //PCIEMSIX_VECT21_CONTROL 4834 #define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 4835 //PCIEMSIX_VECT22_ADDR_LO 4836 #define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4837 //PCIEMSIX_VECT22_ADDR_HI 4838 #define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4839 //PCIEMSIX_VECT22_MSG_DATA 4840 #define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 4841 //PCIEMSIX_VECT22_CONTROL 4842 #define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 4843 //PCIEMSIX_VECT23_ADDR_LO 4844 #define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4845 //PCIEMSIX_VECT23_ADDR_HI 4846 #define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4847 //PCIEMSIX_VECT23_MSG_DATA 4848 #define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 4849 //PCIEMSIX_VECT23_CONTROL 4850 #define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 4851 //PCIEMSIX_VECT24_ADDR_LO 4852 #define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4853 //PCIEMSIX_VECT24_ADDR_HI 4854 #define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4855 //PCIEMSIX_VECT24_MSG_DATA 4856 #define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 4857 //PCIEMSIX_VECT24_CONTROL 4858 #define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 4859 //PCIEMSIX_VECT25_ADDR_LO 4860 #define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4861 //PCIEMSIX_VECT25_ADDR_HI 4862 #define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4863 //PCIEMSIX_VECT25_MSG_DATA 4864 #define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 4865 //PCIEMSIX_VECT25_CONTROL 4866 #define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 4867 //PCIEMSIX_VECT26_ADDR_LO 4868 #define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4869 //PCIEMSIX_VECT26_ADDR_HI 4870 #define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4871 //PCIEMSIX_VECT26_MSG_DATA 4872 #define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 4873 //PCIEMSIX_VECT26_CONTROL 4874 #define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 4875 //PCIEMSIX_VECT27_ADDR_LO 4876 #define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4877 //PCIEMSIX_VECT27_ADDR_HI 4878 #define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4879 //PCIEMSIX_VECT27_MSG_DATA 4880 #define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 4881 //PCIEMSIX_VECT27_CONTROL 4882 #define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 4883 //PCIEMSIX_VECT28_ADDR_LO 4884 #define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4885 //PCIEMSIX_VECT28_ADDR_HI 4886 #define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4887 //PCIEMSIX_VECT28_MSG_DATA 4888 #define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 4889 //PCIEMSIX_VECT28_CONTROL 4890 #define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 4891 //PCIEMSIX_VECT29_ADDR_LO 4892 #define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4893 //PCIEMSIX_VECT29_ADDR_HI 4894 #define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4895 //PCIEMSIX_VECT29_MSG_DATA 4896 #define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 4897 //PCIEMSIX_VECT29_CONTROL 4898 #define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 4899 //PCIEMSIX_VECT30_ADDR_LO 4900 #define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4901 //PCIEMSIX_VECT30_ADDR_HI 4902 #define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4903 //PCIEMSIX_VECT30_MSG_DATA 4904 #define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 4905 //PCIEMSIX_VECT30_CONTROL 4906 #define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 4907 //PCIEMSIX_VECT31_ADDR_LO 4908 #define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4909 //PCIEMSIX_VECT31_ADDR_HI 4910 #define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4911 //PCIEMSIX_VECT31_MSG_DATA 4912 #define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 4913 //PCIEMSIX_VECT31_CONTROL 4914 #define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 4915 4916 4917 // addressBlock: pciemsix_amdgfx_MSIXPDEC 4918 //PCIEMSIX_PBA 4919 #define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 4920 4921 4922 // addressBlock: syshub_mmreg_ind_syshubind 4923 //SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 4924 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 4925 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 4926 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 4927 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 4928 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 4929 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 4930 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 4931 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 4932 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 4933 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 4934 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 4935 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 4936 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 4937 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 4938 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 4939 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 4940 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 4941 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f 4942 //SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 4943 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 4944 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 4945 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 4946 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 4947 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf 4948 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 4949 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 4950 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 4951 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 4952 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 4953 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf 4954 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 4955 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 4956 //SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 4957 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 4958 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 4959 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 4960 //SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 4961 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 4962 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 4963 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 4964 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 4965 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4966 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4967 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4968 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4969 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4970 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4971 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 4972 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4973 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4974 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4975 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4976 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4977 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4978 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 4979 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4980 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4981 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4982 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4983 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4984 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4985 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 4986 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4987 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4988 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4989 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4990 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4991 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4992 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 4993 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4994 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4995 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4996 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4997 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4998 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4999 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 5000 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5001 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5002 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5003 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5004 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5005 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5006 //SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 5007 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5008 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5009 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5010 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5011 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5012 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5013 //SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 5014 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5015 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5016 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5017 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5018 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5019 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5020 //SYSHUBMMREGIND_SYSHUB_CG_CNTL 5021 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 5022 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 5023 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 5024 //SYSHUBMMREGIND_SYSHUB_TRANS_IDLE 5025 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 5026 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 5027 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 5028 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 5029 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 5030 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 5031 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 5032 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 5033 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 5034 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 5035 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa 5036 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb 5037 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc 5038 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd 5039 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe 5040 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf 5041 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 5042 //SYSHUBMMREGIND_SYSHUB_HP_TIMER 5043 #define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 5044 //SYSHUBMMREGIND_SYSHUB_SCRATCH 5045 #define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 5046 //SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 5047 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 5048 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 5049 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 5050 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 5051 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 5052 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 5053 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 5054 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 5055 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 5056 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 5057 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 5058 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 5059 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 5060 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 5061 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 5062 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 5063 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 5064 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f 5065 //SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 5066 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 5067 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 5068 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf 5069 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 5070 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 5071 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf 5072 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 5073 //SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 5074 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 5075 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 5076 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 5077 //SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 5078 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 5079 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 5080 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 5081 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 5082 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5083 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5084 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5085 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5086 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5087 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5088 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 5089 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5090 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5091 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5092 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5093 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5094 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5095 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 5096 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5097 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5098 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5099 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5100 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5101 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5102 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 5103 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5104 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5105 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5106 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5107 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5108 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5109 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 5110 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5111 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5112 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5113 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5114 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5115 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5116 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 5117 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5118 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5119 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5120 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5121 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5122 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5123 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 5124 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5125 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5126 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5127 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5128 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5129 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5130 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 5131 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5132 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5133 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5134 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5135 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5136 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5137 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 5138 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5139 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5140 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5141 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5142 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5143 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5144 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 5145 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5146 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5147 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5148 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5149 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5150 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5151 //MASK 5152 5153 5154 // addressBlock: bif_cfg_dev0_epf0_bifcfgdecp 5155 //VENDOR_ID 5156 #define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL 5157 //DEVICE_ID 5158 #define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL 5159 //COMMAND 5160 #define COMMAND__IO_ACCESS_EN__MASK 0x0001L 5161 #define COMMAND__MEM_ACCESS_EN__MASK 0x0002L 5162 #define COMMAND__BUS_MASTER_EN__MASK 0x0004L 5163 #define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L 5164 #define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L 5165 #define COMMAND__PAL_SNOOP_EN__MASK 0x0020L 5166 #define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L 5167 #define COMMAND__AD_STEPPING__MASK 0x0080L 5168 #define COMMAND__SERR_EN__MASK 0x0100L 5169 #define COMMAND__FAST_B2B_EN__MASK 0x0200L 5170 #define COMMAND__INT_DIS__MASK 0x0400L 5171 //STATUS 5172 #define STATUS__INT_STATUS__MASK 0x0008L 5173 #define STATUS__CAP_LIST__MASK 0x0010L 5174 #define STATUS__PCI_66_EN__MASK 0x0020L 5175 #define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L 5176 #define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L 5177 #define STATUS__DEVSEL_TIMING__MASK 0x0600L 5178 #define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L 5179 #define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L 5180 #define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L 5181 #define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L 5182 #define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L 5183 //REVISION_ID 5184 #define REVISION_ID__MINOR_REV_ID__MASK 0x0FL 5185 #define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L 5186 //PROG_INTERFACE 5187 #define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL 5188 //SUB_CLASS 5189 #define SUB_CLASS__SUB_CLASS__MASK 0xFFL 5190 //BASE_CLASS 5191 #define BASE_CLASS__BASE_CLASS__MASK 0xFFL 5192 //CACHE_LINE 5193 #define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL 5194 //LATENCY 5195 #define LATENCY__LATENCY_TIMER__MASK 0xFFL 5196 //HEADER 5197 #define HEADER__HEADER_TYPE__MASK 0x7FL 5198 #define HEADER__DEVICE_TYPE__MASK 0x80L 5199 //BIST 5200 #define BIST__BIST_COMP__MASK 0x0FL 5201 #define BIST__BIST_STRT__MASK 0x40L 5202 #define BIST__BIST_CAP__MASK 0x80L 5203 //BASE_ADDR_1 5204 #define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL 5205 //BASE_ADDR_2 5206 #define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL 5207 //BASE_ADDR_3 5208 #define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL 5209 //BASE_ADDR_4 5210 #define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL 5211 //BASE_ADDR_5 5212 #define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL 5213 //BASE_ADDR_6 5214 #define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL 5215 //ADAPTER_ID 5216 #define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 5217 #define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L 5218 //ROM_BASE_ADDR 5219 #define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL 5220 //CAP_PTR 5221 #define CAP_PTR__CAP_PTR__MASK 0x000000FFL 5222 //INTERRUPT_LINE 5223 #define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL 5224 //INTERRUPT_PIN 5225 #define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL 5226 //MIN_GRANT 5227 #define MIN_GRANT__MIN_GNT__MASK 0xFFL 5228 //MAX_LATENCY 5229 #define MAX_LATENCY__MAX_LAT__MASK 0xFFL 5230 //VENDOR_CAP_LIST 5231 #define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL 5232 #define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L 5233 #define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L 5234 //ADAPTER_ID_W 5235 #define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 5236 #define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L 5237 //PMI_CAP_LIST 5238 #define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL 5239 #define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5240 //PMI_CAP 5241 #define PMI_CAP__VERSION__MASK 0x0007L 5242 #define PMI_CAP__PME_CLOCK__MASK 0x0008L 5243 #define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L 5244 #define PMI_CAP__AUX_CURRENT__MASK 0x01C0L 5245 #define PMI_CAP__D1_SUPPORT__MASK 0x0200L 5246 #define PMI_CAP__D2_SUPPORT__MASK 0x0400L 5247 #define PMI_CAP__PME_SUPPORT__MASK 0xF800L 5248 //PMI_STATUS_CNTL 5249 #define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L 5250 #define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L 5251 #define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L 5252 #define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L 5253 #define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L 5254 #define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L 5255 #define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L 5256 #define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L 5257 #define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L 5258 //PCIE_CAP_LIST 5259 #define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL 5260 #define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5261 //PCIE_CAP 5262 #define PCIE_CAP__VERSION__MASK 0x000FL 5263 #define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L 5264 #define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L 5265 #define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L 5266 //DEVICE_CAP 5267 #define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L 5268 #define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L 5269 #define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L 5270 #define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L 5271 #define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L 5272 #define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L 5273 #define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L 5274 #define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L 5275 #define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L 5276 //DEVICE_CNTL 5277 #define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L 5278 #define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L 5279 #define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L 5280 #define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L 5281 #define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L 5282 #define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L 5283 #define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L 5284 #define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L 5285 #define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L 5286 #define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L 5287 #define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L 5288 #define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L 5289 //DEVICE_STATUS 5290 #define DEVICE_STATUS__CORR_ERR__MASK 0x0001L 5291 #define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L 5292 #define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L 5293 #define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L 5294 #define DEVICE_STATUS__AUX_PWR__MASK 0x0010L 5295 #define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L 5296 //LINK_CAP 5297 #define LINK_CAP__LINK_SPEED__MASK 0x0000000FL 5298 #define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L 5299 #define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L 5300 #define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L 5301 #define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L 5302 #define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L 5303 #define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L 5304 #define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L 5305 #define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L 5306 #define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L 5307 #define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L 5308 //LINK_CNTL 5309 #define LINK_CNTL__PM_CONTROL__MASK 0x0003L 5310 #define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L 5311 #define LINK_CNTL__LINK_DIS__MASK 0x0010L 5312 #define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L 5313 #define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L 5314 #define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L 5315 #define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L 5316 #define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L 5317 #define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L 5318 #define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L 5319 //LINK_STATUS 5320 #define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL 5321 #define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L 5322 #define LINK_STATUS__LINK_TRAINING__MASK 0x0800L 5323 #define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L 5324 #define LINK_STATUS__DL_ACTIVE__MASK 0x2000L 5325 #define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L 5326 #define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L 5327 //DEVICE_CAP2 5328 #define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL 5329 #define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L 5330 #define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L 5331 #define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L 5332 #define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L 5333 #define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L 5334 #define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L 5335 #define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L 5336 #define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L 5337 #define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L 5338 #define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L 5339 #define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L 5340 #define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L 5341 #define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L 5342 //DEVICE_CNTL2 5343 #define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL 5344 #define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L 5345 #define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L 5346 #define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L 5347 #define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L 5348 #define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L 5349 #define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L 5350 #define DEVICE_CNTL2__LTR_EN__MASK 0x0400L 5351 #define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L 5352 #define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L 5353 //DEVICE_STATUS2 5354 #define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL 5355 //LINK_CAP2 5356 #define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL 5357 #define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L 5358 #define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L 5359 //LINK_CNTL2 5360 #define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL 5361 #define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L 5362 #define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L 5363 #define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L 5364 #define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L 5365 #define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L 5366 #define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L 5367 #define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L 5368 //LINK_STATUS2 5369 #define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L 5370 #define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L 5371 #define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L 5372 #define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L 5373 #define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L 5374 #define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L 5375 //SLOT_CAP2 5376 #define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL 5377 //SLOT_CNTL2 5378 #define SLOT_CNTL2__RESERVED__MASK 0xFFFFL 5379 //SLOT_STATUS2 5380 #define SLOT_STATUS2__RESERVED__MASK 0xFFFFL 5381 //MSI_CAP_LIST 5382 #define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL 5383 #define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5384 //MSI_MSG_CNTL 5385 #define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L 5386 #define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL 5387 #define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L 5388 #define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L 5389 #define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L 5390 //MSI_MSG_ADDR_LO 5391 #define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL 5392 //MSI_MSG_ADDR_HI 5393 #define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL 5394 //MSI_MSG_DATA 5395 #define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL 5396 //MSI_MSG_DATA_64 5397 #define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL 5398 //MSI_MASK 5399 #define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL 5400 //MSI_PENDING 5401 #define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL 5402 //MSI_MASK_64 5403 #define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL 5404 //MSI_PENDING_64 5405 #define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL 5406 //MSIX_CAP_LIST 5407 #define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL 5408 #define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5409 //MSIX_MSG_CNTL 5410 #define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL 5411 #define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L 5412 #define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L 5413 //MSIX_TABLE 5414 #define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L 5415 #define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L 5416 //MSIX_PBA 5417 #define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L 5418 #define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L 5419 //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 5420 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5421 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5422 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5423 //PCIE_VENDOR_SPECIFIC_HDR 5424 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL 5425 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L 5426 #define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L 5427 //PCIE_VENDOR_SPECIFIC1 5428 #define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL 5429 //PCIE_VENDOR_SPECIFIC2 5430 #define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL 5431 //PCIE_VC_ENH_CAP_LIST 5432 #define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5433 #define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5434 #define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5435 //PCIE_PORT_VC_CAP_REG1 5436 #define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L 5437 #define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L 5438 #define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L 5439 #define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L 5440 //PCIE_PORT_VC_CAP_REG2 5441 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL 5442 #define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L 5443 //PCIE_PORT_VC_CNTL 5444 #define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L 5445 #define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL 5446 //PCIE_PORT_VC_STATUS 5447 #define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L 5448 //PCIE_VC0_RESOURCE_CAP 5449 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL 5450 #define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L 5451 #define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L 5452 #define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L 5453 //PCIE_VC0_RESOURCE_CNTL 5454 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L 5455 #define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL 5456 #define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L 5457 #define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L 5458 #define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L 5459 #define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L 5460 //PCIE_VC0_RESOURCE_STATUS 5461 #define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L 5462 #define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L 5463 //PCIE_VC1_RESOURCE_CAP 5464 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL 5465 #define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L 5466 #define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L 5467 #define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L 5468 //PCIE_VC1_RESOURCE_CNTL 5469 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L 5470 #define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL 5471 #define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L 5472 #define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L 5473 #define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L 5474 #define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L 5475 //PCIE_VC1_RESOURCE_STATUS 5476 #define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L 5477 #define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L 5478 //PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 5479 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5480 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5481 #define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5482 //PCIE_DEV_SERIAL_NUM_DW1 5483 #define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL 5484 //PCIE_DEV_SERIAL_NUM_DW2 5485 #define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL 5486 //PCIE_ADV_ERR_RPT_ENH_CAP_LIST 5487 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5488 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5489 #define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5490 //PCIE_UNCORR_ERR_STATUS 5491 #define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L 5492 #define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L 5493 #define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L 5494 #define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L 5495 #define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L 5496 #define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L 5497 #define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L 5498 #define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L 5499 #define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L 5500 #define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L 5501 #define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L 5502 #define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L 5503 #define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L 5504 #define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L 5505 #define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L 5506 #define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L 5507 //PCIE_UNCORR_ERR_MASK 5508 #define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L 5509 #define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L 5510 #define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L 5511 #define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L 5512 #define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L 5513 #define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L 5514 #define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L 5515 #define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L 5516 #define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L 5517 #define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L 5518 #define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L 5519 #define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L 5520 #define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L 5521 #define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L 5522 #define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L 5523 #define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L 5524 //PCIE_UNCORR_ERR_SEVERITY 5525 #define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L 5526 #define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L 5527 #define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L 5528 #define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L 5529 #define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L 5530 #define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L 5531 #define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L 5532 #define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L 5533 #define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L 5534 #define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L 5535 #define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L 5536 #define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L 5537 #define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L 5538 #define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L 5539 #define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L 5540 #define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L 5541 //PCIE_CORR_ERR_STATUS 5542 #define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L 5543 #define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L 5544 #define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L 5545 #define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L 5546 #define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L 5547 #define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L 5548 #define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L 5549 #define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L 5550 //PCIE_CORR_ERR_MASK 5551 #define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L 5552 #define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L 5553 #define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L 5554 #define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L 5555 #define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L 5556 #define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L 5557 #define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L 5558 #define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L 5559 //PCIE_ADV_ERR_CAP_CNTL 5560 #define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL 5561 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L 5562 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L 5563 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L 5564 #define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L 5565 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L 5566 #define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L 5567 #define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L 5568 //PCIE_HDR_LOG0 5569 #define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL 5570 //PCIE_HDR_LOG1 5571 #define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL 5572 //PCIE_HDR_LOG2 5573 #define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL 5574 //PCIE_HDR_LOG3 5575 #define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL 5576 //PCIE_ROOT_ERR_CMD 5577 #define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L 5578 #define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L 5579 #define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L 5580 //PCIE_ROOT_ERR_STATUS 5581 #define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L 5582 #define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L 5583 #define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L 5584 #define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L 5585 #define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L 5586 #define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L 5587 #define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L 5588 #define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L 5589 //PCIE_ERR_SRC_ID 5590 #define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL 5591 #define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L 5592 //PCIE_TLP_PREFIX_LOG0 5593 #define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL 5594 //PCIE_TLP_PREFIX_LOG1 5595 #define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL 5596 //PCIE_TLP_PREFIX_LOG2 5597 #define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL 5598 //PCIE_TLP_PREFIX_LOG3 5599 #define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL 5600 //PCIE_BAR_ENH_CAP_LIST 5601 #define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5602 #define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5603 #define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5604 //PCIE_BAR1_CAP 5605 #define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5606 //PCIE_BAR1_CNTL 5607 #define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L 5608 #define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5609 #define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L 5610 //PCIE_BAR2_CAP 5611 #define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5612 //PCIE_BAR2_CNTL 5613 #define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L 5614 #define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5615 #define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L 5616 //PCIE_BAR3_CAP 5617 #define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5618 //PCIE_BAR3_CNTL 5619 #define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L 5620 #define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5621 #define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L 5622 //PCIE_BAR4_CAP 5623 #define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5624 //PCIE_BAR4_CNTL 5625 #define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L 5626 #define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5627 #define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L 5628 //PCIE_BAR5_CAP 5629 #define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5630 //PCIE_BAR5_CNTL 5631 #define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L 5632 #define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5633 #define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L 5634 //PCIE_BAR6_CAP 5635 #define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5636 //PCIE_BAR6_CNTL 5637 #define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L 5638 #define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5639 #define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L 5640 //PCIE_PWR_BUDGET_ENH_CAP_LIST 5641 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5642 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5643 #define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5644 //PCIE_PWR_BUDGET_DATA_SELECT 5645 #define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL 5646 //PCIE_PWR_BUDGET_DATA 5647 #define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL 5648 #define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L 5649 #define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L 5650 #define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L 5651 #define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L 5652 #define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L 5653 //PCIE_PWR_BUDGET_CAP 5654 #define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L 5655 //PCIE_DPA_ENH_CAP_LIST 5656 #define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5657 #define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5658 #define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5659 //PCIE_DPA_CAP 5660 #define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL 5661 #define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L 5662 #define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L 5663 #define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L 5664 #define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L 5665 //PCIE_DPA_LATENCY_INDICATOR 5666 #define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL 5667 //PCIE_DPA_STATUS 5668 #define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL 5669 #define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L 5670 //PCIE_DPA_CNTL 5671 #define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL 5672 //PCIE_DPA_SUBSTATE_PWR_ALLOC_0 5673 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5674 //PCIE_DPA_SUBSTATE_PWR_ALLOC_1 5675 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5676 //PCIE_DPA_SUBSTATE_PWR_ALLOC_2 5677 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5678 //PCIE_DPA_SUBSTATE_PWR_ALLOC_3 5679 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5680 //PCIE_DPA_SUBSTATE_PWR_ALLOC_4 5681 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5682 //PCIE_DPA_SUBSTATE_PWR_ALLOC_5 5683 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5684 //PCIE_DPA_SUBSTATE_PWR_ALLOC_6 5685 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5686 //PCIE_DPA_SUBSTATE_PWR_ALLOC_7 5687 #define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5688 //PCIE_SECONDARY_ENH_CAP_LIST 5689 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5690 #define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5691 #define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5692 //PCIE_LINK_CNTL3 5693 #define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L 5694 #define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L 5695 #define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL 5696 //PCIE_LANE_ERROR_STATUS 5697 #define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL 5698 #define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L 5699 //PCIE_LANE_0_EQUALIZATION_CNTL 5700 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5701 #define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5702 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5703 #define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5704 #define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5705 //PCIE_LANE_1_EQUALIZATION_CNTL 5706 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5707 #define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5708 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5709 #define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5710 #define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5711 //PCIE_LANE_2_EQUALIZATION_CNTL 5712 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5713 #define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5714 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5715 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5716 #define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5717 //PCIE_LANE_3_EQUALIZATION_CNTL 5718 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5719 #define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5720 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5721 #define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5722 #define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5723 //PCIE_LANE_4_EQUALIZATION_CNTL 5724 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5725 #define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5726 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5727 #define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5728 #define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5729 //PCIE_LANE_5_EQUALIZATION_CNTL 5730 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5731 #define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5732 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5733 #define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5734 #define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5735 //PCIE_LANE_6_EQUALIZATION_CNTL 5736 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5737 #define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5738 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5739 #define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5740 #define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5741 //PCIE_LANE_7_EQUALIZATION_CNTL 5742 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5743 #define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5744 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5745 #define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5746 #define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5747 //PCIE_LANE_8_EQUALIZATION_CNTL 5748 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5749 #define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5750 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5751 #define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5752 #define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5753 //PCIE_LANE_9_EQUALIZATION_CNTL 5754 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5755 #define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5756 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5757 #define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5758 #define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5759 //PCIE_LANE_10_EQUALIZATION_CNTL 5760 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5761 #define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5762 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5763 #define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5764 #define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5765 //PCIE_LANE_11_EQUALIZATION_CNTL 5766 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5767 #define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5768 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5769 #define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5770 #define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5771 //PCIE_LANE_12_EQUALIZATION_CNTL 5772 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5773 #define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5774 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5775 #define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5776 #define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5777 //PCIE_LANE_13_EQUALIZATION_CNTL 5778 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5779 #define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5780 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5781 #define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5782 #define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5783 //PCIE_LANE_14_EQUALIZATION_CNTL 5784 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5785 #define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5786 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5787 #define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5788 #define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5789 //PCIE_LANE_15_EQUALIZATION_CNTL 5790 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5791 #define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5792 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5793 #define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5794 #define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5795 //PCIE_ACS_ENH_CAP_LIST 5796 #define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5797 #define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5798 #define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5799 //PCIE_ACS_CAP 5800 #define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L 5801 #define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L 5802 #define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L 5803 #define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L 5804 #define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L 5805 #define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L 5806 #define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L 5807 #define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L 5808 //PCIE_ACS_CNTL 5809 #define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L 5810 #define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L 5811 #define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L 5812 #define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L 5813 #define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L 5814 #define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L 5815 #define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L 5816 //PCIE_ATS_ENH_CAP_LIST 5817 #define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5818 #define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5819 #define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5820 //PCIE_ATS_CAP 5821 #define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL 5822 #define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L 5823 #define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L 5824 //PCIE_ATS_CNTL 5825 #define PCIE_ATS_CNTL__STU__MASK 0x001FL 5826 #define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L 5827 //PCIE_PAGE_REQ_ENH_CAP_LIST 5828 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5829 #define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5830 #define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5831 //PCIE_PAGE_REQ_CNTL 5832 #define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L 5833 #define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L 5834 //PCIE_PAGE_REQ_STATUS 5835 #define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L 5836 #define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L 5837 #define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L 5838 #define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L 5839 //PCIE_OUTSTAND_PAGE_REQ_CAPACITY 5840 #define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL 5841 //PCIE_OUTSTAND_PAGE_REQ_ALLOC 5842 #define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL 5843 //PCIE_PASID_ENH_CAP_LIST 5844 #define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5845 #define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5846 #define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5847 //PCIE_PASID_CAP 5848 #define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L 5849 #define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L 5850 #define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L 5851 //PCIE_PASID_CNTL 5852 #define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L 5853 #define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L 5854 #define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L 5855 //PCIE_TPH_REQR_ENH_CAP_LIST 5856 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5857 #define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5858 #define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5859 //PCIE_TPH_REQR_CAP 5860 #define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L 5861 #define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L 5862 #define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L 5863 #define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L 5864 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L 5865 #define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L 5866 //PCIE_TPH_REQR_CNTL 5867 #define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L 5868 #define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L 5869 //PCIE_MC_ENH_CAP_LIST 5870 #define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5871 #define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5872 #define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5873 //PCIE_MC_CAP 5874 #define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL 5875 #define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L 5876 #define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L 5877 //PCIE_MC_CNTL 5878 #define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL 5879 #define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L 5880 //PCIE_MC_ADDR0 5881 #define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL 5882 #define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L 5883 //PCIE_MC_ADDR1 5884 #define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL 5885 //PCIE_MC_RCV0 5886 #define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL 5887 //PCIE_MC_RCV1 5888 #define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL 5889 //PCIE_MC_BLOCK_ALL0 5890 #define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL 5891 //PCIE_MC_BLOCK_ALL1 5892 #define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL 5893 //PCIE_MC_BLOCK_UNTRANSLATED_0 5894 #define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL 5895 //PCIE_MC_BLOCK_UNTRANSLATED_1 5896 #define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL 5897 //PCIE_LTR_ENH_CAP_LIST 5898 #define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5899 #define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5900 #define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5901 //PCIE_LTR_CAP 5902 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL 5903 #define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L 5904 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L 5905 #define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L 5906 //PCIE_ARI_ENH_CAP_LIST 5907 #define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5908 #define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5909 #define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5910 //PCIE_ARI_CAP 5911 #define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L 5912 #define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L 5913 #define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L 5914 //PCIE_ARI_CNTL 5915 #define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L 5916 #define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L 5917 #define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L 5918 //PCIE_SRIOV_ENH_CAP_LIST 5919 #define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5920 #define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5921 #define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5922 //PCIE_SRIOV_CAP 5923 #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L 5924 #define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L 5925 #define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L 5926 //PCIE_SRIOV_CONTROL 5927 #define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L 5928 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L 5929 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L 5930 #define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L 5931 #define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L 5932 //PCIE_SRIOV_STATUS 5933 #define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L 5934 //PCIE_SRIOV_INITIAL_VFS 5935 #define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL 5936 //PCIE_SRIOV_TOTAL_VFS 5937 #define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL 5938 //PCIE_SRIOV_NUM_VFS 5939 #define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL 5940 //PCIE_SRIOV_FUNC_DEP_LINK 5941 #define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL 5942 //PCIE_SRIOV_FIRST_VF_OFFSET 5943 #define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL 5944 //PCIE_SRIOV_VF_STRIDE 5945 #define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL 5946 //PCIE_SRIOV_VF_DEVICE_ID 5947 #define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL 5948 //PCIE_SRIOV_SUPPORTED_PAGE_SIZE 5949 #define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL 5950 //PCIE_SRIOV_SYSTEM_PAGE_SIZE 5951 #define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL 5952 //PCIE_SRIOV_VF_BASE_ADDR_0 5953 #define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5954 //PCIE_SRIOV_VF_BASE_ADDR_1 5955 #define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5956 //PCIE_SRIOV_VF_BASE_ADDR_2 5957 #define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5958 //PCIE_SRIOV_VF_BASE_ADDR_3 5959 #define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5960 //PCIE_SRIOV_VF_BASE_ADDR_4 5961 #define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5962 //PCIE_SRIOV_VF_BASE_ADDR_5 5963 #define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5964 //PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 5965 #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L 5966 #define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L 5967 //PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 5968 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL 5969 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L 5970 #define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L 5971 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 5972 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL 5973 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L 5974 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L 5975 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 5976 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L 5977 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L 5978 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 5979 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L 5980 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L 5981 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L 5982 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L 5983 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L 5984 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L 5985 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L 5986 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L 5987 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L 5988 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L 5989 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L 5990 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L 5991 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L 5992 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L 5993 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 5994 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L 5995 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L 5996 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L 5997 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L 5998 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L 5999 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L 6000 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L 6001 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L 6002 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L 6003 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L 6004 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L 6005 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L 6006 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L 6007 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L 6008 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 6009 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L 6010 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 6011 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL 6012 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L 6013 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L 6014 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L 6015 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L 6016 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 6017 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L 6018 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L 6019 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L 6020 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L 6021 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L 6022 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L 6023 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L 6024 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L 6025 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L 6026 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L 6027 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L 6028 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L 6029 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L 6030 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L 6031 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L 6032 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L 6033 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L 6034 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L 6035 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L 6036 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L 6037 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L 6038 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L 6039 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L 6040 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L 6041 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L 6042 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L 6043 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L 6044 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L 6045 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L 6046 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L 6047 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L 6048 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L 6049 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 6050 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L 6051 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L 6052 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 6053 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL 6054 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L 6055 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L 6056 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 6057 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL 6058 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L 6059 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 6060 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL 6061 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L 6062 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L 6063 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 6064 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL 6065 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L 6066 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 6067 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL 6068 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L 6069 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 6070 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL 6071 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L 6072 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 6073 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL 6074 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L 6075 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 6076 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL 6077 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L 6078 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 6079 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL 6080 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L 6081 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 6082 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL 6083 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L 6084 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 6085 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL 6086 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L 6087 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 6088 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL 6089 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L 6090 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 6091 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL 6092 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L 6093 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 6094 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL 6095 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L 6096 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 6097 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL 6098 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L 6099 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 6100 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL 6101 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L 6102 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 6103 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL 6104 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L 6105 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 6106 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL 6107 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L 6108 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 6109 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL 6110 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L 6111 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 6112 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL 6113 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 6114 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL 6115 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 6116 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL 6117 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 6118 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL 6119 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 6120 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL 6121 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 6122 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL 6123 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 6124 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL 6125 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 6126 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL 6127 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 6128 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL 6129 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 6130 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL 6131 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 6132 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL 6133 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 6134 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL 6135 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 6136 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL 6137 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 6138 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL 6139 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 6140 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL 6141 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 6142 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL 6143 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 6144 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL 6145 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 6146 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL 6147 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 6148 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL 6149 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 6150 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL 6151 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 6152 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL 6153 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 6154 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL 6155 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 6156 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL 6157 //PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 6158 #define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL 6159 6160 6161 // addressBlock: bif_cfg_dev0_swds_bifcfgdecp 6162 //SUB_BUS_NUMBER_LATENCY 6163 #define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL 6164 #define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L 6165 #define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L 6166 #define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L 6167 //IO_BASE_LIMIT 6168 #define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL 6169 #define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L 6170 #define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L 6171 #define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L 6172 //SECONDARY_STATUS 6173 #define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L 6174 #define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L 6175 #define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L 6176 #define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L 6177 #define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L 6178 #define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L 6179 #define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L 6180 #define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L 6181 #define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L 6182 #define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L 6183 //MEM_BASE_LIMIT 6184 #define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL 6185 #define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L 6186 #define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L 6187 #define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L 6188 //PREF_BASE_LIMIT 6189 #define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL 6190 #define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L 6191 #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L 6192 #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L 6193 //PREF_BASE_UPPER 6194 #define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL 6195 //PREF_LIMIT_UPPER 6196 #define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL 6197 //IO_BASE_LIMIT_HI 6198 #define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL 6199 #define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L 6200 //IRQ_BRIDGE_CNTL 6201 #define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L 6202 #define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L 6203 #define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L 6204 #define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L 6205 #define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L 6206 #define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L 6207 #define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L 6208 #define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L 6209 //SLOT_CAP 6210 #define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L 6211 #define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L 6212 #define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L 6213 #define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L 6214 #define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L 6215 #define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L 6216 #define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L 6217 #define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L 6218 #define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L 6219 #define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L 6220 #define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L 6221 #define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L 6222 //SLOT_CNTL 6223 #define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L 6224 #define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L 6225 #define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L 6226 #define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L 6227 #define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L 6228 #define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L 6229 #define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L 6230 #define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L 6231 #define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L 6232 #define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L 6233 #define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L 6234 //SLOT_STATUS 6235 #define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L 6236 #define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L 6237 #define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L 6238 #define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L 6239 #define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L 6240 #define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L 6241 #define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L 6242 #define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L 6243 #define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L 6244 //SSID_CAP_LIST 6245 #define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL 6246 #define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L 6247 //SSID_CAP 6248 #define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 6249 #define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L 6250 6251 6252 // addressBlock: rcc_shadow_reg_shadowdec 6253 //SHADOW_COMMAND 6254 #define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L 6255 #define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L 6256 //SHADOW_BASE_ADDR_1 6257 #define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL 6258 //SHADOW_BASE_ADDR_2 6259 #define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL 6260 //SHADOW_SUB_BUS_NUMBER_LATENCY 6261 #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L 6262 #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L 6263 //SHADOW_IO_BASE_LIMIT 6264 #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L 6265 #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L 6266 //SHADOW_MEM_BASE_LIMIT 6267 #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL 6268 #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L 6269 #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L 6270 #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L 6271 //SHADOW_PREF_BASE_LIMIT 6272 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL 6273 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L 6274 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L 6275 #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L 6276 //SHADOW_PREF_BASE_UPPER 6277 #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL 6278 //SHADOW_PREF_LIMIT_UPPER 6279 #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL 6280 //SHADOW_IO_BASE_LIMIT_HI 6281 #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL 6282 #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L 6283 //SHADOW_IRQ_BRIDGE_CNTL 6284 #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L 6285 #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L 6286 #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L 6287 #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L 6288 //SUC_INDEX 6289 #define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL 6290 //SUC_DATA 6291 #define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL 6292 6293 6294 // addressBlock: bif_bx_pf_SUMDEC 6295 //SUM_INDEX 6296 #define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL 6297 //SUM_DATA 6298 #define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL 6299 6300 6301 // addressBlock: gdc_GDCDEC 6302 //A2S_CNTL_CL0 6303 #define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L 6304 #define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6305 #define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6306 #define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6307 #define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6308 #define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L 6309 #define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L 6310 #define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L 6311 #define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L 6312 #define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L 6313 #define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L 6314 //A2S_CNTL_CL1 6315 #define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L 6316 #define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6317 #define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6318 #define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6319 #define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6320 #define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L 6321 #define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L 6322 #define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L 6323 #define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L 6324 #define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L 6325 #define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L 6326 //A2S_CNTL_CL2 6327 #define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L 6328 #define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6329 #define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6330 #define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6331 #define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6332 #define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L 6333 #define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L 6334 #define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L 6335 #define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L 6336 #define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L 6337 #define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L 6338 //A2S_CNTL_CL3 6339 #define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L 6340 #define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6341 #define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6342 #define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6343 #define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6344 #define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L 6345 #define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L 6346 #define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L 6347 #define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L 6348 #define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L 6349 #define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L 6350 //A2S_CNTL_CL4 6351 #define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L 6352 #define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6353 #define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6354 #define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6355 #define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6356 #define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L 6357 #define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L 6358 #define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L 6359 #define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L 6360 #define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L 6361 #define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L 6362 //A2S_CNTL_SW0 6363 #define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L 6364 #define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L 6365 #define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6366 #define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L 6367 #define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L 6368 #define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6369 #define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6370 #define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6371 #define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6372 #define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L 6373 #define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L 6374 //A2S_CNTL_SW1 6375 #define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L 6376 #define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L 6377 #define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6378 #define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L 6379 #define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L 6380 #define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6381 #define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6382 #define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6383 #define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6384 #define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L 6385 #define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L 6386 //A2S_CNTL_SW2 6387 #define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L 6388 #define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L 6389 #define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6390 #define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L 6391 #define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L 6392 #define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6393 #define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6394 #define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6395 #define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6396 #define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L 6397 #define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L 6398 //NGDC_MGCG_CTRL 6399 #define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L 6400 #define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L 6401 #define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL 6402 //A2S_MISC_CNTL 6403 #define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L 6404 #define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L 6405 //NGDC_SDP_PORT_CTRL 6406 #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL 6407 //NGDC_RESERVED_0 6408 #define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL 6409 //NGDC_RESERVED_1 6410 #define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL 6411 //BIF_SDMA0_DOORBELL_RANGE 6412 #define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6413 #define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6414 //BIF_SDMA1_DOORBELL_RANGE 6415 #define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6416 #define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6417 //BIF_IH_DOORBELL_RANGE 6418 #define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6419 #define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6420 //BIF_MMSCH0_DOORBELL_RANGE 6421 #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6422 #define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6423 //BIF_DOORBELL_FENCE_CNTL 6424 #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L 6425 //S2A_MISC_CNTL 6426 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L 6427 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L 6428 #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L 6429 //A2S_CNTL2_SEC_CL0 6430 #define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L 6431 //A2S_CNTL2_SEC_CL1 6432 #define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L 6433 //A2S_CNTL2_SEC_CL2 6434 #define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L 6435 //A2S_CNTL2_SEC_CL3 6436 #define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L 6437 //A2S_CNTL2_SEC_CL4 6438 #define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L 6439 6440 6441 // addressBlock: nbif_sion_SIONDEC 6442 //SION_CL0_RdRsp_BurstTarget_REG0 6443 #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6444 //SION_CL0_RdRsp_BurstTarget_REG1 6445 #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6446 //SION_CL0_RdRsp_TimeSlot_REG0 6447 #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6448 //SION_CL0_RdRsp_TimeSlot_REG1 6449 #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6450 //SION_CL0_WrRsp_BurstTarget_REG0 6451 #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6452 //SION_CL0_WrRsp_BurstTarget_REG1 6453 #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6454 //SION_CL0_WrRsp_TimeSlot_REG0 6455 #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6456 //SION_CL0_WrRsp_TimeSlot_REG1 6457 #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6458 //SION_CL0_Req_BurstTarget_REG0 6459 #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6460 //SION_CL0_Req_BurstTarget_REG1 6461 #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6462 //SION_CL0_Req_TimeSlot_REG0 6463 #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6464 //SION_CL0_Req_TimeSlot_REG1 6465 #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6466 //SION_CL0_ReqPoolCredit_Alloc_REG0 6467 #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6468 //SION_CL0_ReqPoolCredit_Alloc_REG1 6469 #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6470 //SION_CL0_DataPoolCredit_Alloc_REG0 6471 #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6472 //SION_CL0_DataPoolCredit_Alloc_REG1 6473 #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6474 //SION_CL0_RdRspPoolCredit_Alloc_REG0 6475 #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6476 //SION_CL0_RdRspPoolCredit_Alloc_REG1 6477 #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6478 //SION_CL0_WrRspPoolCredit_Alloc_REG0 6479 #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6480 //SION_CL0_WrRspPoolCredit_Alloc_REG1 6481 #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6482 //SION_CL1_RdRsp_BurstTarget_REG0 6483 #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6484 //SION_CL1_RdRsp_BurstTarget_REG1 6485 #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6486 //SION_CL1_RdRsp_TimeSlot_REG0 6487 #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6488 //SION_CL1_RdRsp_TimeSlot_REG1 6489 #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6490 //SION_CL1_WrRsp_BurstTarget_REG0 6491 #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6492 //SION_CL1_WrRsp_BurstTarget_REG1 6493 #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6494 //SION_CL1_WrRsp_TimeSlot_REG0 6495 #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6496 //SION_CL1_WrRsp_TimeSlot_REG1 6497 #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6498 //SION_CL1_Req_BurstTarget_REG0 6499 #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6500 //SION_CL1_Req_BurstTarget_REG1 6501 #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6502 //SION_CL1_Req_TimeSlot_REG0 6503 #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6504 //SION_CL1_Req_TimeSlot_REG1 6505 #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6506 //SION_CL1_ReqPoolCredit_Alloc_REG0 6507 #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6508 //SION_CL1_ReqPoolCredit_Alloc_REG1 6509 #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6510 //SION_CL1_DataPoolCredit_Alloc_REG0 6511 #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6512 //SION_CL1_DataPoolCredit_Alloc_REG1 6513 #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6514 //SION_CL1_RdRspPoolCredit_Alloc_REG0 6515 #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6516 //SION_CL1_RdRspPoolCredit_Alloc_REG1 6517 #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6518 //SION_CL1_WrRspPoolCredit_Alloc_REG0 6519 #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6520 //SION_CL1_WrRspPoolCredit_Alloc_REG1 6521 #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6522 //SION_CL2_RdRsp_BurstTarget_REG0 6523 #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6524 //SION_CL2_RdRsp_BurstTarget_REG1 6525 #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6526 //SION_CL2_RdRsp_TimeSlot_REG0 6527 #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6528 //SION_CL2_RdRsp_TimeSlot_REG1 6529 #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6530 //SION_CL2_WrRsp_BurstTarget_REG0 6531 #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6532 //SION_CL2_WrRsp_BurstTarget_REG1 6533 #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6534 //SION_CL2_WrRsp_TimeSlot_REG0 6535 #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6536 //SION_CL2_WrRsp_TimeSlot_REG1 6537 #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6538 //SION_CL2_Req_BurstTarget_REG0 6539 #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6540 //SION_CL2_Req_BurstTarget_REG1 6541 #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6542 //SION_CL2_Req_TimeSlot_REG0 6543 #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6544 //SION_CL2_Req_TimeSlot_REG1 6545 #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6546 //SION_CL2_ReqPoolCredit_Alloc_REG0 6547 #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6548 //SION_CL2_ReqPoolCredit_Alloc_REG1 6549 #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6550 //SION_CL2_DataPoolCredit_Alloc_REG0 6551 #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6552 //SION_CL2_DataPoolCredit_Alloc_REG1 6553 #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6554 //SION_CL2_RdRspPoolCredit_Alloc_REG0 6555 #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6556 //SION_CL2_RdRspPoolCredit_Alloc_REG1 6557 #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6558 //SION_CL2_WrRspPoolCredit_Alloc_REG0 6559 #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6560 //SION_CL2_WrRspPoolCredit_Alloc_REG1 6561 #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6562 //SION_CL3_RdRsp_BurstTarget_REG0 6563 #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6564 //SION_CL3_RdRsp_BurstTarget_REG1 6565 #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6566 //SION_CL3_RdRsp_TimeSlot_REG0 6567 #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6568 //SION_CL3_RdRsp_TimeSlot_REG1 6569 #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6570 //SION_CL3_WrRsp_BurstTarget_REG0 6571 #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6572 //SION_CL3_WrRsp_BurstTarget_REG1 6573 #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6574 //SION_CL3_WrRsp_TimeSlot_REG0 6575 #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6576 //SION_CL3_WrRsp_TimeSlot_REG1 6577 #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6578 //SION_CL3_Req_BurstTarget_REG0 6579 #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6580 //SION_CL3_Req_BurstTarget_REG1 6581 #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6582 //SION_CL3_Req_TimeSlot_REG0 6583 #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6584 //SION_CL3_Req_TimeSlot_REG1 6585 #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6586 //SION_CL3_ReqPoolCredit_Alloc_REG0 6587 #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6588 //SION_CL3_ReqPoolCredit_Alloc_REG1 6589 #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6590 //SION_CL3_DataPoolCredit_Alloc_REG0 6591 #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6592 //SION_CL3_DataPoolCredit_Alloc_REG1 6593 #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6594 //SION_CL3_RdRspPoolCredit_Alloc_REG0 6595 #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6596 //SION_CL3_RdRspPoolCredit_Alloc_REG1 6597 #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6598 //SION_CL3_WrRspPoolCredit_Alloc_REG0 6599 #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6600 //SION_CL3_WrRspPoolCredit_Alloc_REG1 6601 #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6602 //SION_CL4_RdRsp_BurstTarget_REG0 6603 #define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6604 //SION_CL4_RdRsp_BurstTarget_REG1 6605 #define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6606 //SION_CL4_RdRsp_TimeSlot_REG0 6607 #define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6608 //SION_CL4_RdRsp_TimeSlot_REG1 6609 #define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6610 //SION_CL4_WrRsp_BurstTarget_REG0 6611 #define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6612 //SION_CL4_WrRsp_BurstTarget_REG1 6613 #define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6614 //SION_CL4_WrRsp_TimeSlot_REG0 6615 #define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6616 //SION_CL4_WrRsp_TimeSlot_REG1 6617 #define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6618 //SION_CL4_Req_BurstTarget_REG0 6619 #define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6620 //SION_CL4_Req_BurstTarget_REG1 6621 #define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6622 //SION_CL4_Req_TimeSlot_REG0 6623 #define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6624 //SION_CL4_Req_TimeSlot_REG1 6625 #define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6626 //SION_CL4_ReqPoolCredit_Alloc_REG0 6627 #define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6628 //SION_CL4_ReqPoolCredit_Alloc_REG1 6629 #define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6630 //SION_CL4_DataPoolCredit_Alloc_REG0 6631 #define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6632 //SION_CL4_DataPoolCredit_Alloc_REG1 6633 #define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6634 //SION_CL4_RdRspPoolCredit_Alloc_REG0 6635 #define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6636 //SION_CL4_RdRspPoolCredit_Alloc_REG1 6637 #define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6638 //SION_CL4_WrRspPoolCredit_Alloc_REG0 6639 #define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6640 //SION_CL4_WrRspPoolCredit_Alloc_REG1 6641 #define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6642 //SION_CL5_RdRsp_BurstTarget_REG0 6643 #define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6644 //SION_CL5_RdRsp_BurstTarget_REG1 6645 #define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6646 //SION_CL5_RdRsp_TimeSlot_REG0 6647 #define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6648 //SION_CL5_RdRsp_TimeSlot_REG1 6649 #define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6650 //SION_CL5_WrRsp_BurstTarget_REG0 6651 #define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6652 //SION_CL5_WrRsp_BurstTarget_REG1 6653 #define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6654 //SION_CL5_WrRsp_TimeSlot_REG0 6655 #define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6656 //SION_CL5_WrRsp_TimeSlot_REG1 6657 #define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6658 //SION_CL5_Req_BurstTarget_REG0 6659 #define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6660 //SION_CL5_Req_BurstTarget_REG1 6661 #define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6662 //SION_CL5_Req_TimeSlot_REG0 6663 #define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6664 //SION_CL5_Req_TimeSlot_REG1 6665 #define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6666 //SION_CL5_ReqPoolCredit_Alloc_REG0 6667 #define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6668 //SION_CL5_ReqPoolCredit_Alloc_REG1 6669 #define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6670 //SION_CL5_DataPoolCredit_Alloc_REG0 6671 #define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6672 //SION_CL5_DataPoolCredit_Alloc_REG1 6673 #define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6674 //SION_CL5_RdRspPoolCredit_Alloc_REG0 6675 #define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6676 //SION_CL5_RdRspPoolCredit_Alloc_REG1 6677 #define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6678 //SION_CL5_WrRspPoolCredit_Alloc_REG0 6679 #define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6680 //SION_CL5_WrRspPoolCredit_Alloc_REG1 6681 #define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6682 //SION_CNTL_REG0 6683 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L 6684 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L 6685 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L 6686 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L 6687 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L 6688 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L 6689 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L 6690 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L 6691 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L 6692 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L 6693 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L 6694 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L 6695 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L 6696 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L 6697 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L 6698 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L 6699 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L 6700 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L 6701 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L 6702 #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L 6703 //SION_CNTL_REG1 6704 #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL 6705 #define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L 6706 6707 6708 // addressBlock: syshub_mmreg_direct_syshubdirect 6709 //SYSHUB_DS_CTRL_SOCCLK 6710 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 6711 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 6712 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 6713 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 6714 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 6715 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 6716 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 6717 #define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 6718 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 6719 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 6720 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 6721 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 6722 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 6723 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 6724 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 6725 #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 6726 #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 6727 #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L 6728 //SYSHUB_DS_CTRL2_SOCCLK 6729 #define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL 6730 //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 6731 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L 6732 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L 6733 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L 6734 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L 6735 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L 6736 //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 6737 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L 6738 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L 6739 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L 6740 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L 6741 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L 6742 //DMA_CLK0_SW0_SYSHUB_QOS_CNTL 6743 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6744 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6745 #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6746 //DMA_CLK0_SW1_SYSHUB_QOS_CNTL 6747 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6748 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6749 #define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6750 //DMA_CLK0_SW0_CL0_CNTL 6751 #define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6752 #define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6753 #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6754 #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6755 #define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6756 #define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6757 //DMA_CLK0_SW0_CL1_CNTL 6758 #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6759 #define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6760 #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6761 #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6762 #define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6763 #define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6764 //DMA_CLK0_SW0_CL2_CNTL 6765 #define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6766 #define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6767 #define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6768 #define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6769 #define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6770 #define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6771 //DMA_CLK0_SW0_CL3_CNTL 6772 #define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6773 #define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6774 #define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6775 #define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6776 #define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6777 #define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6778 //DMA_CLK0_SW0_CL4_CNTL 6779 #define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6780 #define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6781 #define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6782 #define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6783 #define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6784 #define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6785 //DMA_CLK0_SW0_CL5_CNTL 6786 #define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6787 #define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6788 #define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6789 #define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6790 #define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6791 #define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6792 //DMA_CLK0_SW1_CL0_CNTL 6793 #define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6794 #define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6795 #define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6796 #define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6797 #define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6798 #define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6799 //DMA_CLK0_SW2_CL0_CNTL 6800 #define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6801 #define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6802 #define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6803 #define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6804 #define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6805 #define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6806 //SYSHUB_CG_CNTL 6807 #define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L 6808 #define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L 6809 #define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L 6810 //SYSHUB_TRANS_IDLE 6811 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L 6812 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L 6813 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L 6814 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L 6815 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L 6816 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L 6817 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L 6818 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L 6819 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L 6820 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L 6821 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L 6822 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L 6823 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L 6824 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L 6825 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L 6826 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L 6827 #define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L 6828 //SYSHUB_HP_TIMER 6829 #define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL 6830 //SYSHUB_SCRATCH 6831 #define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL 6832 //SYSHUB_DS_CTRL_SHUBCLK 6833 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 6834 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 6835 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 6836 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 6837 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 6838 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 6839 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 6840 #define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 6841 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 6842 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 6843 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 6844 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 6845 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 6846 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 6847 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 6848 #define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 6849 #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 6850 #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L 6851 //SYSHUB_DS_CTRL2_SHUBCLK 6852 #define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL 6853 //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 6854 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L 6855 #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L 6856 //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 6857 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L 6858 #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L 6859 //DMA_CLK1_SW0_SYSHUB_QOS_CNTL 6860 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6861 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6862 #define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6863 //DMA_CLK1_SW1_SYSHUB_QOS_CNTL 6864 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6865 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6866 #define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6867 //DMA_CLK1_SW0_CL0_CNTL 6868 #define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6869 #define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6870 #define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6871 #define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6872 #define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6873 #define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6874 //DMA_CLK1_SW0_CL1_CNTL 6875 #define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6876 #define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6877 #define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6878 #define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6879 #define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6880 #define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6881 //DMA_CLK1_SW0_CL2_CNTL 6882 #define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6883 #define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6884 #define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6885 #define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6886 #define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6887 #define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6888 //DMA_CLK1_SW0_CL3_CNTL 6889 #define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6890 #define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6891 #define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6892 #define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6893 #define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6894 #define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6895 //DMA_CLK1_SW0_CL4_CNTL 6896 #define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6897 #define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6898 #define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6899 #define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6900 #define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6901 #define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6902 //DMA_CLK1_SW1_CL0_CNTL 6903 #define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6904 #define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6905 #define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6906 #define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6907 #define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6908 #define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6909 //DMA_CLK1_SW1_CL1_CNTL 6910 #define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6911 #define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6912 #define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6913 #define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6914 #define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6915 #define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6916 //DMA_CLK1_SW1_CL2_CNTL 6917 #define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6918 #define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6919 #define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6920 #define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6921 #define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6922 #define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6923 //DMA_CLK1_SW1_CL3_CNTL 6924 #define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6925 #define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6926 #define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6927 #define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6928 #define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6929 #define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6930 //DMA_CLK1_SW1_CL4_CNTL 6931 #define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6932 #define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6933 #define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6934 #define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6935 #define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6936 #define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6937 6938 6939 // addressBlock: gdc_ras_gdc_ras_regblk 6940 //GDC_RAS_LEAF0_CTRL 6941 #define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L 6942 #define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6943 #define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L 6944 #define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L 6945 #define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6946 #define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6947 #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6948 #define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6949 #define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L 6950 #define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6951 #define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6952 #define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L 6953 //GDC_RAS_LEAF1_CTRL 6954 #define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L 6955 #define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6956 #define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L 6957 #define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L 6958 #define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6959 #define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6960 #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6961 #define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6962 #define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L 6963 #define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6964 #define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6965 #define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L 6966 //GDC_RAS_LEAF2_CTRL 6967 #define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L 6968 #define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6969 #define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L 6970 #define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L 6971 #define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6972 #define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6973 #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6974 #define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6975 #define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L 6976 #define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6977 #define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6978 #define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L 6979 //GDC_RAS_LEAF3_CTRL 6980 #define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L 6981 #define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6982 #define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L 6983 #define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L 6984 #define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6985 #define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6986 #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6987 #define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6988 #define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L 6989 #define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6990 #define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6991 #define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L 6992 //GDC_RAS_LEAF4_CTRL 6993 #define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L 6994 #define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6995 #define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L 6996 #define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L 6997 #define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6998 #define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6999 #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 7000 #define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L 7001 #define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L 7002 #define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L 7003 #define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 7004 #define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L 7005 //GDC_RAS_LEAF5_CTRL 7006 #define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L 7007 #define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 7008 #define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L 7009 #define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L 7010 #define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 7011 #define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L 7012 #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 7013 #define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L 7014 #define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L 7015 #define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L 7016 #define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 7017 #define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L 7018 7019 7020 // addressBlock: gdc_rst_GDCRST_DEC 7021 //SHUB_PF_FLR_RST 7022 #define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L 7023 #define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L 7024 #define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L 7025 #define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L 7026 #define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L 7027 #define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L 7028 #define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L 7029 #define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L 7030 //SHUB_GFX_DRV_MODE1_RST 7031 #define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L 7032 //SHUB_LINK_RESET 7033 #define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L 7034 //SHUB_PF0_VF_FLR_RST 7035 #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L 7036 #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L 7037 #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L 7038 #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L 7039 #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L 7040 #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L 7041 #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L 7042 #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L 7043 #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L 7044 #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L 7045 #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L 7046 #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L 7047 #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L 7048 #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L 7049 #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L 7050 #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L 7051 #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L 7052 //SHUB_HARD_RST_CTRL 7053 #define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L 7054 #define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L 7055 #define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L 7056 #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L 7057 #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L 7058 //SHUB_SOFT_RST_CTRL 7059 #define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L 7060 #define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L 7061 #define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L 7062 #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L 7063 #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L 7064 //SHUB_SDP_PORT_RST 7065 #define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L 7066 7067 7068 // addressBlock: bif_bx_pf_SYSDEC 7069 //SBIOS_SCRATCH_0 7070 #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7071 //SBIOS_SCRATCH_1 7072 #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7073 //SBIOS_SCRATCH_2 7074 #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7075 //SBIOS_SCRATCH_3 7076 #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7077 //BIOS_SCRATCH_0 7078 #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL 7079 //BIOS_SCRATCH_1 7080 #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL 7081 //BIOS_SCRATCH_2 7082 #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL 7083 //BIOS_SCRATCH_3 7084 #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL 7085 //BIOS_SCRATCH_4 7086 #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL 7087 //BIOS_SCRATCH_5 7088 #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL 7089 //BIOS_SCRATCH_6 7090 #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL 7091 //BIOS_SCRATCH_7 7092 #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL 7093 //BIOS_SCRATCH_8 7094 #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL 7095 //BIOS_SCRATCH_9 7096 #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL 7097 //BIOS_SCRATCH_10 7098 #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL 7099 //BIOS_SCRATCH_11 7100 #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL 7101 //BIOS_SCRATCH_12 7102 #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL 7103 //BIOS_SCRATCH_13 7104 #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL 7105 //BIOS_SCRATCH_14 7106 #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL 7107 //BIOS_SCRATCH_15 7108 #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL 7109 //BIF_RLC_INTR_CNTL 7110 #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L 7111 #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L 7112 #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L 7113 #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L 7114 //BIF_VCE_INTR_CNTL 7115 #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L 7116 #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L 7117 #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L 7118 #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L 7119 //BIF_UVD_INTR_CNTL 7120 #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L 7121 #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L 7122 #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L 7123 #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L 7124 //GFX_MMIOREG_CAM_ADDR0 7125 #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL 7126 //GFX_MMIOREG_CAM_REMAP_ADDR0 7127 #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL 7128 //GFX_MMIOREG_CAM_ADDR1 7129 #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL 7130 //GFX_MMIOREG_CAM_REMAP_ADDR1 7131 #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL 7132 //GFX_MMIOREG_CAM_ADDR2 7133 #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL 7134 //GFX_MMIOREG_CAM_REMAP_ADDR2 7135 #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL 7136 //GFX_MMIOREG_CAM_ADDR3 7137 #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL 7138 //GFX_MMIOREG_CAM_REMAP_ADDR3 7139 #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL 7140 //GFX_MMIOREG_CAM_ADDR4 7141 #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL 7142 //GFX_MMIOREG_CAM_REMAP_ADDR4 7143 #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL 7144 //GFX_MMIOREG_CAM_ADDR5 7145 #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL 7146 //GFX_MMIOREG_CAM_REMAP_ADDR5 7147 #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL 7148 //GFX_MMIOREG_CAM_ADDR6 7149 #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL 7150 //GFX_MMIOREG_CAM_REMAP_ADDR6 7151 #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL 7152 //GFX_MMIOREG_CAM_ADDR7 7153 #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL 7154 //GFX_MMIOREG_CAM_REMAP_ADDR7 7155 #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL 7156 //GFX_MMIOREG_CAM_CNTL 7157 #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL 7158 //GFX_MMIOREG_CAM_ZERO_CPL 7159 #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL 7160 //GFX_MMIOREG_CAM_ONE_CPL 7161 #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL 7162 //GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 7163 #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL 7164 7165 7166 // addressBlock: bif_bx_pf_SYSPFVFDEC 7167 //MM_INDEX 7168 #define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL 7169 #define MM_INDEX__MM_APER__MASK 0x80000000L 7170 //MM_DATA 7171 #define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL 7172 //MM_INDEX_HI 7173 #define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL 7174 //SYSHUB_INDEX_OVLP 7175 #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL 7176 //SYSHUB_DATA_OVLP 7177 #define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL 7178 //PCIE_INDEX 7179 #define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL 7180 //PCIE_DATA 7181 #define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL 7182 //PCIE_INDEX2 7183 #define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL 7184 //PCIE_DATA2 7185 #define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL 7186 7187 7188 // addressBlock: rcc_dwn_BIFDEC1 7189 //DN_PCIE_RESERVED 7190 #define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL 7191 //DN_PCIE_SCRATCH 7192 #define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL 7193 //DN_PCIE_CNTL 7194 #define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L 7195 #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L 7196 #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L 7197 //DN_PCIE_CONFIG_CNTL 7198 #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L 7199 //DN_PCIE_RX_CNTL2 7200 #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L 7201 //DN_PCIE_BUS_CNTL 7202 #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L 7203 #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L 7204 //DN_PCIE_CFG_CNTL 7205 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L 7206 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L 7207 #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L 7208 //DN_PCIE_STRAP_F0 7209 #define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L 7210 #define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L 7211 #define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L 7212 //DN_PCIE_STRAP_MISC 7213 #define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L 7214 #define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L 7215 //DN_PCIE_STRAP_MISC2 7216 #define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L 7217 7218 7219 // addressBlock: rcc_dwnp_BIFDEC1 7220 //PCIEP_RESERVED 7221 #define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL 7222 //PCIEP_SCRATCH 7223 #define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL 7224 //PCIE_ERR_CNTL 7225 #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L 7226 #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L 7227 #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L 7228 #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L 7229 //PCIE_RX_CNTL 7230 #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L 7231 #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L 7232 #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L 7233 #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L 7234 #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L 7235 //PCIE_LC_SPEED_CNTL 7236 #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L 7237 #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L 7238 //PCIE_LC_CNTL2 7239 #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L 7240 //PCIEP_STRAP_MISC 7241 #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L 7242 //LTR_MSG_INFO_FROM_EP 7243 #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL 7244 7245 7246 // addressBlock: rcc_ep_BIFDEC1 7247 //EP_PCIE_SCRATCH 7248 #define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL 7249 //EP_PCIE_CNTL 7250 #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L 7251 #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L 7252 #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L 7253 //EP_PCIE_INT_CNTL 7254 #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L 7255 #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L 7256 #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L 7257 #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L 7258 #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L 7259 #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L 7260 //EP_PCIE_INT_STATUS 7261 #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L 7262 #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L 7263 #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L 7264 #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L 7265 #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L 7266 #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L 7267 //EP_PCIE_RX_CNTL2 7268 #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L 7269 //EP_PCIE_BUS_CNTL 7270 #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L 7271 //EP_PCIE_CFG_CNTL 7272 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L 7273 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L 7274 #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L 7275 //EP_PCIE_OBFF_CNTL 7276 #define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L 7277 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L 7278 #define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L 7279 #define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L 7280 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L 7281 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L 7282 #define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L 7283 #define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L 7284 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L 7285 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L 7286 #define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L 7287 #define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L 7288 //EP_PCIE_TX_LTR_CNTL 7289 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L 7290 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L 7291 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L 7292 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L 7293 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L 7294 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L 7295 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L 7296 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L 7297 #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L 7298 //EP_PCIE_STRAP_MISC 7299 #define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L 7300 //EP_PCIE_STRAP_MISC2 7301 #define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L 7302 //EP_PCIE_STRAP_PI 7303 //EP_PCIE_F0_DPA_CAP 7304 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L 7305 #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L 7306 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L 7307 #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L 7308 //EP_PCIE_F0_DPA_LATENCY_INDICATOR 7309 #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL 7310 //EP_PCIE_F0_DPA_CNTL 7311 #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL 7312 #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L 7313 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 7314 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7315 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 7316 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7317 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 7318 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7319 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 7320 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7321 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 7322 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7323 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 7324 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7325 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 7326 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7327 //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 7328 #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7329 //EP_PCIE_PME_CONTROL 7330 #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL 7331 //EP_PCIEP_RESERVED 7332 #define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL 7333 //EP_PCIE_TX_CNTL 7334 #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L 7335 #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L 7336 #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L 7337 #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L 7338 #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L 7339 //EP_PCIE_TX_REQUESTER_ID 7340 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L 7341 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L 7342 #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L 7343 //EP_PCIE_ERR_CNTL 7344 #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L 7345 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L 7346 #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L 7347 #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L 7348 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L 7349 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L 7350 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L 7351 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L 7352 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L 7353 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L 7354 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L 7355 #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L 7356 //EP_PCIE_RX_CNTL 7357 #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L 7358 #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L 7359 #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L 7360 #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L 7361 #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L 7362 #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L 7363 #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L 7364 #define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L 7365 //EP_PCIE_LC_SPEED_CNTL 7366 #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L 7367 #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L 7368 7369 7370 // addressBlock: bif_bx_pf_BIFDEC1 7371 //BIF_MM_INDACCESS_CNTL 7372 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L 7373 //BUS_CNTL 7374 #define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L 7375 #define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L 7376 #define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L 7377 #define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L 7378 #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L 7379 #define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L 7380 #define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L 7381 #define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L 7382 #define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L 7383 #define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L 7384 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L 7385 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L 7386 #define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L 7387 #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L 7388 #define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L 7389 #define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L 7390 //BIF_SCRATCH0 7391 #define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL 7392 //BIF_SCRATCH1 7393 #define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL 7394 //BX_RESET_EN 7395 #define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L 7396 #define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L 7397 #define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L 7398 #define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L 7399 #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L 7400 //MM_CFGREGS_CNTL 7401 #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L 7402 #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L 7403 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L 7404 //BX_RESET_CNTL 7405 #define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L 7406 //INTERRUPT_CNTL 7407 #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L 7408 #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L 7409 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L 7410 #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L 7411 #define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L 7412 #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L 7413 //INTERRUPT_CNTL2 7414 #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL 7415 //CLKREQB_PAD_CNTL 7416 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L 7417 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L 7418 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L 7419 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L 7420 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L 7421 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L 7422 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L 7423 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L 7424 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L 7425 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L 7426 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L 7427 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L 7428 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L 7429 #define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L 7430 //CLKREQB_PERF_COUNTER 7431 #define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL 7432 //BIF_CLK_CTRL 7433 #define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L 7434 #define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L 7435 //BIF_FEATURES_CONTROL_MISC 7436 #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L 7437 #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L 7438 #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L 7439 #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L 7440 #define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L 7441 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L 7442 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L 7443 #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L 7444 #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L 7445 #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L 7446 #define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L 7447 #define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L 7448 #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L 7449 //BIF_DOORBELL_CNTL 7450 #define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L 7451 #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L 7452 #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L 7453 #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L 7454 #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L 7455 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L 7456 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L 7457 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L 7458 #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L 7459 //BIF_DOORBELL_INT_CNTL 7460 #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L 7461 #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L 7462 #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L 7463 #define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L 7464 //BIF_SLVARB_MODE 7465 #define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L 7466 //BIF_FB_EN 7467 #define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L 7468 #define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L 7469 //BIF_BUSY_DELAY_CNTR 7470 #define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL 7471 //BIF_PERFMON_CNTL 7472 #define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L 7473 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L 7474 #define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L 7475 #define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L 7476 #define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L 7477 //BIF_PERFCOUNTER0_RESULT 7478 #define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL 7479 //BIF_PERFCOUNTER1_RESULT 7480 #define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL 7481 //BIF_MST_TRANS_PENDING_VF 7482 #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL 7483 //BIF_SLV_TRANS_PENDING_VF 7484 #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL 7485 //BACO_CNTL 7486 #define BACO_CNTL__BACO_EN__MASK 0x00000001L 7487 #define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L 7488 #define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L 7489 #define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L 7490 #define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L 7491 #define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L 7492 #define BACO_CNTL__BACO_MODE__MASK 0x00000100L 7493 #define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L 7494 #define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L 7495 //BIF_BACO_EXIT_TIME0 7496 #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL 7497 //BIF_BACO_EXIT_TIMER1 7498 #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL 7499 #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L 7500 #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L 7501 #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L 7502 #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L 7503 #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L 7504 //BIF_BACO_EXIT_TIMER2 7505 #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL 7506 //BIF_BACO_EXIT_TIMER3 7507 #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL 7508 //BIF_BACO_EXIT_TIMER4 7509 #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL 7510 //MEM_TYPE_CNTL 7511 #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L 7512 //SMU_BIF_VDDGFX_PWR_STATUS 7513 #define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L 7514 //BIF_VDDGFX_GFX0_LOWER 7515 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL 7516 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L 7517 #define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L 7518 //BIF_VDDGFX_GFX0_UPPER 7519 #define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL 7520 //BIF_VDDGFX_GFX1_LOWER 7521 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL 7522 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L 7523 #define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L 7524 //BIF_VDDGFX_GFX1_UPPER 7525 #define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL 7526 //BIF_VDDGFX_GFX2_LOWER 7527 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL 7528 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L 7529 #define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L 7530 //BIF_VDDGFX_GFX2_UPPER 7531 #define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL 7532 //BIF_VDDGFX_GFX3_LOWER 7533 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL 7534 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L 7535 #define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L 7536 //BIF_VDDGFX_GFX3_UPPER 7537 #define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL 7538 //BIF_VDDGFX_GFX4_LOWER 7539 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL 7540 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L 7541 #define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L 7542 //BIF_VDDGFX_GFX4_UPPER 7543 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL 7544 //BIF_VDDGFX_GFX5_LOWER 7545 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL 7546 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L 7547 #define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L 7548 //BIF_VDDGFX_GFX5_UPPER 7549 #define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL 7550 //BIF_VDDGFX_RSV1_LOWER 7551 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL 7552 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L 7553 #define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L 7554 //BIF_VDDGFX_RSV1_UPPER 7555 #define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL 7556 //BIF_VDDGFX_RSV2_LOWER 7557 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL 7558 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L 7559 #define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L 7560 //BIF_VDDGFX_RSV2_UPPER 7561 #define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL 7562 //BIF_VDDGFX_RSV3_LOWER 7563 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL 7564 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L 7565 #define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L 7566 //BIF_VDDGFX_RSV3_UPPER 7567 #define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL 7568 //BIF_VDDGFX_RSV4_LOWER 7569 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL 7570 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L 7571 #define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L 7572 //BIF_VDDGFX_RSV4_UPPER 7573 #define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL 7574 //BIF_VDDGFX_FB_CMP 7575 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L 7576 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L 7577 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L 7578 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L 7579 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L 7580 #define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L 7581 //BIF_DOORBELL_GBLAPER1_LOWER 7582 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL 7583 #define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L 7584 //BIF_DOORBELL_GBLAPER1_UPPER 7585 #define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL 7586 //BIF_DOORBELL_GBLAPER2_LOWER 7587 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL 7588 #define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L 7589 //BIF_DOORBELL_GBLAPER2_UPPER 7590 #define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL 7591 //REMAP_HDP_MEM_FLUSH_CNTL 7592 #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL 7593 //REMAP_HDP_REG_FLUSH_CNTL 7594 #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL 7595 //BIF_RB_CNTL 7596 #define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L 7597 #define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL 7598 #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L 7599 #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L 7600 #define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L 7601 #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L 7602 //BIF_RB_BASE 7603 #define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL 7604 //BIF_RB_RPTR 7605 #define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL 7606 //BIF_RB_WPTR 7607 #define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L 7608 #define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL 7609 //BIF_RB_WPTR_ADDR_HI 7610 #define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL 7611 //BIF_RB_WPTR_ADDR_LO 7612 #define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL 7613 //MAILBOX_INDEX 7614 #define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL 7615 //BIF_GPUIOV_RESET_NOTIFICATION 7616 #define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL 7617 //BIF_UVD_GPUIOV_CFG_SIZE 7618 #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7619 //BIF_VCE_GPUIOV_CFG_SIZE 7620 #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7621 //BIF_GFX_SDMA_GPUIOV_CFG_SIZE 7622 #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7623 //BIF_GMI_WRR_WEIGHT 7624 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL 7625 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L 7626 #define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L 7627 //NBIF_STRAP_WRITE_CTRL 7628 #define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L 7629 //BIF_PERSTB_PAD_CNTL 7630 #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL 7631 //BIF_PX_EN_PAD_CNTL 7632 #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL 7633 //BIF_REFPADKIN_PAD_CNTL 7634 #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL 7635 //BIF_CLKREQB_PAD_CNTL 7636 #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL 7637 7638 7639 // addressBlock: rcc_pf_0_BIFDEC1 7640 //RCC_BACO_CNTL_MISC 7641 #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L 7642 #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L 7643 //RCC_RESET_EN 7644 #define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L 7645 //RCC_VDM_SUPPORT 7646 #define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L 7647 #define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L 7648 #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L 7649 #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L 7650 #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L 7651 //RCC_PEER_REG_RANGE0 7652 #define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL 7653 #define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L 7654 //RCC_PEER_REG_RANGE1 7655 #define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL 7656 #define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L 7657 //RCC_BUS_CNTL 7658 #define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L 7659 #define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L 7660 #define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L 7661 #define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L 7662 #define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L 7663 #define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L 7664 #define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L 7665 #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L 7666 #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L 7667 #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L 7668 #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L 7669 #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L 7670 #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L 7671 #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L 7672 #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L 7673 #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L 7674 #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L 7675 #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L 7676 #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L 7677 //RCC_CONFIG_CNTL 7678 #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L 7679 #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L 7680 #define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L 7681 //RCC_CONFIG_F0_BASE 7682 #define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL 7683 //RCC_CONFIG_APER_SIZE 7684 #define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL 7685 //RCC_CONFIG_REG_APER_SIZE 7686 #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL 7687 //RCC_XDMA_LO 7688 #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL 7689 #define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L 7690 //RCC_XDMA_HI 7691 #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL 7692 //RCC_FEATURES_CONTROL_MISC 7693 #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L 7694 #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L 7695 #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L 7696 #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L 7697 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L 7698 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L 7699 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L 7700 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L 7701 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L 7702 #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L 7703 #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L 7704 #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L 7705 #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L 7706 #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L 7707 //RCC_BUSNUM_CNTL1 7708 #define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL 7709 //RCC_BUSNUM_LIST0 7710 #define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL 7711 #define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L 7712 #define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L 7713 #define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L 7714 //RCC_BUSNUM_LIST1 7715 #define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL 7716 #define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L 7717 #define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L 7718 #define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L 7719 //RCC_BUSNUM_CNTL2 7720 #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL 7721 #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L 7722 #define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L 7723 #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L 7724 //RCC_CAPTURE_HOST_BUSNUM 7725 #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L 7726 //RCC_HOST_BUSNUM 7727 #define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL 7728 //RCC_PEER0_FB_OFFSET_HI 7729 #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL 7730 //RCC_PEER0_FB_OFFSET_LO 7731 #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL 7732 #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L 7733 //RCC_PEER1_FB_OFFSET_HI 7734 #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL 7735 //RCC_PEER1_FB_OFFSET_LO 7736 #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL 7737 #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L 7738 //RCC_PEER2_FB_OFFSET_HI 7739 #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL 7740 //RCC_PEER2_FB_OFFSET_LO 7741 #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL 7742 #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L 7743 //RCC_PEER3_FB_OFFSET_HI 7744 #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL 7745 //RCC_PEER3_FB_OFFSET_LO 7746 #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL 7747 #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L 7748 //RCC_DEVFUNCNUM_LIST0 7749 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL 7750 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L 7751 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L 7752 #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L 7753 //RCC_DEVFUNCNUM_LIST1 7754 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL 7755 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L 7756 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L 7757 #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L 7758 //RCC_DEV0_LINK_CNTL 7759 #define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L 7760 #define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L 7761 //RCC_CMN_LINK_CNTL 7762 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L 7763 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L 7764 #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L 7765 #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L 7766 //RCC_EP_REQUESTERID_RESTORE 7767 #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL 7768 #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L 7769 //RCC_LTR_LSWITCH_CNTL 7770 #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL 7771 //RCC_MH_ARB_CNTL 7772 #define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L 7773 #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL 7774 7775 7776 // addressBlock: rcc_pf_0_BIFDEC2 7777 //GFXMSIX_VECT0_ADDR_LO 7778 #define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7779 //GFXMSIX_VECT0_ADDR_HI 7780 #define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7781 //GFXMSIX_VECT0_MSG_DATA 7782 #define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7783 //GFXMSIX_VECT0_CONTROL 7784 #define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L 7785 //GFXMSIX_VECT1_ADDR_LO 7786 #define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7787 //GFXMSIX_VECT1_ADDR_HI 7788 #define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7789 //GFXMSIX_VECT1_MSG_DATA 7790 #define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7791 //GFXMSIX_VECT1_CONTROL 7792 #define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L 7793 //GFXMSIX_VECT2_ADDR_LO 7794 #define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7795 //GFXMSIX_VECT2_ADDR_HI 7796 #define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7797 //GFXMSIX_VECT2_MSG_DATA 7798 #define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7799 //GFXMSIX_VECT2_CONTROL 7800 #define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L 7801 //GFXMSIX_PBA 7802 #define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L 7803 #define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L 7804 #define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L 7805 7806 7807 // addressBlock: rcc_strap_BIFDEC1 7808 //RCC_DEV0_PORT_STRAP0 7809 #define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L 7810 #define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L 7811 #define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L 7812 #define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L 7813 #define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L 7814 #define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L 7815 #define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L 7816 #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L 7817 #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L 7818 #define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L 7819 //RCC_DEV0_PORT_STRAP1 7820 #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL 7821 #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L 7822 //RCC_DEV0_PORT_STRAP2 7823 #define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L 7824 #define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L 7825 #define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L 7826 #define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L 7827 #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L 7828 #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L 7829 #define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L 7830 #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L 7831 #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L 7832 #define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L 7833 #define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L 7834 #define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L 7835 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L 7836 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L 7837 #define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L 7838 #define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L 7839 #define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L 7840 #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L 7841 #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L 7842 #define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L 7843 #define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L 7844 //RCC_DEV0_PORT_STRAP3 7845 #define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L 7846 #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L 7847 #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L 7848 #define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L 7849 #define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L 7850 #define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L 7851 #define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L 7852 #define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L 7853 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L 7854 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L 7855 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L 7856 #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L 7857 #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L 7858 #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L 7859 #define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L 7860 #define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L 7861 #define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L 7862 //RCC_DEV0_PORT_STRAP4 7863 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL 7864 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L 7865 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L 7866 #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L 7867 //RCC_DEV0_PORT_STRAP5 7868 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL 7869 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L 7870 #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L 7871 #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L 7872 #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L 7873 #define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L 7874 #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L 7875 #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L 7876 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L 7877 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L 7878 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L 7879 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L 7880 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L 7881 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L 7882 #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L 7883 #define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L 7884 #define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L 7885 //RCC_DEV0_PORT_STRAP6 7886 #define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L 7887 #define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L 7888 //RCC_DEV0_PORT_STRAP7 7889 #define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL 7890 #define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L 7891 #define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L 7892 #define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L 7893 #define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L 7894 #define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L 7895 //RCC_DEV0_EPF0_STRAP0 7896 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 7897 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L 7898 #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L 7899 #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L 7900 #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L 7901 #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L 7902 #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L 7903 #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L 7904 //RCC_DEV0_EPF0_STRAP1 7905 #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 7906 #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L 7907 //RCC_DEV0_EPF0_STRAP13 7908 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL 7909 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L 7910 #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L 7911 //RCC_DEV0_EPF0_STRAP2 7912 #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L 7913 #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL 7914 #define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L 7915 #define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L 7916 #define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L 7917 #define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L 7918 #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L 7919 #define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L 7920 #define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L 7921 #define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L 7922 #define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L 7923 #define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L 7924 #define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L 7925 #define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L 7926 #define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L 7927 #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L 7928 #define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L 7929 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L 7930 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L 7931 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L 7932 #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L 7933 //RCC_DEV0_EPF0_STRAP3 7934 #define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L 7935 #define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L 7936 #define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL 7937 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L 7938 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L 7939 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L 7940 #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L 7941 #define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L 7942 #define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L 7943 #define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L 7944 #define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L 7945 //RCC_DEV0_EPF0_STRAP4 7946 #define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL 7947 #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L 7948 #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L 7949 #define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L 7950 #define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L 7951 #define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L 7952 #define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L 7953 //RCC_DEV0_EPF0_STRAP5 7954 #define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL 7955 //RCC_DEV0_EPF0_STRAP8 7956 #define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L 7957 #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L 7958 #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L 7959 #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L 7960 #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L 7961 #define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L 7962 #define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L 7963 #define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L 7964 #define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L 7965 #define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L 7966 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L 7967 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L 7968 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L 7969 #define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L 7970 #define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L 7971 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L 7972 #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L 7973 #define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L 7974 //RCC_DEV0_EPF0_STRAP9 7975 //RCC_DEV0_EPF1_STRAP0 7976 #define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL 7977 #define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L 7978 #define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L 7979 #define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L 7980 #define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L 7981 #define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L 7982 #define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L 7983 //RCC_DEV0_EPF1_STRAP10 7984 #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7985 #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7986 //RCC_DEV0_EPF1_STRAP11 7987 #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7988 #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7989 //RCC_DEV0_EPF1_STRAP12 7990 #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7991 #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7992 //RCC_DEV0_EPF1_STRAP13 7993 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL 7994 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L 7995 #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L 7996 //RCC_DEV0_EPF1_STRAP2 7997 #define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L 7998 #define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L 7999 #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L 8000 #define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L 8001 #define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L 8002 #define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L 8003 #define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L 8004 #define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L 8005 #define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L 8006 #define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L 8007 #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L 8008 //RCC_DEV0_EPF1_STRAP3 8009 #define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L 8010 #define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L 8011 #define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL 8012 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L 8013 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L 8014 #define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L 8015 #define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L 8016 #define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L 8017 #define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L 8018 #define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L 8019 //RCC_DEV0_EPF1_STRAP4 8020 #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L 8021 #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L 8022 #define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L 8023 #define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L 8024 #define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L 8025 #define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L 8026 //RCC_DEV0_EPF1_STRAP5 8027 #define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL 8028 //RCC_DEV0_EPF1_STRAP6 8029 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L 8030 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L 8031 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L 8032 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L 8033 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L 8034 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L 8035 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L 8036 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L 8037 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L 8038 #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L 8039 //RCC_DEV0_EPF1_STRAP7 8040 #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L 8041 #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL 8042 8043 8044 // addressBlock: bif_bx_pf_BIFPFVFDEC1 8045 //BIF_BME_STATUS 8046 #define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L 8047 #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L 8048 //BIF_ATOMIC_ERR_LOG 8049 #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L 8050 #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L 8051 #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L 8052 #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L 8053 //DOORBELL_SELFRING_GPA_APER_BASE_HIGH 8054 #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL 8055 //DOORBELL_SELFRING_GPA_APER_BASE_LOW 8056 #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL 8057 //DOORBELL_SELFRING_GPA_APER_CNTL 8058 #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L 8059 #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L 8060 //HDP_REG_COHERENCY_FLUSH_CNTL 8061 #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L 8062 //HDP_MEM_COHERENCY_FLUSH_CNTL 8063 #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L 8064 //GPU_HDP_FLUSH_REQ 8065 #define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L 8066 #define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L 8067 #define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L 8068 #define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L 8069 #define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L 8070 #define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L 8071 #define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L 8072 #define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L 8073 #define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L 8074 #define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L 8075 #define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L 8076 #define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L 8077 //GPU_HDP_FLUSH_DONE 8078 #define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L 8079 #define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L 8080 #define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L 8081 #define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L 8082 #define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L 8083 #define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L 8084 #define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L 8085 #define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L 8086 #define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L 8087 #define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L 8088 #define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L 8089 #define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L 8090 //BIF_TRANS_PENDING 8091 #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L 8092 #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L 8093 //MAILBOX_MSGBUF_TRN_DW0 8094 #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL 8095 //MAILBOX_MSGBUF_TRN_DW1 8096 #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL 8097 //MAILBOX_MSGBUF_TRN_DW2 8098 #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL 8099 //MAILBOX_MSGBUF_TRN_DW3 8100 #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL 8101 //MAILBOX_MSGBUF_RCV_DW0 8102 #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL 8103 //MAILBOX_MSGBUF_RCV_DW1 8104 #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL 8105 //MAILBOX_MSGBUF_RCV_DW2 8106 #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL 8107 //MAILBOX_MSGBUF_RCV_DW3 8108 #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL 8109 //MAILBOX_CONTROL 8110 #define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L 8111 #define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L 8112 #define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L 8113 #define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L 8114 //MAILBOX_INT_CNTL 8115 #define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L 8116 #define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L 8117 //BIF_VMHV_MAILBOX 8118 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L 8119 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L 8120 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L 8121 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L 8122 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L 8123 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L 8124 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L 8125 #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L 8126 8127 8128 // addressBlock: rcc_pf_0_BIFPFVFDEC1 8129 //RCC_DOORBELL_APER_EN 8130 #define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L 8131 //RCC_CONFIG_MEMSIZE 8132 #define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL 8133 //RCC_CONFIG_RESERVED 8134 #define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL 8135 //RCC_IOV_FUNC_IDENTIFIER 8136 #define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L 8137 #define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L 8138 8139 8140 // addressBlock: syshub_mmreg_ind_syshubdec 8141 //SYSHUB_INDEX 8142 #define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL 8143 //SYSHUB_DATA 8144 #define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL 8145 8146 8147 // addressBlock: rcc_strap_rcc_strap_internal 8148 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 8149 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L 8150 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L 8151 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L 8152 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L 8153 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L 8154 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L 8155 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L 8156 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L 8157 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L 8158 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L 8159 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 8160 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL 8161 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L 8162 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 8163 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L 8164 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L 8165 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L 8166 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L 8167 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L 8168 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L 8169 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L 8170 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L 8171 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L 8172 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L 8173 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L 8174 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L 8175 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L 8176 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L 8177 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L 8178 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L 8179 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L 8180 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L 8181 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L 8182 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L 8183 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L 8184 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 8185 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L 8186 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L 8187 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L 8188 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L 8189 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L 8190 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L 8191 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L 8192 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L 8193 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L 8194 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L 8195 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L 8196 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L 8197 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L 8198 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L 8199 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L 8200 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L 8201 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L 8202 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 8203 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL 8204 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L 8205 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L 8206 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L 8207 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 8208 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL 8209 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L 8210 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L 8211 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L 8212 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L 8213 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L 8214 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L 8215 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L 8216 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L 8217 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L 8218 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L 8219 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L 8220 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L 8221 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L 8222 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L 8223 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L 8224 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L 8225 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 8226 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L 8227 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L 8228 //RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 8229 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL 8230 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L 8231 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L 8232 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L 8233 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L 8234 #define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L 8235 //RCC_DEV1_PORT_STRAP0 8236 #define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L 8237 #define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L 8238 #define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L 8239 #define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L 8240 #define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L 8241 #define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L 8242 #define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L 8243 #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L 8244 #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L 8245 #define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L 8246 //RCC_DEV1_PORT_STRAP1 8247 #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL 8248 #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L 8249 //RCC_DEV1_PORT_STRAP2 8250 #define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L 8251 #define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L 8252 #define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L 8253 #define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L 8254 #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L 8255 #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L 8256 #define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L 8257 #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L 8258 #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L 8259 #define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L 8260 #define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L 8261 #define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L 8262 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L 8263 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L 8264 #define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L 8265 #define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L 8266 #define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L 8267 #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L 8268 #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L 8269 #define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L 8270 #define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L 8271 //RCC_DEV1_PORT_STRAP3 8272 #define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L 8273 #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L 8274 #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L 8275 #define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L 8276 #define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L 8277 #define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L 8278 #define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L 8279 #define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L 8280 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L 8281 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L 8282 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L 8283 #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L 8284 #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L 8285 #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L 8286 #define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L 8287 #define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L 8288 #define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L 8289 //RCC_DEV1_PORT_STRAP4 8290 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL 8291 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L 8292 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L 8293 #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L 8294 //RCC_DEV1_PORT_STRAP5 8295 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL 8296 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L 8297 #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L 8298 #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L 8299 #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L 8300 #define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L 8301 #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L 8302 #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L 8303 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L 8304 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L 8305 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L 8306 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L 8307 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L 8308 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L 8309 #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L 8310 #define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L 8311 #define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L 8312 //RCC_DEV1_PORT_STRAP6 8313 #define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L 8314 #define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L 8315 //RCC_DEV1_PORT_STRAP7 8316 #define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL 8317 #define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L 8318 #define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L 8319 #define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L 8320 #define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L 8321 #define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L 8322 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 8323 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 8324 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L 8325 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L 8326 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L 8327 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L 8328 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L 8329 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L 8330 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L 8331 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 8332 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 8333 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L 8334 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 8335 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L 8336 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL 8337 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L 8338 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L 8339 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L 8340 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L 8341 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L 8342 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L 8343 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L 8344 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L 8345 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L 8346 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L 8347 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L 8348 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L 8349 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L 8350 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L 8351 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L 8352 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L 8353 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L 8354 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L 8355 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L 8356 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 8357 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L 8358 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L 8359 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL 8360 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L 8361 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L 8362 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L 8363 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L 8364 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L 8365 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L 8366 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L 8367 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L 8368 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 8369 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL 8370 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L 8371 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L 8372 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L 8373 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L 8374 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L 8375 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L 8376 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 8377 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL 8378 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 8379 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L 8380 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L 8381 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L 8382 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L 8383 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L 8384 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L 8385 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L 8386 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L 8387 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L 8388 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L 8389 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L 8390 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L 8391 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L 8392 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L 8393 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L 8394 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L 8395 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L 8396 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L 8397 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 8398 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 8399 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL 8400 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L 8401 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L 8402 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 8403 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL 8404 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L 8405 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L 8406 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L 8407 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L 8408 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L 8409 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L 8410 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 8411 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L 8412 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L 8413 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L 8414 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L 8415 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L 8416 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L 8417 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L 8418 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L 8419 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L 8420 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L 8421 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L 8422 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 8423 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L 8424 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L 8425 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL 8426 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L 8427 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L 8428 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L 8429 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L 8430 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L 8431 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L 8432 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L 8433 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 8434 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L 8435 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L 8436 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L 8437 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L 8438 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L 8439 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L 8440 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 8441 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL 8442 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 8443 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L 8444 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L 8445 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L 8446 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L 8447 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L 8448 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L 8449 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L 8450 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L 8451 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L 8452 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L 8453 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 8454 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L 8455 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL 8456 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 8457 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8458 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8459 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 8460 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8461 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8462 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 8463 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8464 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8465 //RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 8466 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL 8467 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L 8468 #define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L 8469 //RCC_DEV0_EPF2_STRAP0 8470 #define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL 8471 #define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L 8472 #define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L 8473 #define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L 8474 #define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L 8475 #define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L 8476 #define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L 8477 //RCC_DEV0_EPF2_STRAP2 8478 #define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L 8479 #define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L 8480 #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L 8481 #define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L 8482 #define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L 8483 #define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L 8484 #define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L 8485 #define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L 8486 #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L 8487 //RCC_DEV0_EPF2_STRAP3 8488 #define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L 8489 #define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L 8490 #define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL 8491 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L 8492 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L 8493 #define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L 8494 #define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L 8495 #define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L 8496 #define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L 8497 #define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L 8498 //RCC_DEV0_EPF2_STRAP4 8499 #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L 8500 #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L 8501 #define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L 8502 #define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L 8503 #define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L 8504 #define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L 8505 //RCC_DEV0_EPF2_STRAP5 8506 #define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL 8507 #define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L 8508 //RCC_DEV0_EPF2_STRAP6 8509 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L 8510 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L 8511 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L 8512 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L 8513 #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L 8514 //RCC_DEV0_EPF2_STRAP13 8515 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL 8516 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L 8517 #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L 8518 //RCC_DEV0_EPF3_STRAP0 8519 #define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL 8520 #define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L 8521 #define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L 8522 #define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L 8523 #define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L 8524 #define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L 8525 #define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L 8526 //RCC_DEV0_EPF3_STRAP2 8527 #define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L 8528 #define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L 8529 #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L 8530 #define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L 8531 #define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L 8532 #define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L 8533 #define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L 8534 #define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L 8535 #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L 8536 //RCC_DEV0_EPF3_STRAP3 8537 #define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L 8538 #define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L 8539 #define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL 8540 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L 8541 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L 8542 #define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L 8543 #define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L 8544 #define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L 8545 #define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L 8546 #define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L 8547 //RCC_DEV0_EPF3_STRAP4 8548 #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L 8549 #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L 8550 #define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L 8551 #define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L 8552 #define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L 8553 #define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L 8554 //RCC_DEV0_EPF3_STRAP5 8555 #define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL 8556 #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L 8557 #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L 8558 //RCC_DEV0_EPF3_STRAP6 8559 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L 8560 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L 8561 #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L 8562 //RCC_DEV0_EPF3_STRAP13 8563 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL 8564 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L 8565 #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L 8566 //RCC_DEV0_EPF4_STRAP0 8567 #define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL 8568 #define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L 8569 #define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L 8570 #define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L 8571 #define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L 8572 #define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L 8573 #define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L 8574 //RCC_DEV0_EPF4_STRAP2 8575 #define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L 8576 #define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L 8577 #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L 8578 #define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L 8579 #define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L 8580 #define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L 8581 #define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L 8582 #define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L 8583 #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L 8584 //RCC_DEV0_EPF4_STRAP3 8585 #define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L 8586 #define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L 8587 #define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL 8588 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L 8589 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L 8590 #define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L 8591 #define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L 8592 #define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L 8593 #define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L 8594 #define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L 8595 //RCC_DEV0_EPF4_STRAP4 8596 #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L 8597 #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L 8598 #define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L 8599 #define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L 8600 #define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L 8601 #define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L 8602 //RCC_DEV0_EPF4_STRAP5 8603 #define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL 8604 #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L 8605 #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L 8606 //RCC_DEV0_EPF4_STRAP6 8607 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L 8608 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L 8609 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L 8610 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L 8611 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L 8612 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L 8613 #define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L 8614 //RCC_DEV0_EPF4_STRAP13 8615 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL 8616 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L 8617 #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L 8618 //RCC_DEV0_EPF5_STRAP0 8619 #define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL 8620 #define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L 8621 #define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L 8622 #define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L 8623 #define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L 8624 #define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L 8625 #define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L 8626 //RCC_DEV0_EPF5_STRAP2 8627 #define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L 8628 #define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L 8629 #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L 8630 #define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L 8631 #define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L 8632 #define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L 8633 #define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L 8634 #define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L 8635 #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L 8636 //RCC_DEV0_EPF5_STRAP3 8637 #define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L 8638 #define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L 8639 #define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL 8640 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L 8641 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L 8642 #define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L 8643 #define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L 8644 #define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L 8645 #define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L 8646 #define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L 8647 //RCC_DEV0_EPF5_STRAP4 8648 #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L 8649 #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L 8650 #define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L 8651 #define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L 8652 #define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L 8653 #define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L 8654 //RCC_DEV0_EPF5_STRAP5 8655 #define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL 8656 //RCC_DEV0_EPF5_STRAP6 8657 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L 8658 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L 8659 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L 8660 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L 8661 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L 8662 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L 8663 #define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L 8664 //RCC_DEV0_EPF5_STRAP13 8665 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL 8666 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L 8667 #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L 8668 //RCC_DEV0_EPF6_STRAP0 8669 #define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL 8670 #define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L 8671 #define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L 8672 #define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L 8673 #define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L 8674 #define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L 8675 #define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L 8676 //RCC_DEV0_EPF6_STRAP2 8677 #define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L 8678 #define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L 8679 #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L 8680 #define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L 8681 #define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L 8682 #define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L 8683 #define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L 8684 #define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L 8685 #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L 8686 //RCC_DEV0_EPF6_STRAP3 8687 #define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L 8688 #define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L 8689 #define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL 8690 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L 8691 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L 8692 #define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L 8693 #define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L 8694 #define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L 8695 #define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L 8696 #define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L 8697 //RCC_DEV0_EPF6_STRAP4 8698 #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L 8699 #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L 8700 #define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L 8701 #define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L 8702 #define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L 8703 #define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L 8704 //RCC_DEV0_EPF6_STRAP5 8705 #define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL 8706 //RCC_DEV0_EPF6_STRAP6 8707 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L 8708 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L 8709 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L 8710 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L 8711 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L 8712 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L 8713 #define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L 8714 //RCC_DEV0_EPF6_STRAP13 8715 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL 8716 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L 8717 #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L 8718 //RCC_DEV0_EPF7_STRAP0 8719 #define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL 8720 #define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L 8721 #define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L 8722 #define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L 8723 #define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L 8724 #define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L 8725 #define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L 8726 //RCC_DEV0_EPF7_STRAP2 8727 #define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L 8728 #define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L 8729 #define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L 8730 #define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L 8731 #define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L 8732 #define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L 8733 #define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L 8734 #define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L 8735 #define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L 8736 //RCC_DEV0_EPF7_STRAP3 8737 #define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L 8738 #define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L 8739 #define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL 8740 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L 8741 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L 8742 #define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L 8743 #define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L 8744 #define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L 8745 #define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L 8746 #define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L 8747 //RCC_DEV0_EPF7_STRAP4 8748 #define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L 8749 #define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L 8750 #define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L 8751 #define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L 8752 #define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L 8753 #define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L 8754 //RCC_DEV0_EPF7_STRAP5 8755 #define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL 8756 //RCC_DEV0_EPF7_STRAP6 8757 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L 8758 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L 8759 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L 8760 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L 8761 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L 8762 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L 8763 #define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L 8764 //RCC_DEV0_EPF7_STRAP13 8765 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL 8766 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L 8767 #define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L 8768 //RCC_DEV1_EPF0_STRAP0 8769 #define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL 8770 #define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L 8771 #define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L 8772 #define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L 8773 #define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L 8774 #define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L 8775 #define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L 8776 //RCC_DEV1_EPF0_STRAP2 8777 #define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L 8778 #define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L 8779 #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L 8780 #define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L 8781 #define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L 8782 #define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L 8783 #define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L 8784 #define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L 8785 #define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L 8786 #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L 8787 //RCC_DEV1_EPF0_STRAP3 8788 #define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L 8789 #define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L 8790 #define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL 8791 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L 8792 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L 8793 #define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L 8794 #define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L 8795 #define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L 8796 #define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L 8797 #define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L 8798 //RCC_DEV1_EPF0_STRAP4 8799 #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L 8800 #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L 8801 #define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L 8802 #define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L 8803 #define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L 8804 #define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L 8805 //RCC_DEV1_EPF0_STRAP5 8806 #define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL 8807 #define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L 8808 //RCC_DEV1_EPF0_STRAP6 8809 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L 8810 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L 8811 #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L 8812 //RCC_DEV1_EPF0_STRAP13 8813 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL 8814 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L 8815 #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L 8816 //RCC_DEV1_EPF1_STRAP0 8817 #define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL 8818 #define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L 8819 #define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L 8820 #define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L 8821 #define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L 8822 #define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L 8823 #define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L 8824 //RCC_DEV1_EPF1_STRAP2 8825 #define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L 8826 #define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L 8827 #define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L 8828 #define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L 8829 #define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L 8830 #define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L 8831 #define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L 8832 #define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L 8833 #define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L 8834 //RCC_DEV1_EPF1_STRAP3 8835 #define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L 8836 #define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L 8837 #define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL 8838 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L 8839 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L 8840 #define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L 8841 #define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L 8842 #define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L 8843 #define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L 8844 #define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L 8845 //RCC_DEV1_EPF1_STRAP4 8846 #define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L 8847 #define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L 8848 #define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L 8849 #define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L 8850 #define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L 8851 #define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L 8852 //RCC_DEV1_EPF1_STRAP5 8853 #define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL 8854 //RCC_DEV1_EPF1_STRAP6 8855 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L 8856 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L 8857 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L 8858 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L 8859 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L 8860 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L 8861 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L 8862 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L 8863 #define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L 8864 //RCC_DEV1_EPF1_STRAP13 8865 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL 8866 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L 8867 #define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L 8868 //RCC_DEV1_EPF2_STRAP0 8869 #define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL 8870 #define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L 8871 #define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L 8872 #define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L 8873 #define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L 8874 #define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L 8875 #define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L 8876 //RCC_DEV1_EPF2_STRAP2 8877 #define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L 8878 #define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L 8879 #define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L 8880 #define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L 8881 #define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L 8882 #define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L 8883 #define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L 8884 #define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L 8885 #define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L 8886 //RCC_DEV1_EPF2_STRAP3 8887 #define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L 8888 #define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L 8889 #define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL 8890 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L 8891 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L 8892 #define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L 8893 #define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L 8894 #define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L 8895 #define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L 8896 #define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L 8897 //RCC_DEV1_EPF2_STRAP4 8898 #define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L 8899 #define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L 8900 #define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L 8901 #define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L 8902 #define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L 8903 #define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L 8904 //RCC_DEV1_EPF2_STRAP5 8905 #define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL 8906 //RCC_DEV1_EPF2_STRAP6 8907 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L 8908 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L 8909 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L 8910 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L 8911 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L 8912 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L 8913 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L 8914 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L 8915 #define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L 8916 //RCC_DEV1_EPF2_STRAP13 8917 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL 8918 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L 8919 #define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L 8920 8921 8922 // addressBlock: bif_rst_bif_rst_regblk 8923 //HARD_RST_CTRL 8924 #define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L 8925 #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L 8926 #define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L 8927 #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L 8928 #define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L 8929 #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L 8930 #define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L 8931 #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L 8932 #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L 8933 #define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L 8934 #define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L 8935 #define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L 8936 //RSMU_SOFT_RST_CTRL 8937 #define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L 8938 #define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L 8939 #define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L 8940 #define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L 8941 #define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L 8942 #define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L 8943 #define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L 8944 #define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L 8945 #define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L 8946 #define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L 8947 #define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L 8948 #define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L 8949 //SELF_SOFT_RST 8950 #define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L 8951 #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L 8952 #define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L 8953 #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L 8954 #define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L 8955 #define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L 8956 #define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L 8957 #define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L 8958 #define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L 8959 #define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L 8960 #define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L 8961 #define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L 8962 #define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L 8963 //GFX_DRV_MODE1_RST_CTRL 8964 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L 8965 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L 8966 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L 8967 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L 8968 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L 8969 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L 8970 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L 8971 #define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L 8972 //BIF_RST_MISC_CTRL 8973 #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L 8974 #define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL 8975 #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L 8976 #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L 8977 #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L 8978 #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L 8979 #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L 8980 #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L 8981 #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L 8982 #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L 8983 #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L 8984 #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L 8985 #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L 8986 //BIF_RST_MISC_CTRL2 8987 #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L 8988 #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L 8989 #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L 8990 #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L 8991 //BIF_RST_MISC_CTRL3 8992 #define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL 8993 #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L 8994 #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L 8995 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L 8996 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L 8997 #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L 8998 //BIF_RST_GFXVF_FLR_IDLE 8999 #define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L 9000 #define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L 9001 #define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L 9002 #define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L 9003 #define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L 9004 #define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L 9005 #define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L 9006 #define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L 9007 #define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L 9008 #define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L 9009 #define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L 9010 #define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L 9011 #define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L 9012 #define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L 9013 #define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L 9014 #define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L 9015 #define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L 9016 //DEV0_PF0_FLR_RST_CTRL 9017 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9018 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9019 #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9020 #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9021 #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9022 #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L 9023 #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L 9024 #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L 9025 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L 9026 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L 9027 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L 9028 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L 9029 #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L 9030 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L 9031 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L 9032 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L 9033 #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L 9034 #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9035 #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9036 #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9037 #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9038 //DEV0_PF1_FLR_RST_CTRL 9039 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9040 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9041 #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9042 #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9043 #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9044 #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9045 #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9046 #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9047 #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9048 //DEV0_PF2_FLR_RST_CTRL 9049 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9050 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9051 #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9052 #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9053 #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9054 #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9055 #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9056 #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9057 #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9058 //DEV0_PF3_FLR_RST_CTRL 9059 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9060 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9061 #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9062 #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9063 #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9064 #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9065 #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9066 #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9067 #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9068 //DEV0_PF4_FLR_RST_CTRL 9069 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9070 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9071 #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9072 #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9073 #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9074 #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9075 #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9076 #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9077 #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9078 //DEV0_PF5_FLR_RST_CTRL 9079 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9080 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9081 #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9082 #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9083 #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9084 #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9085 #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9086 #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9087 #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9088 //DEV0_PF6_FLR_RST_CTRL 9089 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9090 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9091 #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9092 #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9093 #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9094 #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9095 #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9096 #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9097 #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9098 //DEV0_PF7_FLR_RST_CTRL 9099 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9100 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9101 #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9102 #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9103 #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9104 #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9105 #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9106 #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9107 #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9108 //BIF_INST_RESET_INTR_STS 9109 #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L 9110 #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L 9111 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L 9112 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L 9113 #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L 9114 //BIF_PF_FLR_INTR_STS 9115 #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L 9116 #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L 9117 #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L 9118 #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L 9119 #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L 9120 #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L 9121 #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L 9122 #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L 9123 //BIF_D3HOTD0_INTR_STS 9124 #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L 9125 #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L 9126 #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L 9127 #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L 9128 #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L 9129 #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L 9130 #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L 9131 #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L 9132 //BIF_POWER_INTR_STS 9133 #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L 9134 #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L 9135 //BIF_PF_DSTATE_INTR_STS 9136 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L 9137 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L 9138 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L 9139 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L 9140 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L 9141 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L 9142 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L 9143 #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L 9144 //BIF_PF0_VF_FLR_INTR_STS 9145 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L 9146 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L 9147 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L 9148 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L 9149 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L 9150 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L 9151 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L 9152 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L 9153 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L 9154 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L 9155 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L 9156 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L 9157 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L 9158 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L 9159 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L 9160 #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L 9161 #define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L 9162 //BIF_INST_RESET_INTR_MASK 9163 #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L 9164 #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L 9165 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L 9166 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L 9167 #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L 9168 //BIF_PF_FLR_INTR_MASK 9169 #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L 9170 #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L 9171 #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L 9172 #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L 9173 #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L 9174 #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L 9175 #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L 9176 #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L 9177 //BIF_D3HOTD0_INTR_MASK 9178 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L 9179 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L 9180 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L 9181 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L 9182 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L 9183 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L 9184 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L 9185 #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L 9186 //BIF_POWER_INTR_MASK 9187 #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L 9188 #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L 9189 //BIF_PF_DSTATE_INTR_MASK 9190 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L 9191 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L 9192 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L 9193 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L 9194 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L 9195 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L 9196 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L 9197 #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L 9198 //BIF_PF0_VF_FLR_INTR_MASK 9199 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L 9200 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L 9201 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L 9202 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L 9203 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L 9204 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L 9205 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L 9206 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L 9207 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L 9208 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L 9209 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L 9210 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L 9211 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L 9212 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L 9213 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L 9214 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L 9215 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L 9216 //BIF_PF_FLR_RST 9217 #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L 9218 #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L 9219 #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L 9220 #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L 9221 #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L 9222 #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L 9223 #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L 9224 #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L 9225 //BIF_PF0_VF_FLR_RST 9226 #define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L 9227 #define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L 9228 #define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L 9229 #define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L 9230 #define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L 9231 #define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L 9232 #define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L 9233 #define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L 9234 #define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L 9235 #define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L 9236 #define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L 9237 #define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L 9238 #define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L 9239 #define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L 9240 #define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L 9241 #define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L 9242 #define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L 9243 //BIF_DEV0_PF0_DSTATE_VALUE 9244 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L 9245 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9246 #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L 9247 //BIF_DEV0_PF1_DSTATE_VALUE 9248 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L 9249 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9250 #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L 9251 //BIF_DEV0_PF2_DSTATE_VALUE 9252 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L 9253 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9254 #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L 9255 //BIF_DEV0_PF3_DSTATE_VALUE 9256 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L 9257 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9258 #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L 9259 //BIF_DEV0_PF4_DSTATE_VALUE 9260 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L 9261 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9262 #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L 9263 //BIF_DEV0_PF5_DSTATE_VALUE 9264 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L 9265 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9266 #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L 9267 //BIF_DEV0_PF6_DSTATE_VALUE 9268 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L 9269 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9270 #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L 9271 //BIF_DEV0_PF7_DSTATE_VALUE 9272 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L 9273 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9274 #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L 9275 //DEV0_PF0_D3HOTD0_RST_CTRL 9276 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9277 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9278 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9279 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9280 #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9281 //DEV0_PF1_D3HOTD0_RST_CTRL 9282 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9283 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9284 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9285 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9286 #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9287 //DEV0_PF2_D3HOTD0_RST_CTRL 9288 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9289 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9290 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9291 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9292 #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9293 //DEV0_PF3_D3HOTD0_RST_CTRL 9294 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9295 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9296 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9297 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9298 #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9299 //DEV0_PF4_D3HOTD0_RST_CTRL 9300 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9301 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9302 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9303 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9304 #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9305 //DEV0_PF5_D3HOTD0_RST_CTRL 9306 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9307 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9308 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9309 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9310 #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9311 //DEV0_PF6_D3HOTD0_RST_CTRL 9312 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9313 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9314 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9315 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9316 #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9317 //DEV0_PF7_D3HOTD0_RST_CTRL 9318 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9319 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9320 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9321 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9322 #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9323 //BIF_PORT0_DSTATE_VALUE 9324 #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L 9325 #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L 9326 9327 9328 // addressBlock: bif_misc_bif_misc_regblk 9329 //MISC_SCRATCH 9330 #define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL 9331 //INTR_LINE_POLARITY 9332 #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL 9333 //INTR_LINE_ENABLE 9334 #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL 9335 //OUTSTANDING_VC_ALLOC 9336 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L 9337 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL 9338 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L 9339 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L 9340 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L 9341 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L 9342 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L 9343 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L 9344 #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L 9345 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L 9346 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L 9347 #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L 9348 //BIFC_MISC_CTRL0 9349 #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L 9350 #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L 9351 #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L 9352 #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L 9353 #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L 9354 #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L 9355 #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L 9356 #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L 9357 #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L 9358 #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L 9359 #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L 9360 #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L 9361 #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L 9362 //BIFC_MISC_CTRL1 9363 #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L 9364 #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L 9365 #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L 9366 #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L 9367 #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L 9368 #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L 9369 #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L 9370 #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L 9371 #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L 9372 #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L 9373 #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L 9374 #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L 9375 #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L 9376 #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L 9377 #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L 9378 #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L 9379 #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L 9380 #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L 9381 //BIFC_BME_ERR_LOG 9382 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L 9383 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L 9384 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L 9385 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L 9386 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L 9387 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L 9388 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L 9389 #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L 9390 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L 9391 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L 9392 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L 9393 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L 9394 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L 9395 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L 9396 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L 9397 #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L 9398 //BIFC_RCCBIH_BME_ERR_LOG 9399 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L 9400 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L 9401 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L 9402 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L 9403 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L 9404 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L 9405 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L 9406 #define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L 9407 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L 9408 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L 9409 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L 9410 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L 9411 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L 9412 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L 9413 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L 9414 #define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L 9415 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 9416 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L 9417 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL 9418 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L 9419 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L 9420 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L 9421 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L 9422 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L 9423 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L 9424 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L 9425 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L 9426 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L 9427 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L 9428 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 9429 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L 9430 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL 9431 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L 9432 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L 9433 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L 9434 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L 9435 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L 9436 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L 9437 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L 9438 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L 9439 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L 9440 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L 9441 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 9442 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L 9443 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL 9444 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L 9445 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L 9446 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L 9447 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L 9448 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L 9449 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L 9450 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L 9451 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L 9452 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L 9453 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L 9454 //BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 9455 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L 9456 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL 9457 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L 9458 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L 9459 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L 9460 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L 9461 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L 9462 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L 9463 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L 9464 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L 9465 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L 9466 #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L 9467 //NBIF_VWIRE_CTRL 9468 #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L 9469 #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L 9470 #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L 9471 #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L 9472 //NBIF_SMN_VWR_VCHG_DIS_CTRL 9473 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L 9474 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L 9475 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L 9476 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L 9477 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L 9478 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L 9479 #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L 9480 //NBIF_SMN_VWR_VCHG_RST_CTRL0 9481 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L 9482 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L 9483 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L 9484 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L 9485 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L 9486 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L 9487 #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L 9488 //NBIF_SMN_VWR_VCHG_TRIG 9489 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L 9490 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L 9491 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L 9492 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L 9493 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L 9494 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L 9495 #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L 9496 //NBIF_SMN_VWR_WTRIG_CNTL 9497 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L 9498 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L 9499 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L 9500 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L 9501 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L 9502 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L 9503 #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L 9504 //NBIF_SMN_VWR_VCHG_DIS_CTRL_1 9505 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L 9506 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L 9507 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L 9508 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L 9509 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L 9510 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L 9511 #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L 9512 //NBIF_MGCG_CTRL 9513 #define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L 9514 #define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L 9515 #define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL 9516 //NBIF_DS_CTRL_LCLK 9517 #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L 9518 #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L 9519 //SMN_MST_CNTL0 9520 #define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L 9521 #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L 9522 #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L 9523 #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L 9524 #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L 9525 #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L 9526 #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L 9527 #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L 9528 #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L 9529 //SMN_MST_EP_CNTL1 9530 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L 9531 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L 9532 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L 9533 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L 9534 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L 9535 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L 9536 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L 9537 #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L 9538 //SMN_MST_EP_CNTL2 9539 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L 9540 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L 9541 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L 9542 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L 9543 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L 9544 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L 9545 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L 9546 #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L 9547 //NBIF_SDP_VWR_VCHG_DIS_CTRL 9548 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L 9549 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L 9550 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L 9551 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L 9552 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L 9553 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L 9554 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L 9555 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L 9556 #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L 9557 //NBIF_SDP_VWR_VCHG_RST_CTRL0 9558 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L 9559 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L 9560 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L 9561 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L 9562 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L 9563 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L 9564 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L 9565 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L 9566 #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L 9567 //NBIF_SDP_VWR_VCHG_RST_CTRL1 9568 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L 9569 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L 9570 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L 9571 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L 9572 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L 9573 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L 9574 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L 9575 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L 9576 #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L 9577 //NBIF_SDP_VWR_VCHG_TRIG 9578 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L 9579 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L 9580 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L 9581 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L 9582 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L 9583 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L 9584 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L 9585 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L 9586 #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L 9587 //BME_DUMMY_CNTL_0 9588 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L 9589 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL 9590 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L 9591 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L 9592 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L 9593 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L 9594 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L 9595 #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L 9596 //BIFC_THT_CNTL 9597 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL 9598 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L 9599 #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L 9600 //BIFC_HSTARB_CNTL 9601 #define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L 9602 //BIFC_GSI_CNTL 9603 #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L 9604 #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL 9605 #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L 9606 #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L 9607 #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L 9608 #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L 9609 #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L 9610 #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L 9611 #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L 9612 //BIFC_PCIEFUNC_CNTL 9613 #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL 9614 #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L 9615 //BIFC_SDP_CNTL_0 9616 #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL 9617 #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L 9618 #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L 9619 #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L 9620 //BIFC_PERF_CNTL_0 9621 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L 9622 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L 9623 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L 9624 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L 9625 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L 9626 #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L 9627 //BIFC_PERF_CNTL_1 9628 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L 9629 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L 9630 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L 9631 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L 9632 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L 9633 #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L 9634 //BIFC_PERF_CNT_MMIO_RD 9635 #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL 9636 //BIFC_PERF_CNT_MMIO_WR 9637 #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL 9638 //BIFC_PERF_CNT_DMA_RD 9639 #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL 9640 //BIFC_PERF_CNT_DMA_WR 9641 #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL 9642 //NBIF_REGIF_ERRSET_CTRL 9643 #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L 9644 //SMN_MST_EP_CNTL3 9645 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L 9646 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L 9647 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L 9648 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L 9649 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L 9650 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L 9651 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L 9652 #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L 9653 //SMN_MST_EP_CNTL4 9654 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L 9655 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L 9656 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L 9657 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L 9658 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L 9659 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L 9660 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L 9661 #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L 9662 //BIF_SELFRING_BUFFER_VID 9663 #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL 9664 #define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L 9665 //BIF_SELFRING_VECTOR_CNTL 9666 #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L 9667 9668 9669 // addressBlock: bif_ras_bif_ras_regblk 9670 //BIF_RAS_LEAF0_CTRL 9671 #define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L 9672 #define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9673 #define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L 9674 #define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L 9675 #define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9676 #define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9677 #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9678 #define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9679 #define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L 9680 #define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9681 #define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9682 #define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L 9683 //BIF_RAS_LEAF1_CTRL 9684 #define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L 9685 #define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9686 #define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L 9687 #define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L 9688 #define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9689 #define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9690 #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9691 #define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9692 #define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L 9693 #define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9694 #define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9695 #define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L 9696 //BIF_RAS_LEAF2_CTRL 9697 #define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L 9698 #define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9699 #define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L 9700 #define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L 9701 #define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9702 #define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9703 #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9704 #define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9705 #define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L 9706 #define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9707 #define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9708 #define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L 9709 //BIF_RAS_MISC_CTRL 9710 #define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L 9711 //BIF_IOHUB_RAS_IH_CNTL 9712 #define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L 9713 //BIF_RAS_VWR_FROM_IOHUB 9714 #define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L 9715 9716 9717 // addressBlock: rcc_pfc_amdgfx_RCCPFCDEC 9718 //RCC_PFC_LTR_CNTL 9719 #define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL 9720 #define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L 9721 #define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L 9722 #define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L 9723 #define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L 9724 #define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L 9725 //RCC_PFC_PME_RESTORE 9726 #define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L 9727 #define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L 9728 //RCC_PFC_STICKY_RESTORE_0 9729 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L 9730 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L 9731 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L 9732 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L 9733 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L 9734 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L 9735 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L 9736 #define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L 9737 //RCC_PFC_STICKY_RESTORE_1 9738 #define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL 9739 //RCC_PFC_STICKY_RESTORE_2 9740 #define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL 9741 //RCC_PFC_STICKY_RESTORE_3 9742 #define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL 9743 //RCC_PFC_STICKY_RESTORE_4 9744 #define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL 9745 //RCC_PFC_STICKY_RESTORE_5 9746 #define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL 9747 //RCC_PFC_AUXPWR_CNTL 9748 #define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L 9749 #define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L 9750 9751 9752 // addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC 9753 //RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 9754 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL 9755 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L 9756 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L 9757 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L 9758 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L 9759 #define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L 9760 //RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 9761 #define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L 9762 #define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L 9763 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 9764 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L 9765 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L 9766 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L 9767 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L 9768 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L 9769 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L 9770 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L 9771 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L 9772 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 9773 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL 9774 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 9775 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL 9776 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 9777 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL 9778 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 9779 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL 9780 //RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 9781 #define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL 9782 //RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 9783 #define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L 9784 #define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L 9785 9786 9787 // addressBlock: pciemsix_amdgfx_MSIXTDEC 9788 //PCIEMSIX_VECT0_ADDR_LO 9789 #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9790 //PCIEMSIX_VECT0_ADDR_HI 9791 #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9792 //PCIEMSIX_VECT0_MSG_DATA 9793 #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9794 //PCIEMSIX_VECT0_CONTROL 9795 #define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L 9796 //PCIEMSIX_VECT1_ADDR_LO 9797 #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9798 //PCIEMSIX_VECT1_ADDR_HI 9799 #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9800 //PCIEMSIX_VECT1_MSG_DATA 9801 #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9802 //PCIEMSIX_VECT1_CONTROL 9803 #define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L 9804 //PCIEMSIX_VECT2_ADDR_LO 9805 #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9806 //PCIEMSIX_VECT2_ADDR_HI 9807 #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9808 //PCIEMSIX_VECT2_MSG_DATA 9809 #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9810 //PCIEMSIX_VECT2_CONTROL 9811 #define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L 9812 //PCIEMSIX_VECT3_ADDR_LO 9813 #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9814 //PCIEMSIX_VECT3_ADDR_HI 9815 #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9816 //PCIEMSIX_VECT3_MSG_DATA 9817 #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9818 //PCIEMSIX_VECT3_CONTROL 9819 #define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L 9820 //PCIEMSIX_VECT4_ADDR_LO 9821 #define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9822 //PCIEMSIX_VECT4_ADDR_HI 9823 #define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9824 //PCIEMSIX_VECT4_MSG_DATA 9825 #define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9826 //PCIEMSIX_VECT4_CONTROL 9827 #define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L 9828 //PCIEMSIX_VECT5_ADDR_LO 9829 #define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9830 //PCIEMSIX_VECT5_ADDR_HI 9831 #define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9832 //PCIEMSIX_VECT5_MSG_DATA 9833 #define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9834 //PCIEMSIX_VECT5_CONTROL 9835 #define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L 9836 //PCIEMSIX_VECT6_ADDR_LO 9837 #define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9838 //PCIEMSIX_VECT6_ADDR_HI 9839 #define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9840 //PCIEMSIX_VECT6_MSG_DATA 9841 #define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9842 //PCIEMSIX_VECT6_CONTROL 9843 #define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L 9844 //PCIEMSIX_VECT7_ADDR_LO 9845 #define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9846 //PCIEMSIX_VECT7_ADDR_HI 9847 #define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9848 //PCIEMSIX_VECT7_MSG_DATA 9849 #define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9850 //PCIEMSIX_VECT7_CONTROL 9851 #define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L 9852 //PCIEMSIX_VECT8_ADDR_LO 9853 #define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9854 //PCIEMSIX_VECT8_ADDR_HI 9855 #define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9856 //PCIEMSIX_VECT8_MSG_DATA 9857 #define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9858 //PCIEMSIX_VECT8_CONTROL 9859 #define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L 9860 //PCIEMSIX_VECT9_ADDR_LO 9861 #define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9862 //PCIEMSIX_VECT9_ADDR_HI 9863 #define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9864 //PCIEMSIX_VECT9_MSG_DATA 9865 #define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9866 //PCIEMSIX_VECT9_CONTROL 9867 #define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L 9868 //PCIEMSIX_VECT10_ADDR_LO 9869 #define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9870 //PCIEMSIX_VECT10_ADDR_HI 9871 #define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9872 //PCIEMSIX_VECT10_MSG_DATA 9873 #define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9874 //PCIEMSIX_VECT10_CONTROL 9875 #define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L 9876 //PCIEMSIX_VECT11_ADDR_LO 9877 #define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9878 //PCIEMSIX_VECT11_ADDR_HI 9879 #define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9880 //PCIEMSIX_VECT11_MSG_DATA 9881 #define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9882 //PCIEMSIX_VECT11_CONTROL 9883 #define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L 9884 //PCIEMSIX_VECT12_ADDR_LO 9885 #define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9886 //PCIEMSIX_VECT12_ADDR_HI 9887 #define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9888 //PCIEMSIX_VECT12_MSG_DATA 9889 #define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9890 //PCIEMSIX_VECT12_CONTROL 9891 #define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L 9892 //PCIEMSIX_VECT13_ADDR_LO 9893 #define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9894 //PCIEMSIX_VECT13_ADDR_HI 9895 #define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9896 //PCIEMSIX_VECT13_MSG_DATA 9897 #define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9898 //PCIEMSIX_VECT13_CONTROL 9899 #define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L 9900 //PCIEMSIX_VECT14_ADDR_LO 9901 #define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9902 //PCIEMSIX_VECT14_ADDR_HI 9903 #define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9904 //PCIEMSIX_VECT14_MSG_DATA 9905 #define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9906 //PCIEMSIX_VECT14_CONTROL 9907 #define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L 9908 //PCIEMSIX_VECT15_ADDR_LO 9909 #define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9910 //PCIEMSIX_VECT15_ADDR_HI 9911 #define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9912 //PCIEMSIX_VECT15_MSG_DATA 9913 #define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9914 //PCIEMSIX_VECT15_CONTROL 9915 #define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L 9916 //PCIEMSIX_VECT16_ADDR_LO 9917 #define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9918 //PCIEMSIX_VECT16_ADDR_HI 9919 #define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9920 //PCIEMSIX_VECT16_MSG_DATA 9921 #define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9922 //PCIEMSIX_VECT16_CONTROL 9923 #define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L 9924 //PCIEMSIX_VECT17_ADDR_LO 9925 #define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9926 //PCIEMSIX_VECT17_ADDR_HI 9927 #define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9928 //PCIEMSIX_VECT17_MSG_DATA 9929 #define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9930 //PCIEMSIX_VECT17_CONTROL 9931 #define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L 9932 //PCIEMSIX_VECT18_ADDR_LO 9933 #define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9934 //PCIEMSIX_VECT18_ADDR_HI 9935 #define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9936 //PCIEMSIX_VECT18_MSG_DATA 9937 #define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9938 //PCIEMSIX_VECT18_CONTROL 9939 #define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L 9940 //PCIEMSIX_VECT19_ADDR_LO 9941 #define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9942 //PCIEMSIX_VECT19_ADDR_HI 9943 #define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9944 //PCIEMSIX_VECT19_MSG_DATA 9945 #define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9946 //PCIEMSIX_VECT19_CONTROL 9947 #define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L 9948 //PCIEMSIX_VECT20_ADDR_LO 9949 #define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9950 //PCIEMSIX_VECT20_ADDR_HI 9951 #define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9952 //PCIEMSIX_VECT20_MSG_DATA 9953 #define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9954 //PCIEMSIX_VECT20_CONTROL 9955 #define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L 9956 //PCIEMSIX_VECT21_ADDR_LO 9957 #define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9958 //PCIEMSIX_VECT21_ADDR_HI 9959 #define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9960 //PCIEMSIX_VECT21_MSG_DATA 9961 #define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9962 //PCIEMSIX_VECT21_CONTROL 9963 #define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L 9964 //PCIEMSIX_VECT22_ADDR_LO 9965 #define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9966 //PCIEMSIX_VECT22_ADDR_HI 9967 #define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9968 //PCIEMSIX_VECT22_MSG_DATA 9969 #define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9970 //PCIEMSIX_VECT22_CONTROL 9971 #define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L 9972 //PCIEMSIX_VECT23_ADDR_LO 9973 #define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9974 //PCIEMSIX_VECT23_ADDR_HI 9975 #define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9976 //PCIEMSIX_VECT23_MSG_DATA 9977 #define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9978 //PCIEMSIX_VECT23_CONTROL 9979 #define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L 9980 //PCIEMSIX_VECT24_ADDR_LO 9981 #define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9982 //PCIEMSIX_VECT24_ADDR_HI 9983 #define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9984 //PCIEMSIX_VECT24_MSG_DATA 9985 #define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9986 //PCIEMSIX_VECT24_CONTROL 9987 #define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L 9988 //PCIEMSIX_VECT25_ADDR_LO 9989 #define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9990 //PCIEMSIX_VECT25_ADDR_HI 9991 #define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9992 //PCIEMSIX_VECT25_MSG_DATA 9993 #define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9994 //PCIEMSIX_VECT25_CONTROL 9995 #define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L 9996 //PCIEMSIX_VECT26_ADDR_LO 9997 #define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9998 //PCIEMSIX_VECT26_ADDR_HI 9999 #define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10000 //PCIEMSIX_VECT26_MSG_DATA 10001 #define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10002 //PCIEMSIX_VECT26_CONTROL 10003 #define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L 10004 //PCIEMSIX_VECT27_ADDR_LO 10005 #define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10006 //PCIEMSIX_VECT27_ADDR_HI 10007 #define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10008 //PCIEMSIX_VECT27_MSG_DATA 10009 #define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10010 //PCIEMSIX_VECT27_CONTROL 10011 #define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L 10012 //PCIEMSIX_VECT28_ADDR_LO 10013 #define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10014 //PCIEMSIX_VECT28_ADDR_HI 10015 #define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10016 //PCIEMSIX_VECT28_MSG_DATA 10017 #define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10018 //PCIEMSIX_VECT28_CONTROL 10019 #define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L 10020 //PCIEMSIX_VECT29_ADDR_LO 10021 #define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10022 //PCIEMSIX_VECT29_ADDR_HI 10023 #define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10024 //PCIEMSIX_VECT29_MSG_DATA 10025 #define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10026 //PCIEMSIX_VECT29_CONTROL 10027 #define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L 10028 //PCIEMSIX_VECT30_ADDR_LO 10029 #define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10030 //PCIEMSIX_VECT30_ADDR_HI 10031 #define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10032 //PCIEMSIX_VECT30_MSG_DATA 10033 #define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10034 //PCIEMSIX_VECT30_CONTROL 10035 #define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L 10036 //PCIEMSIX_VECT31_ADDR_LO 10037 #define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10038 //PCIEMSIX_VECT31_ADDR_HI 10039 #define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10040 //PCIEMSIX_VECT31_MSG_DATA 10041 #define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10042 //PCIEMSIX_VECT31_CONTROL 10043 #define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L 10044 10045 10046 // addressBlock: pciemsix_amdgfx_MSIXPDEC 10047 //PCIEMSIX_PBA 10048 #define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL 10049 10050 10051 // addressBlock: syshub_mmreg_ind_syshubind 10052 //SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 10053 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 10054 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 10055 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 10056 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 10057 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 10058 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 10059 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 10060 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 10061 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 10062 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 10063 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 10064 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 10065 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 10066 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 10067 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 10068 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 10069 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 10070 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L 10071 //SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 10072 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL 10073 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 10074 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L 10075 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L 10076 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L 10077 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L 10078 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L 10079 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 10080 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L 10081 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L 10082 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L 10083 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L 10084 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L 10085 //SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 10086 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10087 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10088 #define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10089 //SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 10090 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10091 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10092 #define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10093 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 10094 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10095 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10096 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10097 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10098 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10099 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10100 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 10101 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10102 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10103 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10104 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10105 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10106 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10107 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 10108 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10109 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10110 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10111 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10112 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10113 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10114 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 10115 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10116 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10117 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10118 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10119 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10120 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10121 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 10122 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10123 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10124 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10125 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10126 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10127 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10128 //SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 10129 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10130 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10131 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10132 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10133 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10134 #define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10135 //SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 10136 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10137 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10138 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10139 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10140 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10141 #define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10142 //SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 10143 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10144 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10145 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10146 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10147 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10148 #define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10149 //SYSHUBMMREGIND_SYSHUB_CG_CNTL 10150 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L 10151 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L 10152 #define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L 10153 //SYSHUBMMREGIND_SYSHUB_TRANS_IDLE 10154 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L 10155 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L 10156 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L 10157 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L 10158 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L 10159 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L 10160 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L 10161 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L 10162 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L 10163 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L 10164 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L 10165 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L 10166 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L 10167 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L 10168 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L 10169 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L 10170 #define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L 10171 //SYSHUBMMREGIND_SYSHUB_HP_TIMER 10172 #define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL 10173 //SYSHUBMMREGIND_SYSHUB_SCRATCH 10174 #define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL 10175 //SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 10176 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 10177 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 10178 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 10179 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 10180 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 10181 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 10182 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 10183 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 10184 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 10185 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 10186 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 10187 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 10188 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 10189 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 10190 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 10191 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 10192 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 10193 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L 10194 //SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 10195 #define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL 10196 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 10197 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L 10198 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L 10199 //SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 10200 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L 10201 #define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L 10202 //SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 10203 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10204 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10205 #define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10206 //SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 10207 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10208 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10209 #define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10210 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 10211 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10212 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10213 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10214 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10215 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10216 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10217 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 10218 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10219 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10220 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10221 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10222 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10223 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10224 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 10225 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10226 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10227 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10228 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10229 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10230 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10231 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 10232 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10233 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10234 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10235 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10236 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10237 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10238 //SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 10239 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10240 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10241 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10242 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10243 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10244 #define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10245 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 10246 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10247 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10248 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10249 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10250 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10251 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10252 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 10253 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10254 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10255 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10256 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10257 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10258 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10259 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 10260 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10261 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10262 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10263 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10264 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10265 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10266 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 10267 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10268 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10269 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10270 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10271 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10272 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10273 //SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 10274 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10275 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10276 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10277 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10278 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10279 #define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10280 10281 #endif 10282