// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2012-2020 ASPEED Technology Inc. * * Copyright 2016 Google, Inc */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "sdram_phy_ast2600.h" #define AST2600_SDRAMMC_FPGA #ifdef AST2600_SDRAMMC_FPGA /* mode register settings for FPGA are fixed */ #define DDR4_MR01_MODE 0x03010100 #define DDR4_MR23_MODE 0x00000000 #define DDR4_MR45_MODE 0x04C00000 #define DDR4_MR6_MODE 0x00000050 #define DDR4_TRFC 0x17263434 /* FPGA need for an additional initialization procedure: search read window */ #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) #define SEARCH_RDWIN_PTRN_0 0x12345678 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 #else /* mode register setting for real chip are derived from the model GDDR4-1600 */ #define DDR4_MR01_MODE 0x03010510 #define DDR4_MR23_MODE 0x00000000 #define DDR4_MR45_MODE 0x04000000 #define DDR4_MR6_MODE 0x00000400 #define DDR4_TRFC 0x467299f1 #endif /* end of "#ifdef AST2600_SDRAMMC_FPGA" */ #define SDRAM_SIZE_1KB (1024U) #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) DECLARE_GLOBAL_DATA_PTR; /* * Bandwidth configuration parameters for different SDRAM requests. * These are hardcoded settings taken from Aspeed SDK. */ #ifdef AST2600_SDRAMMC_FPGA static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 0x00000140}; static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 0x88888888}; #else static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 0x00001240}; static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 0x44444444}; #endif struct dram_info { struct ram_info info; struct clk ddr_clk; struct ast2600_sdrammc_regs *regs; void __iomem *scu; struct ast2600_ddr_phy *phy; void __iomem *phy_setting; void __iomem *phy_status; ulong clock_rate; }; static void ast2600_sdramphy_kick_training(struct dram_info *info) { #ifndef AST2600_SDRAMMC_FPGA struct ast2600_sdrammc_regs *regs = info->regs; u32 mask = SDRAM_PHYCTRL0_INIT | SDRAM_PHYCTRL0_PLL_LOCKED; u32 data; writel(0, ®s->phy_ctrl[0]); udelay(2); writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); /* wait for (PLL_LOCKED == 1) and (INIT == 0) */ do { data = readl(®s->phy_ctrl[0]) & mask; } while (SDRAM_PHYCTRL0_PLL_LOCKED != data); #endif } /** * @brief load DDR-PHY configurations table to the PHY registers * @param[in] p_tbl - pointer to the configuration table * @param[in] info - pointer to the DRAM info struct */ static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) { #ifndef AST2600_SDRAMMC_FPGA u32 reg_base = (u32)info->phy_setting; u32 addr = p_tbl[0]; u32 data; int i = 1; debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, addr); /* load PHY configuration table into PHY-setting registers */ while (1) { if (addr < reg_base) { debug("invalid DDR-PHY addr: 0x%08x\n", addr); break; } data = p_tbl[i++]; if (DDR_PHY_TBL_END == data) { break; } else if (DDR_PHY_TBL_CHG_ADDR == data) { addr = p_tbl[i++]; } else { writel(data, addr); addr += 4; } } #endif } static void ast2600_sdramphy_show_status(struct dram_info *info) { #ifndef AST2600_SDRAMMC_FPGA u32 value; u32 reg_base = (u32)info->phy_status; debug("%s:reg base = 0x%08x\n", __func__, reg_base); value = readl(reg_base + 0x00); if (value & BIT(3)) { debug("initial PVT calibration fail\n"); } if (value & BIT(5)) { debug("runtime calibration fail\n"); } value = readl(reg_base + 0x30); debug("IO PU = 0x%02x\n", value & 0xff); debug("IO PD = 0x%02x\n", (value >> 16) & 0xff); value = readl(reg_base + 0x88); debug("PHY vref: 0x%02x_%02x\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0x90); debug("DDR vref: 0x%02x\n", value & 0x3f); value = readl(reg_base + 0x40); debug("MLB Gate training result: 0x%04x_%04x\n", value & 0xffff, (value >> 16) & 0xffff); value = readl(reg_base + 0x50); debug("MLB Gate pass window: 0x%04x_%04x\n", value & 0xffff, (value >> 16) & 0xffff); value = readl(reg_base + 0x60); debug("Rising edge Read Data Eye Training Result = 0x%x_%x\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0x68); debug("Rising edge Read Data Eye Training Pass Window = 0x%x_%x\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0xC0); debug("Falling edge Read Data Eye Training Result = 0x%x_%x\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0xC8); debug("Falling edge Read Data Eye Training Pass Window = 0x%x_%x\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0x74); debug("Write Data Eye fine Training Result = %X_%X\n", value & 0xff, (value >> 8) & 0xff); value = readl(reg_base + 0x7C); debug("Write Data Eye Training Pass Window = 0x%x_%x\n", value & 0xff, (value >> 8) & 0xff); #endif } /** * @brief SDRAM memory controller test mode with data-generation * @param[in] - info - pointer to the current dram_info * @param[in] - data_gen - data_gen index * @param[in] - mode - 0:single, 1:burst * @return - 0:success, others:fail */ static int ast2600_sdrammc_dg_test(struct dram_info *info, u32 data_gen, u32 mode) { u32 data; u32 mask; struct ast2600_sdrammc_regs *regs = info->regs; writel(0, ®s->ecc_test_ctrl); data = (data_gen << SDRAM_TEST_GEN_MODE_SHIFT) | SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN; if (mode) { data |= (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | SDRAM_TEST_MODE_RW); } else { data |= (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | SDRAM_TEST_MODE_WO | SDRAM_TEST_TWO_MODES); } writel(data, ®s->ecc_test_ctrl); mask = SDRAM_TEST_DONE | SDRAM_TEST_FAIL; do { data = readl(®s->ecc_test_ctrl) & mask; if (data & SDRAM_TEST_FAIL) { debug("%s %d fail\n", __func__, data_gen); return 1; } } while (!data); writel(0x00000000, ®s->ecc_test_ctrl); return 0; } static int ast2600_sdrammc_cbr_test(struct dram_info *info, u32 pattern) { struct ast2600_sdrammc_regs *regs = info->regs; int i; int ret = 0; writel((0xff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); writel(pattern, ®s->test_init_val); /* scan all data-generation mode */ for (i = 0; i < 8; i++) { if (0 == ast2600_sdrammc_dg_test(info, i, 0)) { debug("sdrammc calibration test fail: single data " "mode\n"); ret = 1; break; } } for (i = 0; i < 8; i++) { if (0 == ast2600_sdrammc_dg_test(info, i, 1)) { debug( "sdrammc calibration test fail: burst data mode\n"); ret = 1; break; } } writel(0, ®s->ecc_test_ctrl); return ret; } #define MC_TEST_PATTERN_N 8 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; static int ast2600_sdrammc_test(struct dram_info *info) { int i; int ret; for (i = 0; i < MC_TEST_PATTERN_N; i++) { ret = ast2600_sdrammc_cbr_test(info, as2600_sdrammc_test_pattern[i]); if (ret) { return ret; } debug("%s: pass %d\n", __func__, i); } return ret; } static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) { u32 vga_hwconf; size_t vga_mem_size_base = 8 * 1024 * 1024; vga_hwconf = readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK >> SCU_HWSTRAP_VGAMEM_SHIFT; return vga_mem_size_base << vga_hwconf; } #ifdef AST2600_SDRAMMC_FPGA static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) { u32 data; u32 scu_base = (u32)info->scu; writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); do { data = readl(scu_base + AST_SCU_CONFIG); } while (!(data & 0x100)); writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); } static int ast2600_sdrammc_search_read_window(struct dram_info *info) { u32 pll, pll_min, pll_max, dat1, offset; u32 win = 0x03, gwin = 0, gwinsize = 0; u32 phy_setting = (u32)info->phy_setting; writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); while (gwin == 0) { while (!(win & 0x80)) { debug("Window = 0x%X\n", win); writel(win, phy_setting + 0x0000); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); while (dat1 == SEARCH_RDWIN_PTRN_SUM) { ast2600_sdrammc_fpga_set_pll(info); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); } pll_min = 0xfff; pll_max = 0x0; pll = 0; while (pll_max > 0 || pll < 256) { ast2600_sdrammc_fpga_set_pll(info); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); if (dat1 == SEARCH_RDWIN_PTRN_SUM) { if (pll_min > pll) { pll_min = pll; } if (pll_max < pll) { pll_max = pll; } debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); } else if (pll_max > 0) { pll_min = pll_max - pll_min; if (gwinsize < pll_min) { gwin = win; gwinsize = pll_min; } break; } pll += 1; } if (gwin != 0 && pll_max == 0) { break; } win = win << 1; } if (gwin == 0) { win = 0x7; } } debug("Set PLL Read Gating Window = %x\n", gwin); writel(gwin, phy_setting + 0x0000); debug("PLL Read Window training\n"); pll_min = 0xfff; pll_max = 0x0; debug("Search Window Start\n"); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); while (dat1 == SEARCH_RDWIN_PTRN_SUM) { ast2600_sdrammc_fpga_set_pll(info); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); } debug("Search Window Margin\n"); pll = 0; while (pll_max > 0 || pll < 256) { ast2600_sdrammc_fpga_set_pll(info); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); if (dat1 == SEARCH_RDWIN_PTRN_SUM) { if (pll_min > pll) { pll_min = pll; } if (pll_max < pll) { pll_max = pll; } debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); } else if (pll_max > 0 && (pll_max - pll_min) > 20) { break; } else if (pll_max > 0) { pll_min = 0xfff; pll_max = 0x0; } pll += 1; } if (pll_min < pll_max) { debug("PLL Read window = %d\n", (pll_max - pll_min)); offset = (pll_max - pll_min) >> 1; pll_min = 0xfff; pll = 0; while (pll < (pll_min + offset)) { ast2600_sdrammc_fpga_set_pll(info); dat1 = readl(SEARCH_RDWIN_ANCHOR_0); dat1 += readl(SEARCH_RDWIN_ANCHOR_1); if (dat1 == SEARCH_RDWIN_PTRN_SUM) { if (pll_min > pll) { pll_min = pll; } debug("%d\n", pll); } else { pll_min = 0xfff; pll_max = 0x0; } pll += 1; } return (1); } else { debug("PLL Read window training fail\n"); return (0); } } #endif /* end of "#ifdef AST2600_SDRAMMC_FPGA" */ /* * Find out RAM size and save it in dram_info * * The procedure is taken from Aspeed SDK */ static void ast2600_sdrammc_calc_size(struct dram_info *info) { /* The controller supports 256/512/1024/2048 MB ram */ size_t ram_size = SDRAM_MIN_SIZE; const int write_test_offset = 0x100000; u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_2048M; u32 refresh_timing_param = DDR4_TRFC; const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { writel(test_pattern, write_addr_base + (ram_size >> 1)); test_pattern = (test_pattern >> 4) | (test_pattern << 28); } /* One last write to overwrite all wrapped values */ writel(test_pattern, write_addr_base); /* Reset the pattern and see which value was really written */ test_pattern = 0xdeadbeef; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) break; --cap_param; refresh_timing_param >>= 8; test_pattern = (test_pattern >> 4) | (test_pattern << 28); } clrsetbits_le32(&info->regs->ac_timing[1], (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT)); info->info.base = CONFIG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), ((cap_param & SDRAM_CONF_CAP_MASK) << SDRAM_CONF_CAP_SHIFT)); } static int ast2600_sdrammc_init_ddr4(struct dram_info *info) { const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | MCR34_ODT_EN | MCR34_ODT_AUTO_ON | (0x1 << MCR34_ODT_EXT_SHIFT); #ifdef CONFIG_DUALX8_RAM setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8); #else setbits_le32(&info->regs->config, SDRAM_CONF_DDR4); #endif /* init SDRAM-PHY only on real chip */ ast2600_sdramphy_init(ast2600_sdramphy_config, info); ast2600_sdramphy_kick_training(info); writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), &info->regs->power_ctrl); writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, &info->regs->mode_setting_control); #ifdef AST2600_SDRAMMC_FPGA writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), &info->regs->refresh_timing); #else writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), &info->regs->refresh_timing); #endif /* wait self-refresh idle */ while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) ; #ifdef AST2600_SDRAMMC_FPGA writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | SDRAM_REFRESH_ZQCS_EN | (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), &info->regs->refresh_timing); #else writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | SDRAM_REFRESH_ZQCS_EN | (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), &info->regs->refresh_timing); #endif writel(power_ctrl, &info->regs->power_ctrl); #ifdef AST2600_SDRAMMC_FPGA /* toggle Vref training */ setbits_le32(&info->regs->mr6_mode_setting, 0x80); writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), &info->regs->mode_setting_control); clrbits_le32(&info->regs->mr6_mode_setting, 0x80); writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), &info->regs->mode_setting_control); #endif return 0; } static void ast2600_sdrammc_unlock(struct dram_info *info) { writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); while (!readl(&info->regs->protection_key)) ; } static void ast2600_sdrammc_lock(struct dram_info *info) { writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); while (readl(&info->regs->protection_key)) ; } static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) { int i; writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, ®s->arbitration_ctrl); writel(0xFFFFFFFF, ®s->req_limit_mask); for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); /* FIXME: the sample code does NOT match the datasheet */ writel(0x7FFFFFF, ®s->ecc_range_ctrl); writel(0, ®s->ecc_test_ctrl); writel(0, ®s->test_addr); writel(0, ®s->test_fail_dq_bit); writel(0, ®s->test_init_val); writel(0xFFFFFFFF, ®s->req_input_ctrl); writel(0, ®s->req_high_pri_ctrl); #ifdef AST2600_SDRAMMC_FPGA //writel(0xFF, 0x1e6e0100); #endif udelay(500); /* set capacity to the max size */ clrsetbits_le32(®s->config, SDRAM_CONF_CAP_MASK, SDRAM_CONF_CAP_2048M); /* load controller setting */ for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) writel(ddr4_ac_timing[i], ®s->ac_timing[i]); writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); } static int ast2600_sdrammc_probe(struct udevice *dev) { //struct reset_ctl reset_ctl; struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); struct ast2600_sdrammc_regs *regs = priv->regs; struct udevice *clk_dev; int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); if (ret) { debug("DDR:No CLK\n"); return ret; } /* find SCU base address from clock device */ ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), &clk_dev); if (ret) { debug("clock device not defined\n"); return ret; } priv->scu = devfdt_get_addr_ptr(clk_dev); if (IS_ERR(priv->scu)) { debug("%s(): can't get SCU\n", __func__); return PTR_ERR(priv->scu); } clk_set_rate(&priv->ddr_clk, priv->clock_rate); #if 0 /* FIXME: enable the following code if reset-driver is ready */ ret = reset_get_by_index(dev, 0, &reset_ctl); if (ret) { debug("%s(): Failed to get reset signal\n", __func__); return ret; } ret = reset_assert(&reset_ctl); if (ret) { debug("%s(): SDRAM reset failed: %u\n", __func__, ret); return ret; } #endif ast2600_sdrammc_unlock(priv); ast2600_sdrammc_common_init(regs); if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) { debug("Unsupported SDRAM type: DDR3\n"); return -EINVAL; } else { ast2600_sdrammc_init_ddr4(priv); } #ifdef AST2600_SDRAMMC_FPGA ast2600_sdrammc_search_read_window(priv); #endif ast2600_sdramphy_show_status(priv); ast2600_sdrammc_calc_size(priv); ast2600_sdrammc_test(priv); clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); ast2600_sdrammc_lock(priv); return 0; } static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); struct regmap *map; int ret; ret = regmap_init_mem(dev_ofnode(dev), &map); if (ret) return ret; priv->regs = regmap_get_range(map, 0); priv->phy_setting = regmap_get_range(map, 1); priv->phy_status = regmap_get_range(map, 2); priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock-frequency", 0); if (!priv->clock_rate) { debug("DDR Clock Rate not defined\n"); return -EINVAL; } return 0; } static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) { struct dram_info *priv = dev_get_priv(dev); *info = priv->info; return 0; } static struct ram_ops ast2600_sdrammc_ops = { .get_info = ast2600_sdrammc_get_info, }; static const struct udevice_id ast2600_sdrammc_ids[] = { { .compatible = "aspeed,ast2600-sdrammc" }, { } }; U_BOOT_DRIVER(sdrammc_ast2600) = { .name = "aspeed_ast2600_sdrammc", .id = UCLASS_RAM, .of_match = ast2600_sdrammc_ids, .ops = &ast2600_sdrammc_ops, .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, .probe = ast2600_sdrammc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), };