// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Stefan Roese * * Derived from drivers/mtd/nand/spi/micron.c * Copyright (c) 2016-2017 Micron Technology, Inc. */ #ifndef __UBOOT__ #include #include #endif #include #define SPINAND_MFR_GIGADEVICE 0xc8 #define GIGADEVICE_STATUS_ECC_MASK GENMASK(5, 4) #define GIGADEVICE_STATUS_ECC_NO_BITFLIPS (0 << 4) #define GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS (1 << 4) #define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4) static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); static SPINAND_OP_VARIANTS(write_cache_variants, SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), SPINAND_PROG_LOAD(true, 0, NULL, 0)); static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section) return -ERANGE; region->offset = 64; region->length = 64; return 0; } static int gd5f1gq4u_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { if (section) return -ERANGE; /* Reserve 2 bytes for the BBM. */ region->offset = 2; region->length = 62; return 0; } static const struct mtd_ooblayout_ops gd5f1gq4u_ooblayout = { .ecc = gd5f1gq4u_ooblayout_ecc, .free = gd5f1gq4u_ooblayout_free, }; static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand, u8 status) { if (status) debug("%s (%d): status=%02x\n", __func__, __LINE__, status); switch (status & GIGADEVICE_STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: return 0; case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS: return 7; case GIGADEVICE_STATUS_ECC_8_BITFLIPS: return 8; case STATUS_ECC_UNCOR_ERROR: return -EBADMSG; default: break; } return -EINVAL; } static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_INFO("GD5F1GQ4UC", 0xd1, NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 2048), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), 0, SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, gd5f1gq4u_ecc_get_status)), }; static int gigadevice_spinand_detect(struct spinand_device *spinand) { u8 *id = spinand->id.data; int ret; /* * Gigadevice SPI NAND read ID need a dummy byte, * so the first byte in raw_id is dummy. */ if (id[1] != SPINAND_MFR_GIGADEVICE) return 0; ret = spinand_match_and_init(spinand, gigadevice_spinand_table, ARRAY_SIZE(gigadevice_spinand_table), id[2]); if (ret) return ret; return 1; } static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { .detect = gigadevice_spinand_detect, }; const struct spinand_manufacturer gigadevice_spinand_manufacturer = { .id = SPINAND_MFR_GIGADEVICE, .name = "GigaDevice", .ops = &gigadevice_spinand_manuf_ops, };