/* * Copyright (C) 2014 Soeren Moch <smoch@web.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <asm/errno.h> #include <asm/gpio.h> #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/sata.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/video.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <i2c.h> DECLARE_GLOBAL_DATA_PTR; #define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) #ifdef CONFIG_SYS_I2C /* I2C1, SGTL5000 */ static struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, .gp = IMX_GPIO_NR(5, 27) }, .sda = { .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, .gp = IMX_GPIO_NR(5, 26) } }; /* I2C2 HDMI */ static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, .gp = IMX_GPIO_NR(4, 12) }, .sda = { .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, .gp = IMX_GPIO_NR(4, 13) } }; /* I2C3, CON11, DS1307, PCIe_SMB */ static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, .gp = IMX_GPIO_NR(1, 3) }, .sda = { .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, .gp = IMX_GPIO_NR(1, 6) } }; #endif /* CONFIG_SYS_I2C */ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const uart2_pads[] = { MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8035 PHY Reset */ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static iomux_v3_cfg_t const pcie_pads[] = { /* W_DISABLE# */ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* PERST# */ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), }; int dram_init(void) { gd->ram_size = 2048ul * 1024 * 1024; return 0; } static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset AR8035 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); udelay(500); gpio_set_value(IMX_GPIO_NR(1, 25), 1); } static void setup_pcie(void) { imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); } static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } #ifdef CONFIG_FSL_ESDHC static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; static struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; switch (cfg->esdhc_base) { case USDHC2_BASE_ADDR: ret = !gpio_get_value(USDHC2_CD_GPIO); break; case USDHC3_BASE_ADDR: ret = !gpio_get_value(USDHC3_CD_GPIO); break; case USDHC4_BASE_ADDR: ret = 1; /* eMMC/uSDHC4 is always present */ break; } return ret; } int board_mmc_init(bd_t *bis) { /* * (U-Boot device node) (Physical Port) * mmc0 SD2 * mmc1 SD3 * mmc2 eMMC */ int i, ret; for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; case 1: imx_iomux_v3_setup_multiple_pads( usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); gpio_direction_input(USDHC3_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 2: imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); break; default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", i + 1, CONFIG_SYS_FSL_USDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); if (ret) return ret; } return 0; } /* set environment device to boot device when booting from SD */ int board_mmc_get_env_dev(int devno) { return devno - 1; } int board_mmc_get_env_part(int devno) { return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */ } #endif /* CONFIG_FSL_ESDHC */ #ifdef CONFIG_VIDEO_IPUV3 static void do_enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); } struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, .detect = detect_hdmi, .enable = do_enable_hdmi, .mode = { .name = "HDMI", /* 1024x768@60Hz (VESA)*/ .refresh = 60, .xres = 1024, .yres = 768, .pixclock = 15384, .left_margin = 160, .right_margin = 24, .upper_margin = 29, .lower_margin = 3, .hsync_len = 136, .vsync_len = 6, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays); static void setup_display(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; s32 timeout = 100000; enable_ipu_clock(); imx_setup_hdmi(); /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); writel(reg, &ccm->analog_pll_video); writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; writel(reg, &ccm->analog_pll_video); while (timeout--) if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) break; if (timeout < 0) printf("Warning: video pll lock timeout!\n"); reg = readl(&ccm->analog_pll_video); reg |= BM_ANADIG_PLL_VIDEO_ENABLE; reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; writel(reg, &ccm->analog_pll_video); /* gate ipu1_di0_clk */ reg = readl(&ccm->CCGR3); reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &ccm->CCGR3); /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ reg = readl(&ccm->chsccdr); reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); writel(reg, &ccm->chsccdr); /* enable ipu1_di0_clk */ reg = readl(&ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; writel(reg, &ccm->CCGR3); } #endif /* CONFIG_VIDEO_IPUV3 */ int board_eth_init(bd_t *bis) { setup_iomux_enet(); setup_pcie(); return cpu_eth_init(bis); } int board_early_init_f(void) { setup_iomux_uart(); return 0; } #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, /* 8 bit bus width */ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, {NULL, 0}, }; #endif #ifdef CONFIG_USB_EHCI_MX6 static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), }; #endif int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif #ifdef CONFIG_SYS_I2C setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); #endif #ifdef CONFIG_DWC_AHSATA setup_sata(); #endif #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif #ifdef CONFIG_USB_EHCI_MX6 imx_iomux_v3_setup_multiple_pads( usb_otg_pads, ARRAY_SIZE(usb_otg_pads)); #endif return 0; } int checkboard(void) { puts("Board: TBS2910 Matrix ARM mini PC\n"); return 0; }