/* * board/renesas/porter/porter.c * * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2015 Cogent Embedded, Inc. * * SPDX-License-Identifier: GPL-2.0 */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "qos.h" DECLARE_GLOBAL_DATA_PTR; #define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; u32 stc; /* Watchdog init */ writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra); /* CPU frequency setting. Set to 1.5GHz */ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); /* QoS */ qos_init(); } #define TMU0_MSTP125 BIT(25) #define SD2CKCR 0xE615026C #define SD_97500KHZ 0x7 int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* * SD0 clock is set to 97.5MHz by default. * Set SD2 to the 97.5MHz as well. */ writel(SD_97500KHZ, SD2CKCR); return 0; } int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { if (fdtdec_setup_memory_size() != 0) return -EINVAL; return 0; } int dram_init_banksize(void) { fdtdec_setup_memory_banksize(); return 0; } /* porter has KSZ8041RNLI */ #define PHY_CONTROL1 0x1E #define PHY_LED_MODE 0xC0000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); ret &= ~PHY_LED_MODE; ret |= PHY_LED_MODE_ACK; ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); return 0; } const struct rmobile_sysinfo sysinfo = { CONFIG_ARCH_RMOBILE_BOARD_STRING }; void reset_cpu(ulong addr) { u8 val; i2c_set_bus_num(2); /* PowerIC connected to ch2 */ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); }