/* * PPC-AG BG0900 board * * Copyright (C) 2013 Marek Vasut <marex@denx.de> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-mx28.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <linux/mii.h> #include <miiphy.h> #include <netdev.h> #include <errno.h> DECLARE_GLOBAL_DATA_PTR; /* * Functions */ int board_early_init_f(void) { /* IO0 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK0, 480000); /* IO1 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK1, 480000); /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); return 0; } int dram_init(void) { return mxs_dram_init(); } int board_init(void) { /* Adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; ret = cpu_eth_init(bis); /* BG0900 uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); /* Reset FEC PHYs */ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); udelay(200); gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { puts("FEC MXS: Unable to init FEC0\n"); return ret; } dev = eth_get_dev_by_name("FEC0"); if (!dev) { puts("FEC MXS: Unable to get FEC0 device entry\n"); return -EINVAL; } return ret; } #endif