if ARCH_ASPEED config SYS_ARCH default "arm" config SYS_SOC default "aspeed" config SYS_TEXT_BASE default 0x00000000 choice prompt "Aspeed SoC select" depends on ARCH_ASPEED default ASPEED_AST2500 config ASPEED_AST2400 bool "Support Aspeed AST2400 SoC" select CPU_ARM926EJS help The Aspeed AST2400 is a ARM-based SoC with arm926ejs CPU. It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" select CPU_ARM1176 select SUPPORT_SPL help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. config ASPEED_AST2600 bool "Support Aspeed AST2600 SoC" select CPU_V7A select CPU_V7_HAS_NONSEC select ARCH_SUPPORT_PSCI select SYS_ARCH_TIMER select SUPPORT_SPL select ENABLE_ARM_SOC_BOOT0_HOOK help The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. endchoice config ASPEED_ALLOW_DANGEROUS_BACKDOORS bool "Expose options enabling dangerous Aspeed hardware backdoors" help This option exposes configuration settings that create critical security vulnerabilities by enabling dangerous hardware backdoors in Aspeed BMCs. Enable it only if absolutely required for a specific system or for debugging during development. if ASPEED_ALLOW_DANGEROUS_BACKDOORS config ASPEED_ENABLE_SUPERIO bool "Enable built-in AST2x00 Super I/O hardware" depends on ASPEED_AST2400 || ASPEED_AST2500 help The Aspeed AST2400 and AST2500 include a built-in Super I/O device that is normally disabled; say Y here to enable it. WARNING: this has serious security implications: it grants the host read access to the BMC's entire address space. This should thus be left disabled unless required by a specific system. config ASPEED_ENABLE_DEBUG_UART bool "Enable AST2500 hardware debug UART" depends on ASPEED_AST2500 help The Aspeed AST2500 include a hardware-supported, UART-based debug interface that is normally disabled; say Y here to enable it. Note that this has security implications: the debug UART provides read/write access to the BMC's entire address space. This should thus be left disabled on production systems, but may be useful to enable for debugging during development. endif config ASPEED_PALLADIUM bool "Aspeed palladium for simulation" default n help Say Y here to enable palladium build for simulation. This is mainly for internal verification and investigation on HW design. If not sure, say N. config ASPEED_SSP_RERV_MEM hex "Reserve memory for SSP" default 0x0 help The size in bytes of reserve memory for ASPEED SoC SSP run. config ASPEED_DEFAULT_SPI_FREQUENCY bool "Using default SPI clock frequency" default n help Using default SPI clock frequency during early booting up progress. source "arch/arm/mach-aspeed/ast2400/Kconfig" source "arch/arm/mach-aspeed/ast2500/Kconfig" source "arch/arm/mach-aspeed/ast2600/Kconfig" endif