/* * ARMv7M CPU object * * Copyright (c) 2017 Linaro Ltd * Written by Peter Maydell * * This code is licensed under the GPL version 2 or later. */ #ifndef HW_ARM_ARMV7M_H #define HW_ARM_ARMV7M_H #include "hw/sysbus.h" #include "hw/intc/armv7m_nvic.h" #include "target/arm/idau.h" #define TYPE_BITBAND "ARM,bitband-memory" #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) typedef struct { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ AddressSpace source_as; MemoryRegion iomem; uint32_t base; MemoryRegion *source_memory; } BitBandState; #define TYPE_ARMV7M "armv7m" #define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M) #define ARMV7M_NUM_BITBANDS 2 /* ARMv7M container object. * + Unnamed GPIO input lines: external IRQ lines for the NVIC * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ * + Property "cpu-type": CPU type to instantiate * + Property "num-irq": number of external IRQ lines * + Property "memory": MemoryRegion defining the physical address space * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal * devices will be automatically layered on top of this view.) * + Property "idau": IDAU interface (forwarded to CPU object) * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO */ typedef struct ARMv7MState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ NVICState nvic; BitBandState bitband[ARMV7M_NUM_BITBANDS]; ARMCPU *cpu; /* MemoryRegion we pass to the CPU, with our devices layered on * top of the ones the board provides in board_memory. */ MemoryRegion container; /* Properties */ char *cpu_type; /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ MemoryRegion *board_memory; Object *idau; uint32_t init_svtor; bool enable_bitband; bool start_powered_off; } ARMv7MState; #endif