description: > This defines a PCIe slot to be exposed for system management. It includes the slot properties. properties: - name: Generation type: enum[self.Generations] default: 'Unknown' description: > The PCIe generation of the slot - name: Lanes type: size description: > The maximum number of PCIe lanes supported by the slot - name: SlotType type: enum[self.SlotTypes] default: 'Unknown' description: > The type of the slot - name: HotPluggable type: boolean description: > Whether this PCIe slot supports hotplug enumerations: - name: Generations description: > Possible PCIe generations values: - name: 'Gen1' description: > PCIe v1.0 slot - name: 'Gen2' description: > PCIe v2.0 slot - name: 'Gen3' description: > PCIe v3.0 slot - name: 'Gen4' description: > PCIe v4.0 slot - name: 'Gen5' description: > PCIe v5.0 slot - name: 'Unknown' description: > Version of the PCIe slot is unknown - name: SlotTypes description: > Possible types of a PCIe slot values: - name: 'FullLength' description: > Full-Length PCIe slot - name: 'HalfLength' description: > Half-Length PCIe slot - name: 'LowProfile' description: > Low-Profile or Slim PCIe slot - name: 'Mini' description: > Mini PCIe slot - name: 'M_2' description: > PCIe M.2 slot - name: 'OEM' description: > An OEM-specific PCIe slot - name: 'OCP3Small' description: > Open Compute Project 3.0 small form factor PCIe slot - name: 'OCP3Large' description: > Open Compute Project 3.0 large form factor PCIe slot - name: 'U_2' description: > U.2 / SFF-8639 PCIe slot or bay - name: 'Unknown' description: > Type of the PCIe slot is unknown associations: - name: upstream_processor description: > Objects that implement PCIeSlot can optionally implement the upstream_processor association to provide a link back to a PCIe host bridge or on-processor PCIe root complexes. reverse_name: associated_pcie_slots required_endpoint_interfaces: - xyz.openbmc_project.Inventory.Item.Cpu