[
    {
        "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.",
        "EventCode": "0x85",
        "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.",
        "EventCode": "0x85",
        "EventName": "UNC_ARB_DAT_OCCUPANCY.RD",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_DAT_REQUESTS.RD",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
        "EventCode": "0x85",
        "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "UNC_CLOCK.SOCKET",
        "EventCode": "0xff",
        "EventName": "UNC_CLOCK.SOCKET",
        "PerPkg": "1",
        "Unit": "CLOCK"
    },
    {
        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    },
    {
        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    },
    {
        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    },
    {
        "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    },
    {
        "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.",
        "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    },
    {
        "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.",
        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
        "PerPkg": "1",
        "Unit": "imc"
    }
]