[
    {
        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "Counter": "0,1",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "PublicDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
        "CounterMask": "1",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
        "PerPkg": "1",
        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ",
        "PerPkg": "1",
        "PublicDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.",
        "UMask": "0x02",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ",
        "PerPkg": "1",
        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "UMask": "0x02",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
        "PerPkg": "1",
        "PublicDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.",
        "UMask": "0x02",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
        "PerPkg": "1",
        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "UMask": "0x20",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
        "Counter": "FIXED",
        "EventCode": "0xff",
        "EventName": "UNC_CLOCK.SOCKET",
        "PerPkg": "1",
        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
        "Unit": "CLOCK"
    }
]