[
  {
    "EventCode": "0x10132",
    "EventName": "PM_MRK_INST_ISSUED",
    "BriefDescription": "Marked instruction issued. Note that stores always get issued twice, the address gets issued to the LSU and the data gets issued to the VSU. Also, issues can sometimes get killed/cancelled and cause multiple sequential issues for the same instruction."
  },
  {
    "EventCode": "0x10134",
    "EventName": "PM_MRK_ST_DONE_L2",
    "BriefDescription": "Marked store completed in L2."
  },
  {
    "EventCode": "0x1C142",
    "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",
    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x1C144",
    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",
    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."
  },
  {
    "EventCode": "0x1F150",
    "EventName": "PM_MRK_ST_L2_CYC",
    "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."
  },
  {
    "EventCode": "0x101E0",
    "EventName": "PM_MRK_INST_DISP",
    "BriefDescription": "The thread has dispatched a randomly sampled marked instruction."
  },
  {
    "EventCode": "0x101E2",
    "EventName": "PM_MRK_BR_TAKEN_CMPL",
    "BriefDescription": "Marked Branch Taken instruction completed."
  },
  {
    "EventCode": "0x101E4",
    "EventName": "PM_MRK_L1_ICACHE_MISS",
    "BriefDescription": "Marked instruction suffered an instruction cache miss."
  },
  {
    "EventCode": "0x101EA",
    "EventName": "PM_MRK_L1_RELOAD_VALID",
    "BriefDescription": "Marked demand reload."
  },
  {
    "EventCode": "0x20114",
    "EventName": "PM_MRK_L2_RC_DISP",
    "BriefDescription": "Marked instruction RC dispatched in L2."
  },
  {
    "EventCode": "0x2011C",
    "EventName": "PM_MRK_NTF_CYC",
    "BriefDescription": "Cycles in which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete)."
  },
  {
    "EventCode": "0x20130",
    "EventName": "PM_MRK_INST_DECODED",
    "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only."
  },
  {
    "EventCode": "0x20132",
    "EventName": "PM_MRK_DFU_ISSUE",
    "BriefDescription": "The marked instruction was a decimal floating point operation issued to the VSU. Measured at issue time."
  },
  {
    "EventCode": "0x20134",
    "EventName": "PM_MRK_FXU_ISSUE",
    "BriefDescription": "The marked instruction was a fixed point operation issued to the VSU. Measured at issue time."
  },
  {
    "EventCode": "0x20138",
    "EventName": "PM_MRK_ST_NEST",
    "BriefDescription": "A store has been sampled/marked and is at the point of execution where it has completed in the core and can no longer be flushed. At this point the store is sent to the L2."
  },
  {
    "EventCode": "0x2013A",
    "EventName": "PM_MRK_BRU_FIN",
    "BriefDescription": "Marked Branch instruction finished."
  },
  {
    "EventCode": "0x2013C",
    "EventName": "PM_MRK_FX_LSU_FIN",
    "BriefDescription": "The marked instruction was simple fixed point that was issued to the store unit. Measured at finish time."
  },
  {
    "EventCode": "0x2C142",
    "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",
    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x2C144",
    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC2",
    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[15:27]."
  },
  {
    "EventCode": "0x24156",
    "EventName": "PM_MRK_STCX_FIN",
    "BriefDescription": "Marked conditional store instruction (STCX) finished. LARX and STCX are instructions used to acquire a lock."
  },
  {
    "EventCode": "0x24158",
    "EventName": "PM_MRK_INST",
    "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens."
  },
  {
    "EventCode": "0x2415C",
    "EventName": "PM_MRK_BR_CMPL",
    "BriefDescription": "A marked branch completed. All branches are included."
  },
  {
    "EventCode": "0x2D154",
    "EventName": "PM_MRK_DERAT_MISS_64K",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x201E0",
    "EventName": "PM_MRK_DATA_FROM_MEMORY",
    "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss for a marked load."
  },
  {
    "EventCode": "0x201E2",
    "EventName": "PM_MRK_LD_MISS_L1",
    "BriefDescription": "Marked demand data load miss counted at finish time."
  },
  {
    "EventCode": "0x201E4",
    "EventName": "PM_MRK_DATA_FROM_L3MISS",
    "BriefDescription": "The processor's data cache was reloaded from a source other than the local core's L1, L2, or L3 due to a demand miss for a marked load."
  },
  {
    "EventCode": "0x3012A",
    "EventName": "PM_MRK_L2_RC_DONE",
    "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
  },
  {
    "EventCode": "0x30132",
    "EventName": "PM_MRK_VSU_FIN",
    "BriefDescription": "VSU marked instruction finished. Excludes simple FX instructions issued to the Store Unit."
  },
  {
    "EventCode": "0x34146",
    "EventName": "PM_MRK_LD_CMPL",
    "BriefDescription": "Marked load instruction completed."
  },
  {
    "EventCode": "0x3C142",
    "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",
    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x3C144",
    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",
    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."
  },
  {
    "EventCode": "0x3E158",
    "EventName": "PM_MRK_STCX_FAIL",
    "BriefDescription": "Marked conditional store instruction (STCX) failed. LARX and STCX are instructions used to acquire a lock."
  },
  {
    "EventCode": "0x3E15A",
    "EventName": "PM_MRK_ST_FIN",
    "BriefDescription": "Marked store instruction finished."
  },
  {
    "EventCode": "0x3F150",
    "EventName": "PM_MRK_ST_DRAIN_CYC",
    "BriefDescription": "Cycles in which the marked store drained from the core to the L2."
  },
  {
    "EventCode": "0x30162",
    "EventName": "PM_MRK_ISSUE_DEPENDENT_LOAD",
    "BriefDescription": "The marked instruction was dependent on a load. It is eligible for issue kill."
  },
  {
    "EventCode": "0x301E2",
    "EventName": "PM_MRK_ST_CMPL",
    "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."
  },
  {
    "EventCode": "0x301E4",
    "EventName": "PM_MRK_BR_MPRED_CMPL",
    "BriefDescription": "Marked Branch Mispredicted. Includes direction and target."
  },
  {
    "EventCode": "0x40116",
    "EventName": "PM_MRK_LARX_FIN",
    "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
  },
  {
    "EventCode": "0x40132",
    "EventName": "PM_MRK_LSU_FIN",
    "BriefDescription": "LSU marked instruction finish."
  },
  {
    "EventCode": "0x44146",
    "EventName": "PM_MRK_STCX_CORE_CYC",
    "BriefDescription": "Cycles spent in the core portion of a marked STCX instruction. It starts counting when the instruction is decoded and stops counting when it drains into the L2."
  },
  {
    "EventCode": "0x4C142",
    "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",
    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
  },
  {
    "EventCode": "0x4C144",
    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",
    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."
  },
  {
    "EventCode": "0x4C15E",
    "EventName": "PM_MRK_DTLB_MISS_64K",
    "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x4E15E",
    "EventName": "PM_MRK_INST_FLUSHED",
    "BriefDescription": "The marked instruction was flushed."
  },
  {
    "EventCode": "0x40164",
    "EventName": "PM_MRK_DERAT_MISS_2M",
    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
  },
  {
    "EventCode": "0x401E0",
    "EventName": "PM_MRK_INST_CMPL",
    "BriefDescription": "Marked instruction completed."
  },
  {
    "EventCode": "0x401E6",
    "EventName": "PM_MRK_INST_FROM_L3MISS",
    "BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L3 due to a demand miss for a marked instruction."
  },
  {
    "EventCode": "0x401E8",
    "EventName": "PM_MRK_DATA_FROM_L2MISS",
    "BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss for a marked instruction."
  }
]