// SPDX-License-Identifier: GPL-2.0-or-later /* * Lite5200 board Device Tree Source * * Copyright 2006-2007 Secret Lab Technologies Ltd. * Grant Likely */ /dts-v1/; / { model = "fsl,lite5200"; compatible = "fsl,lite5200"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&mpc5200_pic>; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,5200@0 { device_type = "cpu"; reg = <0>; d-cache-line-size = <32>; i-cache-line-size = <32>; d-cache-size = <0x4000>; // L1, 16K i-cache-size = <0x4000>; // L1, 16K timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader }; }; memory { device_type = "memory"; reg = <0x00000000 0x04000000>; // 64MB }; soc5200@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc5200-immr"; ranges = <0 0xf0000000 0x0000c000>; reg = <0xf0000000 0x00000100>; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader cdm@200 { compatible = "fsl,mpc5200-cdm"; reg = <0x200 0x38>; }; mpc5200_pic: interrupt-controller@500 { // 5200 interrupts are encoded into two levels; interrupt-controller; #interrupt-cells = <3>; compatible = "fsl,mpc5200-pic"; reg = <0x500 0x80>; }; timer@600 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x600 0x10>; interrupts = <1 9 0>; fsl,has-wdt; }; timer@610 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x610 0x10>; interrupts = <1 10 0>; }; timer@620 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x620 0x10>; interrupts = <1 11 0>; }; timer@630 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x630 0x10>; interrupts = <1 12 0>; }; timer@640 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x640 0x10>; interrupts = <1 13 0>; }; timer@650 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x650 0x10>; interrupts = <1 14 0>; }; timer@660 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x660 0x10>; interrupts = <1 15 0>; }; timer@670 { // General Purpose Timer compatible = "fsl,mpc5200-gpt"; reg = <0x670 0x10>; interrupts = <1 16 0>; }; rtc@800 { // Real time clock compatible = "fsl,mpc5200-rtc"; reg = <0x800 0x100>; interrupts = <1 5 0 1 6 0>; }; can@900 { compatible = "fsl,mpc5200-mscan"; interrupts = <2 17 0>; reg = <0x900 0x80>; }; can@980 { compatible = "fsl,mpc5200-mscan"; interrupts = <2 18 0>; reg = <0x980 0x80>; }; gpio@b00 { compatible = "fsl,mpc5200-gpio"; reg = <0xb00 0x40>; interrupts = <1 7 0>; gpio-controller; #gpio-cells = <2>; }; gpio@c00 { compatible = "fsl,mpc5200-gpio-wkup"; reg = <0xc00 0x40>; interrupts = <1 8 0 0 3 0>; gpio-controller; #gpio-cells = <2>; }; spi@f00 { compatible = "fsl,mpc5200-spi"; reg = <0xf00 0x20>; interrupts = <2 13 0 2 14 0>; }; usb@1000 { compatible = "fsl,mpc5200-ohci","ohci-be"; reg = <0x1000 0xff>; interrupts = <2 6 0>; }; dma-controller@1200 { compatible = "fsl,mpc5200-bestcomm"; reg = <0x1200 0x80>; interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 3 8 0 3 9 0 3 10 0 3 11 0 3 12 0 3 13 0 3 14 0 3 15 0>; }; xlb@1f00 { compatible = "fsl,mpc5200-xlb"; reg = <0x1f00 0x100>; }; serial@2000 { // PSC1 compatible = "fsl,mpc5200-psc-uart"; cell-index = <0>; reg = <0x2000 0x100>; interrupts = <2 1 0>; }; // PSC2 in ac97 mode example //ac97@2200 { // PSC2 // compatible = "fsl,mpc5200-psc-ac97"; // cell-index = <1>; // reg = <0x2200 0x100>; // interrupts = <2 2 0>; //}; // PSC3 in CODEC mode example //i2s@2400 { // PSC3 // compatible = "fsl,mpc5200-psc-i2s"; // cell-index = <2>; // reg = <0x2400 0x100>; // interrupts = <2 3 0>; //}; // PSC4 in uart mode example //serial@2600 { // PSC4 // compatible = "fsl,mpc5200-psc-uart"; // cell-index = <3>; // reg = <0x2600 0x100>; // interrupts = <2 11 0>; //}; // PSC5 in uart mode example //serial@2800 { // PSC5 // compatible = "fsl,mpc5200-psc-uart"; // cell-index = <4>; // reg = <0x2800 0x100>; // interrupts = <2 12 0>; //}; // PSC6 in spi mode example //spi@2c00 { // PSC6 // compatible = "fsl,mpc5200-psc-spi"; // cell-index = <5>; // reg = <0x2c00 0x100>; // interrupts = <2 4 0>; //}; ethernet@3000 { compatible = "fsl,mpc5200-fec"; reg = <0x3000 0x400>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5200-mdio"; reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. phy0: ethernet-phy@0 { reg = <0>; }; }; ata@3a00 { compatible = "fsl,mpc5200-ata"; reg = <0x3a00 0x100>; interrupts = <2 7 0>; }; i2c@3d00 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d00 0x40>; interrupts = <2 15 0>; }; i2c@3d40 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; }; sram@8000 { compatible = "fsl,mpc5200-sram"; reg = <0x8000 0x4000>; }; }; pci@f0000d00 { #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; compatible = "fsl,mpc5200-pci"; reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 0xc000 0 0 2 &mpc5200_pic 0 0 3 0xc000 0 0 3 &mpc5200_pic 0 0 3 0xc000 0 0 4 &mpc5200_pic 0 0 3>; clock-frequency = <0>; // From boot loader interrupts = <2 8 0 2 9 0 2 10 0>; bus-range = <0 0>; ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000>, <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000>, <0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; }; localbus { compatible = "fsl,mpc5200-lpb","simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0xff000000 0x01000000>; flash@0,0 { compatible = "amd,am29lv652d", "cfi-flash"; reg = <0 0 0x01000000>; bank-width = <1>; }; }; };