/*
 * T2081 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *	 notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *	 notice, this list of conditions and the following disclaimer in the
 *	 documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *	 names of its contributors may be used to endorse or promote products
 *	 derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&bman_fbpr {
	compatible = "fsl,bman-fbpr";
	alloc-ranges = <0 0 0x10000 0>;
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,ifc", "simple-bus";
	interrupts = <25 2 0 0>;
};

/* controller at 0x240000 */
&pci0 {
	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	interrupts = <20 2 0 0>;
	fsl,iommu-parent = <&pamu0>;
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <20 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 40 1 0 0
			0000 0 0 2 &mpic 1 1 0 0
			0000 0 0 3 &mpic 2 1 0 0
			0000 0 0 4 &mpic 3 1 0 0
		>;
	};
};

/* controller at 0x250000 */
&pci1 {
	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 0xff>;
	interrupts = <21 2 0 0>;
	fsl,iommu-parent = <&pamu0>;
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <21 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 41 1 0 0
			0000 0 0 2 &mpic 5 1 0 0
			0000 0 0 3 &mpic 6 1 0 0
			0000 0 0 4 &mpic 7 1 0 0
		>;
	};
};

/* controller at 0x260000 */
&pci2 {
	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	interrupts = <22 2 0 0>;
	fsl,iommu-parent = <&pamu0>;
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <22 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 42 1 0 0
			0000 0 0 2 &mpic 9 1 0 0
			0000 0 0 3 &mpic 10 1 0 0
			0000 0 0 4 &mpic 11 1 0 0
		>;
	};
};

/* controller at 0x270000 */
&pci3 {
	compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	interrupts = <23 2 0 0>;
	fsl,iommu-parent = <&pamu0>;
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <23 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0 0 1 &mpic 43 1 0 0
			0000 0 0 2 &mpic 0 1 0 0
			0000 0 0 3 &mpic 4 1 0 0
			0000 0 0 4 &mpic 8 1 0 0
		>;
	};
};

&dcsr {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,dcsr", "simple-bus";

	dcsr-epu@0 {
		compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
		interrupts = <52 2 0 0
			      84 2 0 0
			      85 2 0 0
			      94 2 0 0
			      95 2 0 0>;
		reg = <0x0 0x1000>;
	};
	dcsr-npc {
		compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
		reg = <0x1000 0x1000 0x1002000 0x10000>;
	};
	dcsr-nxc@2000 {
		compatible = "fsl,dcsr-nxc";
		reg = <0x2000 0x1000>;
	};
	dcsr-corenet {
		compatible = "fsl,dcsr-corenet";
		reg = <0x8000 0x1000 0x1A000 0x1000>;
	};
	dcsr-ocn@11000 {
		compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
		reg = <0x11000 0x1000>;
	};
	dcsr-ddr@12000 {
		compatible = "fsl,dcsr-ddr";
		dev-handle = <&ddr1>;
		reg = <0x12000 0x1000>;
	};
	dcsr-nal@18000 {
		compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
		reg = <0x18000 0x1000>;
	};
	dcsr-rcpm@22000 {
		compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
		reg = <0x22000 0x1000>;
	};
	dcsr-snpc@30000 {
		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
		reg = <0x30000 0x1000 0x1022000 0x10000>;
	};
	dcsr-snpc@31000 {
		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
		reg = <0x31000 0x1000 0x1042000 0x10000>;
	};
	dcsr-snpc@32000 {
		compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
		reg = <0x32000 0x1000 0x1062000 0x10000>;
	};
	dcsr-cpu-sb-proxy@100000 {
		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		cpu-handle = <&cpu0>;
		reg = <0x100000 0x1000 0x101000 0x1000>;
	};
	dcsr-cpu-sb-proxy@108000 {
		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		cpu-handle = <&cpu1>;
		reg = <0x108000 0x1000 0x109000 0x1000>;
	};
	dcsr-cpu-sb-proxy@110000 {
		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		cpu-handle = <&cpu2>;
		reg = <0x110000 0x1000 0x111000 0x1000>;
	};
	dcsr-cpu-sb-proxy@118000 {
		compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		cpu-handle = <&cpu3>;
		reg = <0x118000 0x1000 0x119000 0x1000>;
	};
};

&bportals {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	compatible = "simple-bus";

	bman-portal@0 {
		compatible = "fsl,bman-portal";
		reg = <0x0 0x4000>, <0x1000000 0x1000>;
		interrupts = <105 2 0 0>;
	};
	bman-portal@4000 {
		compatible = "fsl,bman-portal";
		reg = <0x4000 0x4000>, <0x1001000 0x1000>;
		interrupts = <107 2 0 0>;
	};
	bman-portal@8000 {
		compatible = "fsl,bman-portal";
		reg = <0x8000 0x4000>, <0x1002000 0x1000>;
		interrupts = <109 2 0 0>;
	};
	bman-portal@c000 {
		compatible = "fsl,bman-portal";
		reg = <0xc000 0x4000>, <0x1003000 0x1000>;
		interrupts = <111 2 0 0>;
	};
	bman-portal@10000 {
		compatible = "fsl,bman-portal";
		reg = <0x10000 0x4000>, <0x1004000 0x1000>;
		interrupts = <113 2 0 0>;
	};
	bman-portal@14000 {
		compatible = "fsl,bman-portal";
		reg = <0x14000 0x4000>, <0x1005000 0x1000>;
		interrupts = <115 2 0 0>;
	};
	bman-portal@18000 {
		compatible = "fsl,bman-portal";
		reg = <0x18000 0x4000>, <0x1006000 0x1000>;
		interrupts = <117 2 0 0>;
	};
	bman-portal@1c000 {
		compatible = "fsl,bman-portal";
		reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
		interrupts = <119 2 0 0>;
	};
	bman-portal@20000 {
		compatible = "fsl,bman-portal";
		reg = <0x20000 0x4000>, <0x1008000 0x1000>;
		interrupts = <121 2 0 0>;
	};
	bman-portal@24000 {
		compatible = "fsl,bman-portal";
		reg = <0x24000 0x4000>, <0x1009000 0x1000>;
		interrupts = <123 2 0 0>;
	};
	bman-portal@28000 {
		compatible = "fsl,bman-portal";
		reg = <0x28000 0x4000>, <0x100a000 0x1000>;
		interrupts = <125 2 0 0>;
	};
	bman-portal@2c000 {
		compatible = "fsl,bman-portal";
		reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
		interrupts = <127 2 0 0>;
	};
	bman-portal@30000 {
		compatible = "fsl,bman-portal";
		reg = <0x30000 0x4000>, <0x100c000 0x1000>;
		interrupts = <129 2 0 0>;
	};
	bman-portal@34000 {
		compatible = "fsl,bman-portal";
		reg = <0x34000 0x4000>, <0x100d000 0x1000>;
		interrupts = <131 2 0 0>;
	};
	bman-portal@38000 {
		compatible = "fsl,bman-portal";
		reg = <0x38000 0x4000>, <0x100e000 0x1000>;
		interrupts = <133 2 0 0>;
	};
	bman-portal@3c000 {
		compatible = "fsl,bman-portal";
		reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
		interrupts = <135 2 0 0>;
	};
	bman-portal@40000 {
		compatible = "fsl,bman-portal";
		reg = <0x40000 0x4000>, <0x1010000 0x1000>;
		interrupts = <137 2 0 0>;
	};
	bman-portal@44000 {
		compatible = "fsl,bman-portal";
		reg = <0x44000 0x4000>, <0x1011000 0x1000>;
		interrupts = <139 2 0 0>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "simple-bus";

	soc-sram-error {
		compatible = "fsl,soc-sram-error";
		interrupts = <16 2 1 29>;
	};

	corenet-law@0 {
		compatible = "fsl,corenet-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <32>;
	};

	ddr1: memory-controller@8000 {
		compatible = "fsl,qoriq-memory-controller-v4.7",
				"fsl,qoriq-memory-controller";
		reg = <0x8000 0x1000>;
		interrupts = <16 2 1 23>;
	};

	cpc: l3-cache-controller@10000 {
		compatible = "fsl,t2080-l3-cache-controller", "cache";
		reg = <0x10000 0x1000
		       0x11000 0x1000
		       0x12000 0x1000>;
		interrupts = <16 2 1 27
			      16 2 1 26
			      16 2 1 25>;
	};

	corenet-cf@18000 {
		compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
		reg = <0x18000 0x1000>;
		interrupts = <16 2 1 31>;
		fsl,ccf-num-csdids = <32>;
		fsl,ccf-num-snoopids = <32>;
	};

	iommu@20000 {
		compatible = "fsl,pamu-v1.0", "fsl,pamu";
		reg = <0x20000 0x3000>;
		fsl,portid-mapping = <0x8000>;
		ranges = <0 0x20000 0x3000>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <
			24 2 0 0
			16 2 1 30>;

		pamu0: pamu@0 {
			reg = <0 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <128 2>;
		};

		pamu1: pamu@1000 {
			reg = <0x1000 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <128 2>;
		};

		pamu2: pamu@2000 {
			reg = <0x2000 0x1000>;
			fsl,primary-cache-geometry = <32 1>;
			fsl,secondary-cache-geometry = <128 2>;
		};
	};

/include/ "qoriq-mpic4.3.dtsi"

	guts: global-utilities@e0000 {
		compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
		reg = <0xe0000 0xe00>;
		fsl,has-rstcr;
		fsl,liodn-bits = <12>;
	};

/include/ "qoriq-clockgen2.dtsi"
	global-utilities@e1000 {
		compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";

		mux0: mux0@0 {
			#clock-cells = <0>;
			reg = <0x0 4>;
			compatible = "fsl,qoriq-core-mux-2.0";
			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
			clock-names = "pll0", "pll0-div2", "pll0-div4",
				"pll1", "pll1-div2", "pll1-div4";
			clock-output-names = "cmux0";
		};

		mux1: mux1@20 {
			#clock-cells = <0>;
			reg = <0x20 4>;
			compatible = "fsl,qoriq-core-mux-2.0";
			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
				 <&pll1 0>, <&pll1 1>, <&pll1 2>;
			clock-names = "pll0", "pll0-div2", "pll0-div4",
				"pll1", "pll1-div2", "pll1-div4";
			clock-output-names = "cmux1";
		};
	};

	rcpm: global-utilities@e2000 {
		compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
		reg = <0xe2000 0x1000>;
	};

	sfp: sfp@e8000 {
		compatible = "fsl,t2080-sfp";
		reg = <0xe8000 0x1000>;
	};

	serdes: serdes@ea000 {
		compatible = "fsl,t2080-serdes";
		reg = <0xea000 0x4000>;
	};

/include/ "elo3-dma-0.dtsi"
	dma@100300 {
		fsl,iommu-parent = <&pamu0>;
		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
	};
/include/ "elo3-dma-1.dtsi"
	dma@101300 {
		fsl,iommu-parent = <&pamu0>;
		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
	};
/include/ "elo3-dma-2.dtsi"
	dma@102300 {
		fsl,iommu-parent = <&pamu0>;
		fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
	};

/include/ "qoriq-espi-0.dtsi"
	spi@110000 {
		fsl,espi-num-chipselects = <4>;
	};

/include/ "qoriq-esdhc-0.dtsi"
	sdhc@114000 {
		compatible = "fsl,t2080-esdhc", "fsl,esdhc";
		fsl,iommu-parent = <&pamu1>;
		fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
		sdhci,auto-cmd12;
	};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-usb2-mph-0.dtsi"
	usb0: usb@210000 {
		compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
		fsl,iommu-parent = <&pamu1>;
		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
		phy_type = "utmi";
		port0;
	};
/include/ "qoriq-usb2-dr-0.dtsi"
	usb1: usb@211000 {
		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
		fsl,iommu-parent = <&pamu1>;
		fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
		dr_mode = "host";
		phy_type = "utmi";
	};
/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-bman1.dtsi"

	L2_1: l2-cache-controller@c20000 {
		/* Cluster 0 L2 cache */
		compatible = "fsl,t2080-l2-cache-controller";
		reg = <0xc20000 0x40000>;
		next-level-cache = <&cpc>;
	};
};