/*
 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
 *
 * Copyright 2014 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *	 notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *	 notice, this list of conditions and the following disclaimer in the
 *	 documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *	 names of its contributors may be used to endorse or promote products
 *	 derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

global-utilities@e1000 {
	compatible = "fsl,qoriq-clockgen-2.0";
	ranges = <0x0 0xe1000 0x1000>;
	reg = <0xe1000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	sysclk: sysclk {
		#clock-cells = <0>;
		compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
		clock-output-names = "sysclk";
	};
	pll0: pll0@800 {
		#clock-cells = <1>;
		reg = <0x800 0x4>;
		compatible = "fsl,qoriq-core-pll-2.0";
		clocks = <&sysclk>;
		clock-output-names = "pll0", "pll0-div2", "pll0-div4";
	};
	pll1: pll1@820 {
		#clock-cells = <1>;
		reg = <0x820 0x4>;
		compatible = "fsl,qoriq-core-pll-2.0";
		clocks = <&sysclk>;
		clock-output-names = "pll1", "pll1-div2", "pll1-div4";
	};
};