/* * P4080DS Device Tree Source * * Copyright 2009 - 2015 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /include/ "p4080si-pre.dtsi" / { model = "fsl,P4080DS"; compatible = "fsl,P4080DS"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { phy_rgmii = &phyrgmii; phy5_slot3 = &phy5slot3; phy6_slot3 = &phy6slot3; phy7_slot3 = &phy7slot3; phy8_slot3 = &phy8slot3; emi1_slot3 = &p4080mdio2; emi1_slot4 = &p4080mdio1; emi1_slot5 = &p4080mdio3; emi1_rgmii = &p4080mdio0; emi2_slot4 = &p4080xmdio1; emi2_slot5 = &p4080xmdio3; }; memory { device_type = "memory"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bman_fbpr: bman-fbpr { size = <0 0x1000000>; alignment = <0 0x1000000>; }; qman_fqd: qman-fqd { size = <0 0x400000>; alignment = <0 0x400000>; }; qman_pfdr: qman-pfdr { size = <0 0x2000000>; alignment = <0 0x2000000>; }; }; dcsr: dcsr@f00000000 { ranges = <0x00000000 0xf 0x00000000 0x01008000>; }; bportals: bman-portals@ff4000000 { ranges = <0x0 0xf 0xf4000000 0x200000>; }; qportals: qman-portals@ff4200000 { ranges = <0x0 0xf 0xf4200000 0x200000>; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; spi@110000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25sl12801"; reg = <0>; spi-max-frequency = <40000000>; /* input clock */ partition@u-boot { label = "u-boot"; reg = <0x00000000 0x00100000>; read-only; }; partition@kernel { label = "kernel"; reg = <0x00100000 0x00500000>; read-only; }; partition@dtb { label = "dtb"; reg = <0x00600000 0x00100000>; read-only; }; partition@fs { label = "file system"; reg = <0x00700000 0x00900000>; }; }; }; i2c@118100 { eeprom@51 { compatible = "at24,24c256"; reg = <0x51>; }; eeprom@52 { compatible = "at24,24c256"; reg = <0x52>; }; rtc@68 { compatible = "dallas,ds3232"; reg = <0x68>; interrupts = <0x1 0x1 0 0>; }; adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; usb0: usb@210000 { phy_type = "ulpi"; }; usb1: usb@211000 { dr_mode = "host"; phy_type = "ulpi"; }; fman@400000 { ethernet@e0000 { phy-handle = <&phy0>; phy-connection-type = "sgmii"; }; ethernet@e2000 { phy-handle = <&phy1>; phy-connection-type = "sgmii"; }; ethernet@e4000 { phy-handle = <&phy2>; phy-connection-type = "sgmii"; }; ethernet@e6000 { phy-handle = <&phy3>; phy-connection-type = "sgmii"; }; ethernet@f0000 { phy-handle = <&phy10>; phy-connection-type = "xgmii"; }; }; fman@500000 { ethernet@e0000 { phy-handle = <&phy5>; phy-connection-type = "sgmii"; }; ethernet@e2000 { phy-handle = <&phy6>; phy-connection-type = "sgmii"; }; ethernet@e4000 { phy-handle = <&phy7>; phy-connection-type = "sgmii"; }; ethernet@e6000 { phy-handle = <&phy8>; phy-connection-type = "sgmii"; }; ethernet@f0000 { phy-handle = <&phy11>; phy-connection-type = "xgmii"; }; }; }; rio: rapidio@ffe0c0000 { reg = <0xf 0xfe0c0000 0 0x11000>; port1 { ranges = <0 0 0xc 0x20000000 0 0x10000000>; }; port2 { ranges = <0 0 0xc 0x30000000 0 0x10000000>; }; }; lbc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x1000>; ranges = <0 0 0xf 0xe8000000 0x08000000 3 0 0xf 0xffdf0000 0x00008000>; flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x08000000>; bank-width = <2>; device-width = <2>; }; board-control@3,0 { compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; reg = <3 0 0x30>; }; }; pci0: pcie@ffe200000 { reg = <0xf 0xfe200000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci1: pcie@ffe201000 { reg = <0xf 0xfe201000 0 0x1000>; ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci2: pcie@ffe202000 { reg = <0xf 0xfe202000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; mdio-mux-emi1 { #address-cells = <1>; #size-cells = <0>; compatible = "mdio-mux-gpio", "mdio-mux"; mdio-parent-bus = <&mdio0>; gpios = <&gpio0 1 0>, <&gpio0 0 0>; p4080mdio0: mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; phyrgmii: ethernet-phy@0 { reg = <0x0>; }; }; p4080mdio1: mdio@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; phy5: ethernet-phy@1c { reg = <0x1c>; }; phy6: ethernet-phy@1d { reg = <0x1d>; }; phy7: ethernet-phy@1e { reg = <0x1e>; }; phy8: ethernet-phy@1f { reg = <0x1f>; }; }; p4080mdio2: mdio@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; status = "disabled"; phy5slot3: ethernet-phy@1c { reg = <0x1c>; }; phy6slot3: ethernet-phy@1d { reg = <0x1d>; }; phy7slot3: ethernet-phy@1e { reg = <0x1e>; }; phy8slot3: ethernet-phy@1f { reg = <0x1f>; }; }; p4080mdio3: mdio@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; phy0: ethernet-phy@1c { reg = <0x1c>; }; phy1: ethernet-phy@1d { reg = <0x1d>; }; phy2: ethernet-phy@1e { reg = <0x1e>; }; phy3: ethernet-phy@1f { reg = <0x1f>; }; }; }; mdio-mux-emi2 { #address-cells = <1>; #size-cells = <0>; compatible = "mdio-mux-gpio", "mdio-mux"; mdio-parent-bus = <&xmdio0>; gpios = <&gpio0 3 0>, <&gpio0 2 0>; p4080xmdio1: mdio@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; phy11: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x0>; }; }; p4080xmdio3: mdio@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; phy10: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x4>; }; }; }; }; /include/ "p4080si-post.dtsi"