/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */

#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
#define DT_BINDINGS_RESET_TEGRA234_RESET_H

/**
 * @file
 * @defgroup bpmp_reset_ids Reset ID's
 * @brief Identifiers for Resets controllable by firmware
 * @{
 */
#define TEGRA234_RESET_HDA			20U
#define TEGRA234_RESET_HDACODEC			21U
#define TEGRA234_RESET_I2C1			24U
#define TEGRA234_RESET_I2C2			29U
#define TEGRA234_RESET_I2C3			30U
#define TEGRA234_RESET_I2C4			31U
#define TEGRA234_RESET_I2C6			32U
#define TEGRA234_RESET_I2C7			33U
#define TEGRA234_RESET_I2C8			34U
#define TEGRA234_RESET_I2C9			35U
#define TEGRA234_RESET_PWM1			68U
#define TEGRA234_RESET_PWM2			69U
#define TEGRA234_RESET_PWM3			70U
#define TEGRA234_RESET_PWM4			71U
#define TEGRA234_RESET_PWM5			72U
#define TEGRA234_RESET_PWM6			73U
#define TEGRA234_RESET_PWM7			74U
#define TEGRA234_RESET_PWM8			75U
#define TEGRA234_RESET_SDMMC4			85U
#define TEGRA234_RESET_UARTA			100U

/** @} */

#endif