/* * Copyright (C) 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _mmhub_9_4_1_OFFSET_HEADER #define _mmhub_9_4_1_OFFSET_HEADER // addressBlock: mmhub_dagb_dagbdec0 // base address: 0x68000 #define mmDAGB0_RDCLI0 0x0000 #define mmDAGB0_RDCLI0_BASE_IDX 1 #define mmDAGB0_RDCLI1 0x0001 #define mmDAGB0_RDCLI1_BASE_IDX 1 #define mmDAGB0_RDCLI2 0x0002 #define mmDAGB0_RDCLI2_BASE_IDX 1 #define mmDAGB0_RDCLI3 0x0003 #define mmDAGB0_RDCLI3_BASE_IDX 1 #define mmDAGB0_RDCLI4 0x0004 #define mmDAGB0_RDCLI4_BASE_IDX 1 #define mmDAGB0_RDCLI5 0x0005 #define mmDAGB0_RDCLI5_BASE_IDX 1 #define mmDAGB0_RDCLI6 0x0006 #define mmDAGB0_RDCLI6_BASE_IDX 1 #define mmDAGB0_RDCLI7 0x0007 #define mmDAGB0_RDCLI7_BASE_IDX 1 #define mmDAGB0_RDCLI8 0x0008 #define mmDAGB0_RDCLI8_BASE_IDX 1 #define mmDAGB0_RDCLI9 0x0009 #define mmDAGB0_RDCLI9_BASE_IDX 1 #define mmDAGB0_RDCLI10 0x000a #define mmDAGB0_RDCLI10_BASE_IDX 1 #define mmDAGB0_RDCLI11 0x000b #define mmDAGB0_RDCLI11_BASE_IDX 1 #define mmDAGB0_RDCLI12 0x000c #define mmDAGB0_RDCLI12_BASE_IDX 1 #define mmDAGB0_RDCLI13 0x000d #define mmDAGB0_RDCLI13_BASE_IDX 1 #define mmDAGB0_RDCLI14 0x000e #define mmDAGB0_RDCLI14_BASE_IDX 1 #define mmDAGB0_RDCLI15 0x000f #define mmDAGB0_RDCLI15_BASE_IDX 1 #define mmDAGB0_RD_CNTL 0x0010 #define mmDAGB0_RD_CNTL_BASE_IDX 1 #define mmDAGB0_RD_GMI_CNTL 0x0011 #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB0_RD_ADDR_DAGB 0x0012 #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB0_RD_VC0_CNTL 0x001c #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC1_CNTL 0x001d #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC2_CNTL 0x001e #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC3_CNTL 0x001f #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC4_CNTL 0x0020 #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC5_CNTL 0x0021 #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC6_CNTL 0x0022 #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB0_RD_VC7_CNTL 0x0023 #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB0_RD_CNTL_MISC 0x0024 #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB0_RD_TLB_CREDIT 0x0025 #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB0_RDCLI_ASK_PENDING 0x0026 #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB0_RDCLI_GO_PENDING 0x0027 #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB0_RDCLI_TLB_PENDING 0x0029 #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB0_RDCLI_OARB_PENDING 0x002a #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB0_RDCLI_OSD_PENDING 0x002b #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI0 0x002c #define mmDAGB0_WRCLI0_BASE_IDX 1 #define mmDAGB0_WRCLI1 0x002d #define mmDAGB0_WRCLI1_BASE_IDX 1 #define mmDAGB0_WRCLI2 0x002e #define mmDAGB0_WRCLI2_BASE_IDX 1 #define mmDAGB0_WRCLI3 0x002f #define mmDAGB0_WRCLI3_BASE_IDX 1 #define mmDAGB0_WRCLI4 0x0030 #define mmDAGB0_WRCLI4_BASE_IDX 1 #define mmDAGB0_WRCLI5 0x0031 #define mmDAGB0_WRCLI5_BASE_IDX 1 #define mmDAGB0_WRCLI6 0x0032 #define mmDAGB0_WRCLI6_BASE_IDX 1 #define mmDAGB0_WRCLI7 0x0033 #define mmDAGB0_WRCLI7_BASE_IDX 1 #define mmDAGB0_WRCLI8 0x0034 #define mmDAGB0_WRCLI8_BASE_IDX 1 #define mmDAGB0_WRCLI9 0x0035 #define mmDAGB0_WRCLI9_BASE_IDX 1 #define mmDAGB0_WRCLI10 0x0036 #define mmDAGB0_WRCLI10_BASE_IDX 1 #define mmDAGB0_WRCLI11 0x0037 #define mmDAGB0_WRCLI11_BASE_IDX 1 #define mmDAGB0_WRCLI12 0x0038 #define mmDAGB0_WRCLI12_BASE_IDX 1 #define mmDAGB0_WRCLI13 0x0039 #define mmDAGB0_WRCLI13_BASE_IDX 1 #define mmDAGB0_WRCLI14 0x003a #define mmDAGB0_WRCLI14_BASE_IDX 1 #define mmDAGB0_WRCLI15 0x003b #define mmDAGB0_WRCLI15_BASE_IDX 1 #define mmDAGB0_WR_CNTL 0x003c #define mmDAGB0_WR_CNTL_BASE_IDX 1 #define mmDAGB0_WR_GMI_CNTL 0x003d #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB0_WR_ADDR_DAGB 0x003e #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB0_WR_DATA_DAGB 0x0048 #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB0_WR_VC0_CNTL 0x004d #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC1_CNTL 0x004e #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC2_CNTL 0x004f #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC3_CNTL 0x0050 #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC4_CNTL 0x0051 #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC5_CNTL 0x0052 #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC6_CNTL 0x0053 #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB0_WR_VC7_CNTL 0x0054 #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB0_WR_CNTL_MISC 0x0055 #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB0_WR_TLB_CREDIT 0x0056 #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB0_WR_DATA_CREDIT 0x0057 #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB0_WR_MISC_CREDIT 0x0058 #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB0_WRCLI_ASK_PENDING 0x005d #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_GO_PENDING 0x005e #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005f #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_TLB_PENDING 0x0060 #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_OARB_PENDING 0x0061 #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_OSD_PENDING 0x0062 #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0063 #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0064 #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB0_DAGB_DLY 0x0065 #define mmDAGB0_DAGB_DLY_BASE_IDX 1 #define mmDAGB0_CNTL_MISC 0x0066 #define mmDAGB0_CNTL_MISC_BASE_IDX 1 #define mmDAGB0_CNTL_MISC2 0x0067 #define mmDAGB0_CNTL_MISC2_BASE_IDX 1 #define mmDAGB0_FIFO_EMPTY 0x0068 #define mmDAGB0_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB0_FIFO_FULL 0x0069 #define mmDAGB0_FIFO_FULL_BASE_IDX 1 #define mmDAGB0_WR_CREDITS_FULL 0x006a #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB0_RD_CREDITS_FULL 0x006b #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER_LO 0x006c #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER_HI 0x006d #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER0_CFG 0x006e #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER1_CFG 0x006f #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER2_CFG 0x0070 #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0071 #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB0_RESERVE0 0x0072 #define mmDAGB0_RESERVE0_BASE_IDX 1 #define mmDAGB0_RESERVE1 0x0073 #define mmDAGB0_RESERVE1_BASE_IDX 1 #define mmDAGB0_RESERVE2 0x0074 #define mmDAGB0_RESERVE2_BASE_IDX 1 #define mmDAGB0_RESERVE3 0x0075 #define mmDAGB0_RESERVE3_BASE_IDX 1 #define mmDAGB0_RESERVE4 0x0076 #define mmDAGB0_RESERVE4_BASE_IDX 1 #define mmDAGB0_RESERVE5 0x0077 #define mmDAGB0_RESERVE5_BASE_IDX 1 #define mmDAGB0_RESERVE6 0x0078 #define mmDAGB0_RESERVE6_BASE_IDX 1 #define mmDAGB0_RESERVE7 0x0079 #define mmDAGB0_RESERVE7_BASE_IDX 1 #define mmDAGB0_RESERVE8 0x007a #define mmDAGB0_RESERVE8_BASE_IDX 1 #define mmDAGB0_RESERVE9 0x007b #define mmDAGB0_RESERVE9_BASE_IDX 1 #define mmDAGB0_RESERVE10 0x007c #define mmDAGB0_RESERVE10_BASE_IDX 1 #define mmDAGB0_RESERVE11 0x007d #define mmDAGB0_RESERVE11_BASE_IDX 1 #define mmDAGB0_RESERVE12 0x007e #define mmDAGB0_RESERVE12_BASE_IDX 1 #define mmDAGB0_RESERVE13 0x007f #define mmDAGB0_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec1 // base address: 0x68200 #define mmDAGB1_RDCLI0 0x0080 #define mmDAGB1_RDCLI0_BASE_IDX 1 #define mmDAGB1_RDCLI1 0x0081 #define mmDAGB1_RDCLI1_BASE_IDX 1 #define mmDAGB1_RDCLI2 0x0082 #define mmDAGB1_RDCLI2_BASE_IDX 1 #define mmDAGB1_RDCLI3 0x0083 #define mmDAGB1_RDCLI3_BASE_IDX 1 #define mmDAGB1_RDCLI4 0x0084 #define mmDAGB1_RDCLI4_BASE_IDX 1 #define mmDAGB1_RDCLI5 0x0085 #define mmDAGB1_RDCLI5_BASE_IDX 1 #define mmDAGB1_RDCLI6 0x0086 #define mmDAGB1_RDCLI6_BASE_IDX 1 #define mmDAGB1_RDCLI7 0x0087 #define mmDAGB1_RDCLI7_BASE_IDX 1 #define mmDAGB1_RDCLI8 0x0088 #define mmDAGB1_RDCLI8_BASE_IDX 1 #define mmDAGB1_RDCLI9 0x0089 #define mmDAGB1_RDCLI9_BASE_IDX 1 #define mmDAGB1_RDCLI10 0x008a #define mmDAGB1_RDCLI10_BASE_IDX 1 #define mmDAGB1_RDCLI11 0x008b #define mmDAGB1_RDCLI11_BASE_IDX 1 #define mmDAGB1_RDCLI12 0x008c #define mmDAGB1_RDCLI12_BASE_IDX 1 #define mmDAGB1_RDCLI13 0x008d #define mmDAGB1_RDCLI13_BASE_IDX 1 #define mmDAGB1_RDCLI14 0x008e #define mmDAGB1_RDCLI14_BASE_IDX 1 #define mmDAGB1_RDCLI15 0x008f #define mmDAGB1_RDCLI15_BASE_IDX 1 #define mmDAGB1_RD_CNTL 0x0090 #define mmDAGB1_RD_CNTL_BASE_IDX 1 #define mmDAGB1_RD_GMI_CNTL 0x0091 #define mmDAGB1_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB1_RD_ADDR_DAGB 0x0092 #define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 #define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB1_RD_VC0_CNTL 0x009c #define mmDAGB1_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC1_CNTL 0x009d #define mmDAGB1_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC2_CNTL 0x009e #define mmDAGB1_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC3_CNTL 0x009f #define mmDAGB1_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC4_CNTL 0x00a0 #define mmDAGB1_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC5_CNTL 0x00a1 #define mmDAGB1_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC6_CNTL 0x00a2 #define mmDAGB1_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB1_RD_VC7_CNTL 0x00a3 #define mmDAGB1_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB1_RD_CNTL_MISC 0x00a4 #define mmDAGB1_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB1_RD_TLB_CREDIT 0x00a5 #define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 #define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB1_RDCLI_GO_PENDING 0x00a7 #define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 #define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 #define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB1_RDCLI_OARB_PENDING 0x00aa #define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB1_RDCLI_OSD_PENDING 0x00ab #define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI0 0x00ac #define mmDAGB1_WRCLI0_BASE_IDX 1 #define mmDAGB1_WRCLI1 0x00ad #define mmDAGB1_WRCLI1_BASE_IDX 1 #define mmDAGB1_WRCLI2 0x00ae #define mmDAGB1_WRCLI2_BASE_IDX 1 #define mmDAGB1_WRCLI3 0x00af #define mmDAGB1_WRCLI3_BASE_IDX 1 #define mmDAGB1_WRCLI4 0x00b0 #define mmDAGB1_WRCLI4_BASE_IDX 1 #define mmDAGB1_WRCLI5 0x00b1 #define mmDAGB1_WRCLI5_BASE_IDX 1 #define mmDAGB1_WRCLI6 0x00b2 #define mmDAGB1_WRCLI6_BASE_IDX 1 #define mmDAGB1_WRCLI7 0x00b3 #define mmDAGB1_WRCLI7_BASE_IDX 1 #define mmDAGB1_WRCLI8 0x00b4 #define mmDAGB1_WRCLI8_BASE_IDX 1 #define mmDAGB1_WRCLI9 0x00b5 #define mmDAGB1_WRCLI9_BASE_IDX 1 #define mmDAGB1_WRCLI10 0x00b6 #define mmDAGB1_WRCLI10_BASE_IDX 1 #define mmDAGB1_WRCLI11 0x00b7 #define mmDAGB1_WRCLI11_BASE_IDX 1 #define mmDAGB1_WRCLI12 0x00b8 #define mmDAGB1_WRCLI12_BASE_IDX 1 #define mmDAGB1_WRCLI13 0x00b9 #define mmDAGB1_WRCLI13_BASE_IDX 1 #define mmDAGB1_WRCLI14 0x00ba #define mmDAGB1_WRCLI14_BASE_IDX 1 #define mmDAGB1_WRCLI15 0x00bb #define mmDAGB1_WRCLI15_BASE_IDX 1 #define mmDAGB1_WR_CNTL 0x00bc #define mmDAGB1_WR_CNTL_BASE_IDX 1 #define mmDAGB1_WR_GMI_CNTL 0x00bd #define mmDAGB1_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB1_WR_ADDR_DAGB 0x00be #define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 #define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB1_WR_DATA_DAGB 0x00c8 #define mmDAGB1_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB1_WR_VC0_CNTL 0x00cd #define mmDAGB1_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC1_CNTL 0x00ce #define mmDAGB1_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC2_CNTL 0x00cf #define mmDAGB1_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC3_CNTL 0x00d0 #define mmDAGB1_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC4_CNTL 0x00d1 #define mmDAGB1_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC5_CNTL 0x00d2 #define mmDAGB1_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC6_CNTL 0x00d3 #define mmDAGB1_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB1_WR_VC7_CNTL 0x00d4 #define mmDAGB1_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB1_WR_CNTL_MISC 0x00d5 #define mmDAGB1_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB1_WR_TLB_CREDIT 0x00d6 #define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB1_WR_DATA_CREDIT 0x00d7 #define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB1_WR_MISC_CREDIT 0x00d8 #define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB1_WRCLI_ASK_PENDING 0x00dd #define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_GO_PENDING 0x00de #define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00df #define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_TLB_PENDING 0x00e0 #define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_OARB_PENDING 0x00e1 #define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_OSD_PENDING 0x00e2 #define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e3 #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e4 #define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB1_DAGB_DLY 0x00e5 #define mmDAGB1_DAGB_DLY_BASE_IDX 1 #define mmDAGB1_CNTL_MISC 0x00e6 #define mmDAGB1_CNTL_MISC_BASE_IDX 1 #define mmDAGB1_CNTL_MISC2 0x00e7 #define mmDAGB1_CNTL_MISC2_BASE_IDX 1 #define mmDAGB1_FIFO_EMPTY 0x00e8 #define mmDAGB1_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB1_FIFO_FULL 0x00e9 #define mmDAGB1_FIFO_FULL_BASE_IDX 1 #define mmDAGB1_WR_CREDITS_FULL 0x00ea #define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB1_RD_CREDITS_FULL 0x00eb #define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER_LO 0x00ec #define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER_HI 0x00ed #define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER0_CFG 0x00ee #define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER1_CFG 0x00ef #define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER2_CFG 0x00f0 #define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00f1 #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB1_RESERVE0 0x00f2 #define mmDAGB1_RESERVE0_BASE_IDX 1 #define mmDAGB1_RESERVE1 0x00f3 #define mmDAGB1_RESERVE1_BASE_IDX 1 #define mmDAGB1_RESERVE2 0x00f4 #define mmDAGB1_RESERVE2_BASE_IDX 1 #define mmDAGB1_RESERVE3 0x00f5 #define mmDAGB1_RESERVE3_BASE_IDX 1 #define mmDAGB1_RESERVE4 0x00f6 #define mmDAGB1_RESERVE4_BASE_IDX 1 #define mmDAGB1_RESERVE5 0x00f7 #define mmDAGB1_RESERVE5_BASE_IDX 1 #define mmDAGB1_RESERVE6 0x00f8 #define mmDAGB1_RESERVE6_BASE_IDX 1 #define mmDAGB1_RESERVE7 0x00f9 #define mmDAGB1_RESERVE7_BASE_IDX 1 #define mmDAGB1_RESERVE8 0x00fa #define mmDAGB1_RESERVE8_BASE_IDX 1 #define mmDAGB1_RESERVE9 0x00fb #define mmDAGB1_RESERVE9_BASE_IDX 1 #define mmDAGB1_RESERVE10 0x00fc #define mmDAGB1_RESERVE10_BASE_IDX 1 #define mmDAGB1_RESERVE11 0x00fd #define mmDAGB1_RESERVE11_BASE_IDX 1 #define mmDAGB1_RESERVE12 0x00fe #define mmDAGB1_RESERVE12_BASE_IDX 1 #define mmDAGB1_RESERVE13 0x00ff #define mmDAGB1_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec2 // base address: 0x68400 #define mmDAGB2_RDCLI0 0x0100 #define mmDAGB2_RDCLI0_BASE_IDX 1 #define mmDAGB2_RDCLI1 0x0101 #define mmDAGB2_RDCLI1_BASE_IDX 1 #define mmDAGB2_RDCLI2 0x0102 #define mmDAGB2_RDCLI2_BASE_IDX 1 #define mmDAGB2_RDCLI3 0x0103 #define mmDAGB2_RDCLI3_BASE_IDX 1 #define mmDAGB2_RDCLI4 0x0104 #define mmDAGB2_RDCLI4_BASE_IDX 1 #define mmDAGB2_RDCLI5 0x0105 #define mmDAGB2_RDCLI5_BASE_IDX 1 #define mmDAGB2_RDCLI6 0x0106 #define mmDAGB2_RDCLI6_BASE_IDX 1 #define mmDAGB2_RDCLI7 0x0107 #define mmDAGB2_RDCLI7_BASE_IDX 1 #define mmDAGB2_RDCLI8 0x0108 #define mmDAGB2_RDCLI8_BASE_IDX 1 #define mmDAGB2_RDCLI9 0x0109 #define mmDAGB2_RDCLI9_BASE_IDX 1 #define mmDAGB2_RDCLI10 0x010a #define mmDAGB2_RDCLI10_BASE_IDX 1 #define mmDAGB2_RDCLI11 0x010b #define mmDAGB2_RDCLI11_BASE_IDX 1 #define mmDAGB2_RDCLI12 0x010c #define mmDAGB2_RDCLI12_BASE_IDX 1 #define mmDAGB2_RDCLI13 0x010d #define mmDAGB2_RDCLI13_BASE_IDX 1 #define mmDAGB2_RDCLI14 0x010e #define mmDAGB2_RDCLI14_BASE_IDX 1 #define mmDAGB2_RDCLI15 0x010f #define mmDAGB2_RDCLI15_BASE_IDX 1 #define mmDAGB2_RD_CNTL 0x0110 #define mmDAGB2_RD_CNTL_BASE_IDX 1 #define mmDAGB2_RD_GMI_CNTL 0x0111 #define mmDAGB2_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB2_RD_ADDR_DAGB 0x0112 #define mmDAGB2_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 #define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 #define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB2_RD_CGTT_CLK_CTRL 0x0115 #define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 #define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 #define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a #define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b #define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB2_RD_VC0_CNTL 0x011c #define mmDAGB2_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC1_CNTL 0x011d #define mmDAGB2_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC2_CNTL 0x011e #define mmDAGB2_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC3_CNTL 0x011f #define mmDAGB2_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC4_CNTL 0x0120 #define mmDAGB2_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC5_CNTL 0x0121 #define mmDAGB2_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC6_CNTL 0x0122 #define mmDAGB2_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB2_RD_VC7_CNTL 0x0123 #define mmDAGB2_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB2_RD_CNTL_MISC 0x0124 #define mmDAGB2_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB2_RD_TLB_CREDIT 0x0125 #define mmDAGB2_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB2_RDCLI_ASK_PENDING 0x0126 #define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB2_RDCLI_GO_PENDING 0x0127 #define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB2_RDCLI_GBLSEND_PENDING 0x0128 #define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB2_RDCLI_TLB_PENDING 0x0129 #define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB2_RDCLI_OARB_PENDING 0x012a #define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB2_RDCLI_OSD_PENDING 0x012b #define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI0 0x012c #define mmDAGB2_WRCLI0_BASE_IDX 1 #define mmDAGB2_WRCLI1 0x012d #define mmDAGB2_WRCLI1_BASE_IDX 1 #define mmDAGB2_WRCLI2 0x012e #define mmDAGB2_WRCLI2_BASE_IDX 1 #define mmDAGB2_WRCLI3 0x012f #define mmDAGB2_WRCLI3_BASE_IDX 1 #define mmDAGB2_WRCLI4 0x0130 #define mmDAGB2_WRCLI4_BASE_IDX 1 #define mmDAGB2_WRCLI5 0x0131 #define mmDAGB2_WRCLI5_BASE_IDX 1 #define mmDAGB2_WRCLI6 0x0132 #define mmDAGB2_WRCLI6_BASE_IDX 1 #define mmDAGB2_WRCLI7 0x0133 #define mmDAGB2_WRCLI7_BASE_IDX 1 #define mmDAGB2_WRCLI8 0x0134 #define mmDAGB2_WRCLI8_BASE_IDX 1 #define mmDAGB2_WRCLI9 0x0135 #define mmDAGB2_WRCLI9_BASE_IDX 1 #define mmDAGB2_WRCLI10 0x0136 #define mmDAGB2_WRCLI10_BASE_IDX 1 #define mmDAGB2_WRCLI11 0x0137 #define mmDAGB2_WRCLI11_BASE_IDX 1 #define mmDAGB2_WRCLI12 0x0138 #define mmDAGB2_WRCLI12_BASE_IDX 1 #define mmDAGB2_WRCLI13 0x0139 #define mmDAGB2_WRCLI13_BASE_IDX 1 #define mmDAGB2_WRCLI14 0x013a #define mmDAGB2_WRCLI14_BASE_IDX 1 #define mmDAGB2_WRCLI15 0x013b #define mmDAGB2_WRCLI15_BASE_IDX 1 #define mmDAGB2_WR_CNTL 0x013c #define mmDAGB2_WR_CNTL_BASE_IDX 1 #define mmDAGB2_WR_GMI_CNTL 0x013d #define mmDAGB2_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB2_WR_ADDR_DAGB 0x013e #define mmDAGB2_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x013f #define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0140 #define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB2_WR_CGTT_CLK_CTRL 0x0141 #define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0142 #define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0143 #define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0144 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0145 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0146 #define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0147 #define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB2_WR_DATA_DAGB 0x0148 #define mmDAGB2_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0x0149 #define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014a #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014b #define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014c #define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB2_WR_VC0_CNTL 0x014d #define mmDAGB2_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC1_CNTL 0x014e #define mmDAGB2_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC2_CNTL 0x014f #define mmDAGB2_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC3_CNTL 0x0150 #define mmDAGB2_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC4_CNTL 0x0151 #define mmDAGB2_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC5_CNTL 0x0152 #define mmDAGB2_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC6_CNTL 0x0153 #define mmDAGB2_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB2_WR_VC7_CNTL 0x0154 #define mmDAGB2_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB2_WR_CNTL_MISC 0x0155 #define mmDAGB2_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB2_WR_TLB_CREDIT 0x0156 #define mmDAGB2_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB2_WR_DATA_CREDIT 0x0157 #define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB2_WR_MISC_CREDIT 0x0158 #define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB2_WRCLI_ASK_PENDING 0x015d #define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_GO_PENDING 0x015e #define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_GBLSEND_PENDING 0x015f #define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_TLB_PENDING 0x0160 #define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_OARB_PENDING 0x0161 #define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_OSD_PENDING 0x0162 #define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_DBUS_ASK_PENDING 0x0163 #define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB2_WRCLI_DBUS_GO_PENDING 0x0164 #define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB2_DAGB_DLY 0x0165 #define mmDAGB2_DAGB_DLY_BASE_IDX 1 #define mmDAGB2_CNTL_MISC 0x0166 #define mmDAGB2_CNTL_MISC_BASE_IDX 1 #define mmDAGB2_CNTL_MISC2 0x0167 #define mmDAGB2_CNTL_MISC2_BASE_IDX 1 #define mmDAGB2_FIFO_EMPTY 0x0168 #define mmDAGB2_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB2_FIFO_FULL 0x0169 #define mmDAGB2_FIFO_FULL_BASE_IDX 1 #define mmDAGB2_WR_CREDITS_FULL 0x016a #define mmDAGB2_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB2_RD_CREDITS_FULL 0x016b #define mmDAGB2_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER_LO 0x016c #define mmDAGB2_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER_HI 0x016d #define mmDAGB2_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER0_CFG 0x016e #define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER1_CFG 0x016f #define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER2_CFG 0x0170 #define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB2_PERFCOUNTER_RSLT_CNTL 0x0171 #define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB2_RESERVE0 0x0172 #define mmDAGB2_RESERVE0_BASE_IDX 1 #define mmDAGB2_RESERVE1 0x0173 #define mmDAGB2_RESERVE1_BASE_IDX 1 #define mmDAGB2_RESERVE2 0x0174 #define mmDAGB2_RESERVE2_BASE_IDX 1 #define mmDAGB2_RESERVE3 0x0175 #define mmDAGB2_RESERVE3_BASE_IDX 1 #define mmDAGB2_RESERVE4 0x0176 #define mmDAGB2_RESERVE4_BASE_IDX 1 #define mmDAGB2_RESERVE5 0x0177 #define mmDAGB2_RESERVE5_BASE_IDX 1 #define mmDAGB2_RESERVE6 0x0178 #define mmDAGB2_RESERVE6_BASE_IDX 1 #define mmDAGB2_RESERVE7 0x0179 #define mmDAGB2_RESERVE7_BASE_IDX 1 #define mmDAGB2_RESERVE8 0x017a #define mmDAGB2_RESERVE8_BASE_IDX 1 #define mmDAGB2_RESERVE9 0x017b #define mmDAGB2_RESERVE9_BASE_IDX 1 #define mmDAGB2_RESERVE10 0x017c #define mmDAGB2_RESERVE10_BASE_IDX 1 #define mmDAGB2_RESERVE11 0x017d #define mmDAGB2_RESERVE11_BASE_IDX 1 #define mmDAGB2_RESERVE12 0x017e #define mmDAGB2_RESERVE12_BASE_IDX 1 #define mmDAGB2_RESERVE13 0x017f #define mmDAGB2_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec3 // base address: 0x68600 #define mmDAGB3_RDCLI0 0x0180 #define mmDAGB3_RDCLI0_BASE_IDX 1 #define mmDAGB3_RDCLI1 0x0181 #define mmDAGB3_RDCLI1_BASE_IDX 1 #define mmDAGB3_RDCLI2 0x0182 #define mmDAGB3_RDCLI2_BASE_IDX 1 #define mmDAGB3_RDCLI3 0x0183 #define mmDAGB3_RDCLI3_BASE_IDX 1 #define mmDAGB3_RDCLI4 0x0184 #define mmDAGB3_RDCLI4_BASE_IDX 1 #define mmDAGB3_RDCLI5 0x0185 #define mmDAGB3_RDCLI5_BASE_IDX 1 #define mmDAGB3_RDCLI6 0x0186 #define mmDAGB3_RDCLI6_BASE_IDX 1 #define mmDAGB3_RDCLI7 0x0187 #define mmDAGB3_RDCLI7_BASE_IDX 1 #define mmDAGB3_RDCLI8 0x0188 #define mmDAGB3_RDCLI8_BASE_IDX 1 #define mmDAGB3_RDCLI9 0x0189 #define mmDAGB3_RDCLI9_BASE_IDX 1 #define mmDAGB3_RDCLI10 0x018a #define mmDAGB3_RDCLI10_BASE_IDX 1 #define mmDAGB3_RDCLI11 0x018b #define mmDAGB3_RDCLI11_BASE_IDX 1 #define mmDAGB3_RDCLI12 0x018c #define mmDAGB3_RDCLI12_BASE_IDX 1 #define mmDAGB3_RDCLI13 0x018d #define mmDAGB3_RDCLI13_BASE_IDX 1 #define mmDAGB3_RDCLI14 0x018e #define mmDAGB3_RDCLI14_BASE_IDX 1 #define mmDAGB3_RDCLI15 0x018f #define mmDAGB3_RDCLI15_BASE_IDX 1 #define mmDAGB3_RD_CNTL 0x0190 #define mmDAGB3_RD_CNTL_BASE_IDX 1 #define mmDAGB3_RD_GMI_CNTL 0x0191 #define mmDAGB3_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB3_RD_ADDR_DAGB 0x0192 #define mmDAGB3_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 #define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 #define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB3_RD_CGTT_CLK_CTRL 0x0195 #define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 #define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 #define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a #define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b #define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB3_RD_VC0_CNTL 0x019c #define mmDAGB3_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC1_CNTL 0x019d #define mmDAGB3_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC2_CNTL 0x019e #define mmDAGB3_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC3_CNTL 0x019f #define mmDAGB3_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC4_CNTL 0x01a0 #define mmDAGB3_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC5_CNTL 0x01a1 #define mmDAGB3_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC6_CNTL 0x01a2 #define mmDAGB3_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB3_RD_VC7_CNTL 0x01a3 #define mmDAGB3_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB3_RD_CNTL_MISC 0x01a4 #define mmDAGB3_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB3_RD_TLB_CREDIT 0x01a5 #define mmDAGB3_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB3_RDCLI_ASK_PENDING 0x01a6 #define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB3_RDCLI_GO_PENDING 0x01a7 #define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB3_RDCLI_GBLSEND_PENDING 0x01a8 #define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB3_RDCLI_TLB_PENDING 0x01a9 #define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB3_RDCLI_OARB_PENDING 0x01aa #define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB3_RDCLI_OSD_PENDING 0x01ab #define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI0 0x01ac #define mmDAGB3_WRCLI0_BASE_IDX 1 #define mmDAGB3_WRCLI1 0x01ad #define mmDAGB3_WRCLI1_BASE_IDX 1 #define mmDAGB3_WRCLI2 0x01ae #define mmDAGB3_WRCLI2_BASE_IDX 1 #define mmDAGB3_WRCLI3 0x01af #define mmDAGB3_WRCLI3_BASE_IDX 1 #define mmDAGB3_WRCLI4 0x01b0 #define mmDAGB3_WRCLI4_BASE_IDX 1 #define mmDAGB3_WRCLI5 0x01b1 #define mmDAGB3_WRCLI5_BASE_IDX 1 #define mmDAGB3_WRCLI6 0x01b2 #define mmDAGB3_WRCLI6_BASE_IDX 1 #define mmDAGB3_WRCLI7 0x01b3 #define mmDAGB3_WRCLI7_BASE_IDX 1 #define mmDAGB3_WRCLI8 0x01b4 #define mmDAGB3_WRCLI8_BASE_IDX 1 #define mmDAGB3_WRCLI9 0x01b5 #define mmDAGB3_WRCLI9_BASE_IDX 1 #define mmDAGB3_WRCLI10 0x01b6 #define mmDAGB3_WRCLI10_BASE_IDX 1 #define mmDAGB3_WRCLI11 0x01b7 #define mmDAGB3_WRCLI11_BASE_IDX 1 #define mmDAGB3_WRCLI12 0x01b8 #define mmDAGB3_WRCLI12_BASE_IDX 1 #define mmDAGB3_WRCLI13 0x01b9 #define mmDAGB3_WRCLI13_BASE_IDX 1 #define mmDAGB3_WRCLI14 0x01ba #define mmDAGB3_WRCLI14_BASE_IDX 1 #define mmDAGB3_WRCLI15 0x01bb #define mmDAGB3_WRCLI15_BASE_IDX 1 #define mmDAGB3_WR_CNTL 0x01bc #define mmDAGB3_WR_CNTL_BASE_IDX 1 #define mmDAGB3_WR_GMI_CNTL 0x01bd #define mmDAGB3_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB3_WR_ADDR_DAGB 0x01be #define mmDAGB3_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01bf #define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c0 #define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB3_WR_CGTT_CLK_CTRL 0x01c1 #define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c2 #define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c3 #define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c4 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c5 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c6 #define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c7 #define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB3_WR_DATA_DAGB 0x01c8 #define mmDAGB3_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01c9 #define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ca #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cb #define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01cc #define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB3_WR_VC0_CNTL 0x01cd #define mmDAGB3_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC1_CNTL 0x01ce #define mmDAGB3_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC2_CNTL 0x01cf #define mmDAGB3_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC3_CNTL 0x01d0 #define mmDAGB3_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC4_CNTL 0x01d1 #define mmDAGB3_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC5_CNTL 0x01d2 #define mmDAGB3_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC6_CNTL 0x01d3 #define mmDAGB3_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB3_WR_VC7_CNTL 0x01d4 #define mmDAGB3_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB3_WR_CNTL_MISC 0x01d5 #define mmDAGB3_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB3_WR_TLB_CREDIT 0x01d6 #define mmDAGB3_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB3_WR_DATA_CREDIT 0x01d7 #define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB3_WR_MISC_CREDIT 0x01d8 #define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB3_WRCLI_ASK_PENDING 0x01dd #define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_GO_PENDING 0x01de #define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_GBLSEND_PENDING 0x01df #define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_TLB_PENDING 0x01e0 #define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_OARB_PENDING 0x01e1 #define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_OSD_PENDING 0x01e2 #define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e3 #define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB3_WRCLI_DBUS_GO_PENDING 0x01e4 #define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB3_DAGB_DLY 0x01e5 #define mmDAGB3_DAGB_DLY_BASE_IDX 1 #define mmDAGB3_CNTL_MISC 0x01e6 #define mmDAGB3_CNTL_MISC_BASE_IDX 1 #define mmDAGB3_CNTL_MISC2 0x01e7 #define mmDAGB3_CNTL_MISC2_BASE_IDX 1 #define mmDAGB3_FIFO_EMPTY 0x01e8 #define mmDAGB3_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB3_FIFO_FULL 0x01e9 #define mmDAGB3_FIFO_FULL_BASE_IDX 1 #define mmDAGB3_WR_CREDITS_FULL 0x01ea #define mmDAGB3_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB3_RD_CREDITS_FULL 0x01eb #define mmDAGB3_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER_LO 0x01ec #define mmDAGB3_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER_HI 0x01ed #define mmDAGB3_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER0_CFG 0x01ee #define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER1_CFG 0x01ef #define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER2_CFG 0x01f0 #define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB3_PERFCOUNTER_RSLT_CNTL 0x01f1 #define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB3_RESERVE0 0x01f2 #define mmDAGB3_RESERVE0_BASE_IDX 1 #define mmDAGB3_RESERVE1 0x01f3 #define mmDAGB3_RESERVE1_BASE_IDX 1 #define mmDAGB3_RESERVE2 0x01f4 #define mmDAGB3_RESERVE2_BASE_IDX 1 #define mmDAGB3_RESERVE3 0x01f5 #define mmDAGB3_RESERVE3_BASE_IDX 1 #define mmDAGB3_RESERVE4 0x01f6 #define mmDAGB3_RESERVE4_BASE_IDX 1 #define mmDAGB3_RESERVE5 0x01f7 #define mmDAGB3_RESERVE5_BASE_IDX 1 #define mmDAGB3_RESERVE6 0x01f8 #define mmDAGB3_RESERVE6_BASE_IDX 1 #define mmDAGB3_RESERVE7 0x01f9 #define mmDAGB3_RESERVE7_BASE_IDX 1 #define mmDAGB3_RESERVE8 0x01fa #define mmDAGB3_RESERVE8_BASE_IDX 1 #define mmDAGB3_RESERVE9 0x01fb #define mmDAGB3_RESERVE9_BASE_IDX 1 #define mmDAGB3_RESERVE10 0x01fc #define mmDAGB3_RESERVE10_BASE_IDX 1 #define mmDAGB3_RESERVE11 0x01fd #define mmDAGB3_RESERVE11_BASE_IDX 1 #define mmDAGB3_RESERVE12 0x01fe #define mmDAGB3_RESERVE12_BASE_IDX 1 #define mmDAGB3_RESERVE13 0x01ff #define mmDAGB3_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec4 // base address: 0x68800 #define mmDAGB4_RDCLI0 0x0200 #define mmDAGB4_RDCLI0_BASE_IDX 1 #define mmDAGB4_RDCLI1 0x0201 #define mmDAGB4_RDCLI1_BASE_IDX 1 #define mmDAGB4_RDCLI2 0x0202 #define mmDAGB4_RDCLI2_BASE_IDX 1 #define mmDAGB4_RDCLI3 0x0203 #define mmDAGB4_RDCLI3_BASE_IDX 1 #define mmDAGB4_RDCLI4 0x0204 #define mmDAGB4_RDCLI4_BASE_IDX 1 #define mmDAGB4_RDCLI5 0x0205 #define mmDAGB4_RDCLI5_BASE_IDX 1 #define mmDAGB4_RDCLI6 0x0206 #define mmDAGB4_RDCLI6_BASE_IDX 1 #define mmDAGB4_RDCLI7 0x0207 #define mmDAGB4_RDCLI7_BASE_IDX 1 #define mmDAGB4_RDCLI8 0x0208 #define mmDAGB4_RDCLI8_BASE_IDX 1 #define mmDAGB4_RDCLI9 0x0209 #define mmDAGB4_RDCLI9_BASE_IDX 1 #define mmDAGB4_RDCLI10 0x020a #define mmDAGB4_RDCLI10_BASE_IDX 1 #define mmDAGB4_RDCLI11 0x020b #define mmDAGB4_RDCLI11_BASE_IDX 1 #define mmDAGB4_RDCLI12 0x020c #define mmDAGB4_RDCLI12_BASE_IDX 1 #define mmDAGB4_RDCLI13 0x020d #define mmDAGB4_RDCLI13_BASE_IDX 1 #define mmDAGB4_RDCLI14 0x020e #define mmDAGB4_RDCLI14_BASE_IDX 1 #define mmDAGB4_RDCLI15 0x020f #define mmDAGB4_RDCLI15_BASE_IDX 1 #define mmDAGB4_RD_CNTL 0x0210 #define mmDAGB4_RD_CNTL_BASE_IDX 1 #define mmDAGB4_RD_GMI_CNTL 0x0211 #define mmDAGB4_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB4_RD_ADDR_DAGB 0x0212 #define mmDAGB4_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 #define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 #define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB4_RD_CGTT_CLK_CTRL 0x0215 #define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 #define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 #define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a #define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b #define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB4_RD_VC0_CNTL 0x021c #define mmDAGB4_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC1_CNTL 0x021d #define mmDAGB4_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC2_CNTL 0x021e #define mmDAGB4_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC3_CNTL 0x021f #define mmDAGB4_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC4_CNTL 0x0220 #define mmDAGB4_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC5_CNTL 0x0221 #define mmDAGB4_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC6_CNTL 0x0222 #define mmDAGB4_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB4_RD_VC7_CNTL 0x0223 #define mmDAGB4_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB4_RD_CNTL_MISC 0x0224 #define mmDAGB4_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB4_RD_TLB_CREDIT 0x0225 #define mmDAGB4_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB4_RDCLI_ASK_PENDING 0x0226 #define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB4_RDCLI_GO_PENDING 0x0227 #define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB4_RDCLI_GBLSEND_PENDING 0x0228 #define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB4_RDCLI_TLB_PENDING 0x0229 #define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB4_RDCLI_OARB_PENDING 0x022a #define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB4_RDCLI_OSD_PENDING 0x022b #define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI0 0x022c #define mmDAGB4_WRCLI0_BASE_IDX 1 #define mmDAGB4_WRCLI1 0x022d #define mmDAGB4_WRCLI1_BASE_IDX 1 #define mmDAGB4_WRCLI2 0x022e #define mmDAGB4_WRCLI2_BASE_IDX 1 #define mmDAGB4_WRCLI3 0x022f #define mmDAGB4_WRCLI3_BASE_IDX 1 #define mmDAGB4_WRCLI4 0x0230 #define mmDAGB4_WRCLI4_BASE_IDX 1 #define mmDAGB4_WRCLI5 0x0231 #define mmDAGB4_WRCLI5_BASE_IDX 1 #define mmDAGB4_WRCLI6 0x0232 #define mmDAGB4_WRCLI6_BASE_IDX 1 #define mmDAGB4_WRCLI7 0x0233 #define mmDAGB4_WRCLI7_BASE_IDX 1 #define mmDAGB4_WRCLI8 0x0234 #define mmDAGB4_WRCLI8_BASE_IDX 1 #define mmDAGB4_WRCLI9 0x0235 #define mmDAGB4_WRCLI9_BASE_IDX 1 #define mmDAGB4_WRCLI10 0x0236 #define mmDAGB4_WRCLI10_BASE_IDX 1 #define mmDAGB4_WRCLI11 0x0237 #define mmDAGB4_WRCLI11_BASE_IDX 1 #define mmDAGB4_WRCLI12 0x0238 #define mmDAGB4_WRCLI12_BASE_IDX 1 #define mmDAGB4_WRCLI13 0x0239 #define mmDAGB4_WRCLI13_BASE_IDX 1 #define mmDAGB4_WRCLI14 0x023a #define mmDAGB4_WRCLI14_BASE_IDX 1 #define mmDAGB4_WRCLI15 0x023b #define mmDAGB4_WRCLI15_BASE_IDX 1 #define mmDAGB4_WR_CNTL 0x023c #define mmDAGB4_WR_CNTL_BASE_IDX 1 #define mmDAGB4_WR_GMI_CNTL 0x023d #define mmDAGB4_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB4_WR_ADDR_DAGB 0x023e #define mmDAGB4_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x023f #define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0240 #define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB4_WR_CGTT_CLK_CTRL 0x0241 #define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0242 #define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0243 #define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0244 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0245 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0246 #define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0247 #define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB4_WR_DATA_DAGB 0x0248 #define mmDAGB4_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0x0249 #define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024a #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024b #define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024c #define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB4_WR_VC0_CNTL 0x024d #define mmDAGB4_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC1_CNTL 0x024e #define mmDAGB4_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC2_CNTL 0x024f #define mmDAGB4_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC3_CNTL 0x0250 #define mmDAGB4_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC4_CNTL 0x0251 #define mmDAGB4_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC5_CNTL 0x0252 #define mmDAGB4_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC6_CNTL 0x0253 #define mmDAGB4_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB4_WR_VC7_CNTL 0x0254 #define mmDAGB4_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB4_WR_CNTL_MISC 0x0255 #define mmDAGB4_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB4_WR_TLB_CREDIT 0x0256 #define mmDAGB4_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB4_WR_DATA_CREDIT 0x0257 #define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB4_WR_MISC_CREDIT 0x0258 #define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB4_WRCLI_ASK_PENDING 0x025d #define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_GO_PENDING 0x025e #define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_GBLSEND_PENDING 0x025f #define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_TLB_PENDING 0x0260 #define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_OARB_PENDING 0x0261 #define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_OSD_PENDING 0x0262 #define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_DBUS_ASK_PENDING 0x0263 #define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB4_WRCLI_DBUS_GO_PENDING 0x0264 #define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB4_DAGB_DLY 0x0265 #define mmDAGB4_DAGB_DLY_BASE_IDX 1 #define mmDAGB4_CNTL_MISC 0x0266 #define mmDAGB4_CNTL_MISC_BASE_IDX 1 #define mmDAGB4_CNTL_MISC2 0x0267 #define mmDAGB4_CNTL_MISC2_BASE_IDX 1 #define mmDAGB4_FIFO_EMPTY 0x0268 #define mmDAGB4_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB4_FIFO_FULL 0x0269 #define mmDAGB4_FIFO_FULL_BASE_IDX 1 #define mmDAGB4_WR_CREDITS_FULL 0x026a #define mmDAGB4_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB4_RD_CREDITS_FULL 0x026b #define mmDAGB4_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER_LO 0x026c #define mmDAGB4_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER_HI 0x026d #define mmDAGB4_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER0_CFG 0x026e #define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER1_CFG 0x026f #define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER2_CFG 0x0270 #define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB4_PERFCOUNTER_RSLT_CNTL 0x0271 #define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB4_RESERVE0 0x0272 #define mmDAGB4_RESERVE0_BASE_IDX 1 #define mmDAGB4_RESERVE1 0x0273 #define mmDAGB4_RESERVE1_BASE_IDX 1 #define mmDAGB4_RESERVE2 0x0274 #define mmDAGB4_RESERVE2_BASE_IDX 1 #define mmDAGB4_RESERVE3 0x0275 #define mmDAGB4_RESERVE3_BASE_IDX 1 #define mmDAGB4_RESERVE4 0x0276 #define mmDAGB4_RESERVE4_BASE_IDX 1 #define mmDAGB4_RESERVE5 0x0277 #define mmDAGB4_RESERVE5_BASE_IDX 1 #define mmDAGB4_RESERVE6 0x0278 #define mmDAGB4_RESERVE6_BASE_IDX 1 #define mmDAGB4_RESERVE7 0x0279 #define mmDAGB4_RESERVE7_BASE_IDX 1 #define mmDAGB4_RESERVE8 0x027a #define mmDAGB4_RESERVE8_BASE_IDX 1 #define mmDAGB4_RESERVE9 0x027b #define mmDAGB4_RESERVE9_BASE_IDX 1 #define mmDAGB4_RESERVE10 0x027c #define mmDAGB4_RESERVE10_BASE_IDX 1 #define mmDAGB4_RESERVE11 0x027d #define mmDAGB4_RESERVE11_BASE_IDX 1 #define mmDAGB4_RESERVE12 0x027e #define mmDAGB4_RESERVE12_BASE_IDX 1 #define mmDAGB4_RESERVE13 0x027f #define mmDAGB4_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec0 // base address: 0x68a00 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0280 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0281 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0282 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0283 #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0284 #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0285 #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA0_DRAM_RD_LAZY 0x0286 #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA0_DRAM_WR_LAZY 0x0287 #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0288 #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0289 #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA0_DRAM_PAGE_BURST 0x028a #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_AGE 0x028b #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_AGE 0x028c #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x028d #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x028e #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_FIXED 0x028f #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0290 #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0291 #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0292 #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0293 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0294 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0295 #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0296 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0297 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0298 #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_GMI_RD_CLI2GRP_MAP0 0x0299 #define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_GMI_RD_CLI2GRP_MAP1 0x029a #define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_GMI_WR_CLI2GRP_MAP0 0x029b #define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_GMI_WR_CLI2GRP_MAP1 0x029c #define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_GMI_RD_GRP2VC_MAP 0x029d #define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA0_GMI_WR_GRP2VC_MAP 0x029e #define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA0_GMI_RD_LAZY 0x029f #define mmMMEA0_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA0_GMI_WR_LAZY 0x02a0 #define mmMMEA0_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA0_GMI_RD_CAM_CNTL 0x02a1 #define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA0_GMI_WR_CAM_CNTL 0x02a2 #define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA0_GMI_PAGE_BURST 0x02a3 #define mmMMEA0_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_AGE 0x02a4 #define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_AGE 0x02a5 #define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_QUEUING 0x02a6 #define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_QUEUING 0x02a7 #define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_FIXED 0x02a8 #define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_FIXED 0x02a9 #define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_URGENCY 0x02aa #define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_URGENCY 0x02ab #define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x02ac #define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x02ad #define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0x02ae #define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0x02af #define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0x02b0 #define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0x02b1 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0x02b2 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0x02b3 #define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x02b4 #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x02b5 #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x02b6 #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x02b7 #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x02b8 #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR2 0x02b9 #define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR2 0x02ba #define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR3 0x02bb #define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR3 0x02bc #define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA0_ADDRNORM_OFFSET_ADDR3 0x02bd #define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR4 0x02be #define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR4 0x02bf #define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA0_ADDRNORM_BASE_ADDR5 0x02c0 #define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR5 0x02c1 #define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA0_ADDRNORM_OFFSET_ADDR5 0x02c2 #define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x02c3 #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0x02c4 #define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x02c5 #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x02c6 #define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA0_ADDRDEC_BANK_CFG 0x02c7 #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA0_ADDRDEC_MISC_CFG 0x02c8 #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x02c9 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x02ca #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x02cb #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x02cc #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x02cd #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x02ce #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x02cf #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x02d0 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x02d1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x02d2 #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x02d3 #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0x02d4 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0x02d5 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0x02d6 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0x02d7 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0x02d8 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0x02d9 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0x02da #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0x02db #define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0x02dc #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0x02dd #define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x02de #define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x02df #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x02e0 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x02e1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x02e2 #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x02e3 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x02e4 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x02e5 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x02e6 #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x02e7 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x02e8 #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x02e9 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x02ea #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x02eb #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x02ec #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x02ed #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x02ee #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x02ef #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x02f0 #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x02f1 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x02f2 #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x02f3 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x02f4 #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x02f5 #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x02f6 #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x02f7 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x02f8 #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x02f9 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x02fa #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x02fb #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x02fc #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x02fd #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x02fe #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x02ff #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0300 #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0301 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0302 #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0303 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0304 #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0305 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0306 #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0307 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0308 #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0309 #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x030a #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x030b #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x030c #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x030d #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x030e #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x030f #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0310 #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0311 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0312 #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0313 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0314 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0315 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0316 #define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0317 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0318 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0319 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x031a #define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x031b #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x031c #define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x031d #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x031e #define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x031f #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x0320 #define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x0321 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x0322 #define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x0323 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x0324 #define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x0325 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x0326 #define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x0327 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x0328 #define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_RM_SEL_CS01 0x0329 #define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_RM_SEL_CS23 0x032a #define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x032b #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x032c #define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x032d #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x032e #define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x0355 #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x0356 #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x0357 #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x0358 #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x0359 #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x035a #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA0_IO_GROUP_BURST 0x035b #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_AGE 0x035c #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_AGE 0x035d #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_QUEUING 0x035e #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_QUEUING 0x035f #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_FIXED 0x0360 #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_FIXED 0x0361 #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_URGENCY 0x0362 #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_URGENCY 0x0363 #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x0364 #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x0365 #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x0366 #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x0367 #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x0368 #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x0369 #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x036a #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x036b #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA0_SDP_ARB_DRAM 0x036c #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA0_SDP_ARB_GMI 0x036d #define mmMMEA0_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA0_SDP_ARB_FINAL 0x036e #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA0_SDP_DRAM_PRIORITY 0x036f #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA0_SDP_GMI_PRIORITY 0x0370 #define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA0_SDP_IO_PRIORITY 0x0371 #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA0_SDP_CREDITS 0x0372 #define mmMMEA0_SDP_CREDITS_BASE_IDX 1 #define mmMMEA0_SDP_TAG_RESERVE0 0x0373 #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA0_SDP_TAG_RESERVE1 0x0374 #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA0_SDP_VCC_RESERVE0 0x0375 #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA0_SDP_VCC_RESERVE1 0x0376 #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA0_SDP_VCD_RESERVE0 0x0377 #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA0_SDP_VCD_RESERVE1 0x0378 #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA0_SDP_REQ_CNTL 0x0379 #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA0_MISC 0x037a #define mmMMEA0_MISC_BASE_IDX 1 #define mmMMEA0_LATENCY_SAMPLING 0x037b #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA0_PERFCOUNTER_LO 0x037c #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA0_PERFCOUNTER_HI 0x037d #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA0_PERFCOUNTER0_CFG 0x037e #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA0_PERFCOUNTER1_CFG 0x037f #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0380 #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA0_EDC_CNT 0x0386 #define mmMMEA0_EDC_CNT_BASE_IDX 1 #define mmMMEA0_EDC_CNT2 0x0387 #define mmMMEA0_EDC_CNT2_BASE_IDX 1 #define mmMMEA0_DSM_CNTL 0x0388 #define mmMMEA0_DSM_CNTL_BASE_IDX 1 #define mmMMEA0_DSM_CNTLA 0x0389 #define mmMMEA0_DSM_CNTLA_BASE_IDX 1 #define mmMMEA0_DSM_CNTLB 0x038a #define mmMMEA0_DSM_CNTLB_BASE_IDX 1 #define mmMMEA0_DSM_CNTL2 0x038b #define mmMMEA0_DSM_CNTL2_BASE_IDX 1 #define mmMMEA0_DSM_CNTL2A 0x038c #define mmMMEA0_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA0_DSM_CNTL2B 0x038d #define mmMMEA0_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA0_CGTT_CLK_CTRL 0x038f #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA0_EDC_MODE 0x0390 #define mmMMEA0_EDC_MODE_BASE_IDX 1 #define mmMMEA0_ERR_STATUS 0x0391 #define mmMMEA0_ERR_STATUS_BASE_IDX 1 #define mmMMEA0_MISC2 0x0392 #define mmMMEA0_MISC2_BASE_IDX 1 #define mmMMEA0_ADDRDEC_SELECT 0x0393 #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA0_EDC_CNT3 0x0394 #define mmMMEA0_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec1 // base address: 0x68f00 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x03c0 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x03c1 #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x03c2 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x03c3 #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x03c4 #define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x03c5 #define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA1_DRAM_RD_LAZY 0x03c6 #define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA1_DRAM_WR_LAZY 0x03c7 #define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA1_DRAM_RD_CAM_CNTL 0x03c8 #define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA1_DRAM_WR_CAM_CNTL 0x03c9 #define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA1_DRAM_PAGE_BURST 0x03ca #define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_AGE 0x03cb #define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_AGE 0x03cc #define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_QUEUING 0x03cd #define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_QUEUING 0x03ce #define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_FIXED 0x03cf #define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_FIXED 0x03d0 #define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_URGENCY 0x03d1 #define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_URGENCY 0x03d2 #define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x03d3 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x03d4 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x03d5 #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x03d6 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x03d7 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x03d8 #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_GMI_RD_CLI2GRP_MAP0 0x03d9 #define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_GMI_RD_CLI2GRP_MAP1 0x03da #define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_GMI_WR_CLI2GRP_MAP0 0x03db #define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_GMI_WR_CLI2GRP_MAP1 0x03dc #define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_GMI_RD_GRP2VC_MAP 0x03dd #define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA1_GMI_WR_GRP2VC_MAP 0x03de #define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA1_GMI_RD_LAZY 0x03df #define mmMMEA1_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA1_GMI_WR_LAZY 0x03e0 #define mmMMEA1_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA1_GMI_RD_CAM_CNTL 0x03e1 #define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA1_GMI_WR_CAM_CNTL 0x03e2 #define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA1_GMI_PAGE_BURST 0x03e3 #define mmMMEA1_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_AGE 0x03e4 #define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_AGE 0x03e5 #define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_QUEUING 0x03e6 #define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_QUEUING 0x03e7 #define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_FIXED 0x03e8 #define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_FIXED 0x03e9 #define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_URGENCY 0x03ea #define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_URGENCY 0x03eb #define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x03ec #define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x03ed #define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0x03ee #define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0x03ef #define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0x03f0 #define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0x03f1 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0x03f2 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0x03f3 #define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR0 0x03f4 #define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x03f5 #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR1 0x03f6 #define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x03f7 #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x03f8 #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR2 0x03f9 #define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR2 0x03fa #define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR3 0x03fb #define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR3 0x03fc #define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA1_ADDRNORM_OFFSET_ADDR3 0x03fd #define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR4 0x03fe #define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR4 0x03ff #define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA1_ADDRNORM_BASE_ADDR5 0x0400 #define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA1_ADDRNORM_LIMIT_ADDR5 0x0401 #define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA1_ADDRNORM_OFFSET_ADDR5 0x0402 #define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0403 #define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0404 #define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0405 #define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0406 #define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA1_ADDRDEC_BANK_CFG 0x0407 #define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA1_ADDRDEC_MISC_CFG 0x0408 #define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0409 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x040a #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x040b #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x040c #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x040d #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0x040e #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x040f #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x0410 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0411 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0412 #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0413 #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0x0414 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0x0415 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0x0416 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0x0417 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0x0418 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0x0419 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0x041a #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0x041b #define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0x041c #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0x041d #define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x041e #define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x041f #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0420 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x0421 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x0422 #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x0423 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x0424 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x0425 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x0426 #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x0427 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x0428 #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x0429 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x042a #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x042b #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x042c #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x042d #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x042e #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x042f #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x0430 #define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x0431 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x0432 #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x0433 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x0434 #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x0435 #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x0436 #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x0437 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x0438 #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x0439 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x043a #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x043b #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x043c #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x043d #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x043e #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x043f #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x0440 #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x0441 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x0442 #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x0443 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x0444 #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x0445 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x0446 #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x0447 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x0448 #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x0449 #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x044a #define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x044b #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x044c #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x044d #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x044e #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x044f #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x0450 #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x0451 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x0452 #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x0453 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x0454 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x0455 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x0456 #define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x0457 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x0458 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x0459 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x045a #define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x045b #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x045c #define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x045d #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x045e #define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x045f #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x0460 #define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x0461 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x0462 #define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x0463 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x0464 #define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x0465 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x0466 #define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x0467 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x0468 #define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_RM_SEL_CS01 0x0469 #define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_RM_SEL_CS23 0x046a #define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x046b #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x046c #define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x046d #define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x046e #define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0495 #define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0496 #define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0497 #define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0498 #define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0499 #define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA1_IO_WR_COMBINE_FLUSH 0x049a #define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA1_IO_GROUP_BURST 0x049b #define mmMMEA1_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_AGE 0x049c #define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_AGE 0x049d #define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_QUEUING 0x049e #define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_QUEUING 0x049f #define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_FIXED 0x04a0 #define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_FIXED 0x04a1 #define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_URGENCY 0x04a2 #define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_URGENCY 0x04a3 #define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0x04a4 #define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0x04a5 #define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x04a6 #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x04a7 #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x04a8 #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x04a9 #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x04aa #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x04ab #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA1_SDP_ARB_DRAM 0x04ac #define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA1_SDP_ARB_GMI 0x04ad #define mmMMEA1_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA1_SDP_ARB_FINAL 0x04ae #define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA1_SDP_DRAM_PRIORITY 0x04af #define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA1_SDP_GMI_PRIORITY 0x04b0 #define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA1_SDP_IO_PRIORITY 0x04b1 #define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA1_SDP_CREDITS 0x04b2 #define mmMMEA1_SDP_CREDITS_BASE_IDX 1 #define mmMMEA1_SDP_TAG_RESERVE0 0x04b3 #define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA1_SDP_TAG_RESERVE1 0x04b4 #define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA1_SDP_VCC_RESERVE0 0x04b5 #define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA1_SDP_VCC_RESERVE1 0x04b6 #define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA1_SDP_VCD_RESERVE0 0x04b7 #define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA1_SDP_VCD_RESERVE1 0x04b8 #define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA1_SDP_REQ_CNTL 0x04b9 #define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA1_MISC 0x04ba #define mmMMEA1_MISC_BASE_IDX 1 #define mmMMEA1_LATENCY_SAMPLING 0x04bb #define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA1_PERFCOUNTER_LO 0x04bc #define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA1_PERFCOUNTER_HI 0x04bd #define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA1_PERFCOUNTER0_CFG 0x04be #define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA1_PERFCOUNTER1_CFG 0x04bf #define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x04c0 #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA1_EDC_CNT 0x04c6 #define mmMMEA1_EDC_CNT_BASE_IDX 1 #define mmMMEA1_EDC_CNT2 0x04c7 #define mmMMEA1_EDC_CNT2_BASE_IDX 1 #define mmMMEA1_DSM_CNTL 0x04c8 #define mmMMEA1_DSM_CNTL_BASE_IDX 1 #define mmMMEA1_DSM_CNTLA 0x04c9 #define mmMMEA1_DSM_CNTLA_BASE_IDX 1 #define mmMMEA1_DSM_CNTLB 0x04ca #define mmMMEA1_DSM_CNTLB_BASE_IDX 1 #define mmMMEA1_DSM_CNTL2 0x04cb #define mmMMEA1_DSM_CNTL2_BASE_IDX 1 #define mmMMEA1_DSM_CNTL2A 0x04cc #define mmMMEA1_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA1_DSM_CNTL2B 0x04cd #define mmMMEA1_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA1_CGTT_CLK_CTRL 0x04cf #define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA1_EDC_MODE 0x04d0 #define mmMMEA1_EDC_MODE_BASE_IDX 1 #define mmMMEA1_ERR_STATUS 0x04d1 #define mmMMEA1_ERR_STATUS_BASE_IDX 1 #define mmMMEA1_MISC2 0x04d2 #define mmMMEA1_MISC2_BASE_IDX 1 #define mmMMEA1_ADDRDEC_SELECT 0x04d3 #define mmMMEA1_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA1_EDC_CNT3 0x04d4 #define mmMMEA1_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec2 // base address: 0x69400 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0500 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0501 #define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0502 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0503 #define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_DRAM_RD_GRP2VC_MAP 0x0504 #define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA2_DRAM_WR_GRP2VC_MAP 0x0505 #define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA2_DRAM_RD_LAZY 0x0506 #define mmMMEA2_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA2_DRAM_WR_LAZY 0x0507 #define mmMMEA2_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA2_DRAM_RD_CAM_CNTL 0x0508 #define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA2_DRAM_WR_CAM_CNTL 0x0509 #define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA2_DRAM_PAGE_BURST 0x050a #define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_AGE 0x050b #define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_AGE 0x050c #define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_QUEUING 0x050d #define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_QUEUING 0x050e #define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_FIXED 0x050f #define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_FIXED 0x0510 #define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_URGENCY 0x0511 #define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_URGENCY 0x0512 #define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0513 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0514 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0515 #define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0516 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0517 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0518 #define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_GMI_RD_CLI2GRP_MAP0 0x0519 #define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_GMI_RD_CLI2GRP_MAP1 0x051a #define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_GMI_WR_CLI2GRP_MAP0 0x051b #define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_GMI_WR_CLI2GRP_MAP1 0x051c #define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_GMI_RD_GRP2VC_MAP 0x051d #define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA2_GMI_WR_GRP2VC_MAP 0x051e #define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA2_GMI_RD_LAZY 0x051f #define mmMMEA2_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA2_GMI_WR_LAZY 0x0520 #define mmMMEA2_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA2_GMI_RD_CAM_CNTL 0x0521 #define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA2_GMI_WR_CAM_CNTL 0x0522 #define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA2_GMI_PAGE_BURST 0x0523 #define mmMMEA2_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_AGE 0x0524 #define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_AGE 0x0525 #define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_QUEUING 0x0526 #define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_QUEUING 0x0527 #define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_FIXED 0x0528 #define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_FIXED 0x0529 #define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_URGENCY 0x052a #define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_URGENCY 0x052b #define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x052c #define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x052d #define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0x052e #define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0x052f #define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0x0530 #define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0x0531 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0x0532 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0x0533 #define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR0 0x0534 #define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR0 0x0535 #define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR1 0x0536 #define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR1 0x0537 #define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA2_ADDRNORM_OFFSET_ADDR1 0x0538 #define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR2 0x0539 #define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR2 0x053a #define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR3 0x053b #define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR3 0x053c #define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA2_ADDRNORM_OFFSET_ADDR3 0x053d #define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR4 0x053e #define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR4 0x053f #define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA2_ADDRNORM_BASE_ADDR5 0x0540 #define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA2_ADDRNORM_LIMIT_ADDR5 0x0541 #define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA2_ADDRNORM_OFFSET_ADDR5 0x0542 #define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x0543 #define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0x0544 #define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0545 #define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0546 #define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA2_ADDRDEC_BANK_CFG 0x0547 #define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA2_ADDRDEC_MISC_CFG 0x0548 #define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0x0549 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0x054a #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0x054b #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0x054c #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0x054d #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0x054e #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0x054f #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0x0550 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0x0551 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0x0552 #define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x0553 #define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0x0554 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0x0555 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0x0556 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0x0557 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0x0558 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0x0559 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0x055a #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0x055b #define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0x055c #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0x055d #define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x055e #define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x055f #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x0560 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x0561 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x0562 #define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x0563 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x0564 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x0565 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x0566 #define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x0567 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x0568 #define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x0569 #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x056a #define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x056b #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x056c #define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x056d #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x056e #define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x056f #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x0570 #define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x0571 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x0572 #define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x0573 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x0574 #define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_RM_SEL_CS01 0x0575 #define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_RM_SEL_CS23 0x0576 #define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x0577 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x0578 #define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x0579 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x057a #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x057b #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x057c #define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x057d #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x057e #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x057f #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0580 #define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0581 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0582 #define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0583 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0584 #define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0585 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0586 #define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0587 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0588 #define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0589 #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x058a #define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x058b #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x058c #define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x058d #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x058e #define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_RM_SEL_CS01 0x058f #define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_RM_SEL_CS23 0x0590 #define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0591 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0592 #define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0593 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0594 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0595 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0596 #define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0597 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0598 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0599 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x059a #define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x059b #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x059c #define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x059d #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x059e #define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x059f #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x05a0 #define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x05a1 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x05a2 #define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x05a3 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x05a4 #define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x05a5 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x05a6 #define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x05a7 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x05a8 #define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_RM_SEL_CS01 0x05a9 #define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_RM_SEL_CS23 0x05aa #define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x05ab #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x05ac #define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x05ad #define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x05ae #define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA2_IO_RD_CLI2GRP_MAP0 0x05d5 #define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_IO_RD_CLI2GRP_MAP1 0x05d6 #define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_IO_WR_CLI2GRP_MAP0 0x05d7 #define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA2_IO_WR_CLI2GRP_MAP1 0x05d8 #define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA2_IO_RD_COMBINE_FLUSH 0x05d9 #define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA2_IO_WR_COMBINE_FLUSH 0x05da #define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA2_IO_GROUP_BURST 0x05db #define mmMMEA2_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_AGE 0x05dc #define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_AGE 0x05dd #define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_QUEUING 0x05de #define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_QUEUING 0x05df #define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_FIXED 0x05e0 #define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_FIXED 0x05e1 #define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_URGENCY 0x05e2 #define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_URGENCY 0x05e3 #define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING 0x05e4 #define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING 0x05e5 #define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_QUANT_PRI1 0x05e6 #define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_QUANT_PRI2 0x05e7 #define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_IO_RD_PRI_QUANT_PRI3 0x05e8 #define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_QUANT_PRI1 0x05e9 #define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_QUANT_PRI2 0x05ea #define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA2_IO_WR_PRI_QUANT_PRI3 0x05eb #define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA2_SDP_ARB_DRAM 0x05ec #define mmMMEA2_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA2_SDP_ARB_GMI 0x05ed #define mmMMEA2_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA2_SDP_ARB_FINAL 0x05ee #define mmMMEA2_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA2_SDP_DRAM_PRIORITY 0x05ef #define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA2_SDP_GMI_PRIORITY 0x05f0 #define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA2_SDP_IO_PRIORITY 0x05f1 #define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA2_SDP_CREDITS 0x05f2 #define mmMMEA2_SDP_CREDITS_BASE_IDX 1 #define mmMMEA2_SDP_TAG_RESERVE0 0x05f3 #define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA2_SDP_TAG_RESERVE1 0x05f4 #define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA2_SDP_VCC_RESERVE0 0x05f5 #define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA2_SDP_VCC_RESERVE1 0x05f6 #define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA2_SDP_VCD_RESERVE0 0x05f7 #define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA2_SDP_VCD_RESERVE1 0x05f8 #define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA2_SDP_REQ_CNTL 0x05f9 #define mmMMEA2_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA2_MISC 0x05fa #define mmMMEA2_MISC_BASE_IDX 1 #define mmMMEA2_LATENCY_SAMPLING 0x05fb #define mmMMEA2_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA2_PERFCOUNTER_LO 0x05fc #define mmMMEA2_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA2_PERFCOUNTER_HI 0x05fd #define mmMMEA2_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA2_PERFCOUNTER0_CFG 0x05fe #define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA2_PERFCOUNTER1_CFG 0x05ff #define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA2_PERFCOUNTER_RSLT_CNTL 0x0600 #define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA2_EDC_CNT 0x0606 #define mmMMEA2_EDC_CNT_BASE_IDX 1 #define mmMMEA2_EDC_CNT2 0x0607 #define mmMMEA2_EDC_CNT2_BASE_IDX 1 #define mmMMEA2_DSM_CNTL 0x0608 #define mmMMEA2_DSM_CNTL_BASE_IDX 1 #define mmMMEA2_DSM_CNTLA 0x0609 #define mmMMEA2_DSM_CNTLA_BASE_IDX 1 #define mmMMEA2_DSM_CNTLB 0x060a #define mmMMEA2_DSM_CNTLB_BASE_IDX 1 #define mmMMEA2_DSM_CNTL2 0x060b #define mmMMEA2_DSM_CNTL2_BASE_IDX 1 #define mmMMEA2_DSM_CNTL2A 0x060c #define mmMMEA2_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA2_DSM_CNTL2B 0x060d #define mmMMEA2_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA2_CGTT_CLK_CTRL 0x060f #define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA2_EDC_MODE 0x0610 #define mmMMEA2_EDC_MODE_BASE_IDX 1 #define mmMMEA2_ERR_STATUS 0x0611 #define mmMMEA2_ERR_STATUS_BASE_IDX 1 #define mmMMEA2_MISC2 0x0612 #define mmMMEA2_MISC2_BASE_IDX 1 #define mmMMEA2_ADDRDEC_SELECT 0x0613 #define mmMMEA2_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA2_EDC_CNT3 0x0614 #define mmMMEA2_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec3 // base address: 0x69900 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0 0x0640 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1 0x0641 #define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0 0x0642 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1 0x0643 #define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_DRAM_RD_GRP2VC_MAP 0x0644 #define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA3_DRAM_WR_GRP2VC_MAP 0x0645 #define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA3_DRAM_RD_LAZY 0x0646 #define mmMMEA3_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA3_DRAM_WR_LAZY 0x0647 #define mmMMEA3_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA3_DRAM_RD_CAM_CNTL 0x0648 #define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA3_DRAM_WR_CAM_CNTL 0x0649 #define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA3_DRAM_PAGE_BURST 0x064a #define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_AGE 0x064b #define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_AGE 0x064c #define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_QUEUING 0x064d #define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_QUEUING 0x064e #define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_FIXED 0x064f #define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_FIXED 0x0650 #define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_URGENCY 0x0651 #define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_URGENCY 0x0652 #define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x0653 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x0654 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x0655 #define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x0656 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x0657 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x0658 #define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_GMI_RD_CLI2GRP_MAP0 0x0659 #define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_GMI_RD_CLI2GRP_MAP1 0x065a #define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_GMI_WR_CLI2GRP_MAP0 0x065b #define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_GMI_WR_CLI2GRP_MAP1 0x065c #define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_GMI_RD_GRP2VC_MAP 0x065d #define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA3_GMI_WR_GRP2VC_MAP 0x065e #define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA3_GMI_RD_LAZY 0x065f #define mmMMEA3_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA3_GMI_WR_LAZY 0x0660 #define mmMMEA3_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA3_GMI_RD_CAM_CNTL 0x0661 #define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA3_GMI_WR_CAM_CNTL 0x0662 #define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA3_GMI_PAGE_BURST 0x0663 #define mmMMEA3_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_AGE 0x0664 #define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_AGE 0x0665 #define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_QUEUING 0x0666 #define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_QUEUING 0x0667 #define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_FIXED 0x0668 #define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_FIXED 0x0669 #define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_URGENCY 0x066a #define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_URGENCY 0x066b #define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x066c #define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x066d #define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1 0x066e #define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2 0x066f #define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3 0x0670 #define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1 0x0671 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2 0x0672 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3 0x0673 #define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR0 0x0674 #define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR0 0x0675 #define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR1 0x0676 #define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR1 0x0677 #define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA3_ADDRNORM_OFFSET_ADDR1 0x0678 #define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR2 0x0679 #define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR2 0x067a #define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR3 0x067b #define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR3 0x067c #define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA3_ADDRNORM_OFFSET_ADDR3 0x067d #define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR4 0x067e #define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR4 0x067f #define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA3_ADDRNORM_BASE_ADDR5 0x0680 #define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA3_ADDRNORM_LIMIT_ADDR5 0x0681 #define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA3_ADDRNORM_OFFSET_ADDR5 0x0682 #define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0683 #define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0684 #define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0685 #define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0686 #define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA3_ADDRDEC_BANK_CFG 0x0687 #define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA3_ADDRDEC_MISC_CFG 0x0688 #define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 0x0689 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 0x068a #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 0x068b #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 0x068c #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 0x068d #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 0x068e #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC 0x068f #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 0x0690 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 0x0691 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 0x0692 #define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0693 #define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 0x0694 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 0x0695 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 0x0696 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 0x0697 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 0x0698 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 0x0699 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC 0x069a #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 0x069b #define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 0x069c #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 0x069d #define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x069e #define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x069f #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x06a0 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x06a1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x06a2 #define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x06a3 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x06a4 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x06a5 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x06a6 #define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x06a7 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x06a8 #define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x06a9 #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x06aa #define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x06ab #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x06ac #define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x06ad #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x06ae #define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x06af #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x06b0 #define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x06b1 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x06b2 #define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x06b3 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x06b4 #define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_RM_SEL_CS01 0x06b5 #define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_RM_SEL_CS23 0x06b6 #define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x06b7 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x06b8 #define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x06b9 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x06ba #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x06bb #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x06bc #define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x06bd #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x06be #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x06bf #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x06c0 #define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x06c1 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x06c2 #define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x06c3 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x06c4 #define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x06c5 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x06c6 #define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x06c7 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x06c8 #define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x06c9 #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x06ca #define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x06cb #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x06cc #define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x06cd #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x06ce #define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_RM_SEL_CS01 0x06cf #define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_RM_SEL_CS23 0x06d0 #define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x06d1 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x06d2 #define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x06d3 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x06d4 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x06d5 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x06d6 #define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x06d7 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x06d8 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x06d9 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x06da #define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x06db #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x06dc #define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x06dd #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x06de #define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x06df #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x06e0 #define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x06e1 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x06e2 #define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x06e3 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x06e4 #define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x06e5 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x06e6 #define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x06e7 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x06e8 #define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_RM_SEL_CS01 0x06e9 #define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_RM_SEL_CS23 0x06ea #define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x06eb #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x06ec #define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x06ed #define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x06ee #define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA3_IO_RD_CLI2GRP_MAP0 0x0715 #define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_IO_RD_CLI2GRP_MAP1 0x0716 #define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_IO_WR_CLI2GRP_MAP0 0x0717 #define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA3_IO_WR_CLI2GRP_MAP1 0x0718 #define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA3_IO_RD_COMBINE_FLUSH 0x0719 #define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA3_IO_WR_COMBINE_FLUSH 0x071a #define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA3_IO_GROUP_BURST 0x071b #define mmMMEA3_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_AGE 0x071c #define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_AGE 0x071d #define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_QUEUING 0x071e #define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_QUEUING 0x071f #define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_FIXED 0x0720 #define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_FIXED 0x0721 #define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_URGENCY 0x0722 #define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_URGENCY 0x0723 #define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING 0x0724 #define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING 0x0725 #define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_QUANT_PRI1 0x0726 #define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_QUANT_PRI2 0x0727 #define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_IO_RD_PRI_QUANT_PRI3 0x0728 #define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_QUANT_PRI1 0x0729 #define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_QUANT_PRI2 0x072a #define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA3_IO_WR_PRI_QUANT_PRI3 0x072b #define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA3_SDP_ARB_DRAM 0x072c #define mmMMEA3_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA3_SDP_ARB_GMI 0x072d #define mmMMEA3_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA3_SDP_ARB_FINAL 0x072e #define mmMMEA3_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA3_SDP_DRAM_PRIORITY 0x072f #define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA3_SDP_GMI_PRIORITY 0x0730 #define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA3_SDP_IO_PRIORITY 0x0731 #define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA3_SDP_CREDITS 0x0732 #define mmMMEA3_SDP_CREDITS_BASE_IDX 1 #define mmMMEA3_SDP_TAG_RESERVE0 0x0733 #define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA3_SDP_TAG_RESERVE1 0x0734 #define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA3_SDP_VCC_RESERVE0 0x0735 #define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA3_SDP_VCC_RESERVE1 0x0736 #define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA3_SDP_VCD_RESERVE0 0x0737 #define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA3_SDP_VCD_RESERVE1 0x0738 #define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA3_SDP_REQ_CNTL 0x0739 #define mmMMEA3_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA3_MISC 0x073a #define mmMMEA3_MISC_BASE_IDX 1 #define mmMMEA3_LATENCY_SAMPLING 0x073b #define mmMMEA3_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA3_PERFCOUNTER_LO 0x073c #define mmMMEA3_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA3_PERFCOUNTER_HI 0x073d #define mmMMEA3_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA3_PERFCOUNTER0_CFG 0x073e #define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA3_PERFCOUNTER1_CFG 0x073f #define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA3_PERFCOUNTER_RSLT_CNTL 0x0740 #define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA3_EDC_CNT 0x0746 #define mmMMEA3_EDC_CNT_BASE_IDX 1 #define mmMMEA3_EDC_CNT2 0x0747 #define mmMMEA3_EDC_CNT2_BASE_IDX 1 #define mmMMEA3_DSM_CNTL 0x0748 #define mmMMEA3_DSM_CNTL_BASE_IDX 1 #define mmMMEA3_DSM_CNTLA 0x0749 #define mmMMEA3_DSM_CNTLA_BASE_IDX 1 #define mmMMEA3_DSM_CNTLB 0x074a #define mmMMEA3_DSM_CNTLB_BASE_IDX 1 #define mmMMEA3_DSM_CNTL2 0x074b #define mmMMEA3_DSM_CNTL2_BASE_IDX 1 #define mmMMEA3_DSM_CNTL2A 0x074c #define mmMMEA3_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA3_DSM_CNTL2B 0x074d #define mmMMEA3_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA3_CGTT_CLK_CTRL 0x074f #define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA3_EDC_MODE 0x0750 #define mmMMEA3_EDC_MODE_BASE_IDX 1 #define mmMMEA3_ERR_STATUS 0x0751 #define mmMMEA3_ERR_STATUS_BASE_IDX 1 #define mmMMEA3_MISC2 0x0752 #define mmMMEA3_MISC2_BASE_IDX 1 #define mmMMEA3_ADDRDEC_SELECT 0x0753 #define mmMMEA3_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA3_EDC_CNT3 0x0754 #define mmMMEA3_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec4 // base address: 0x69e00 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0780 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0781 #define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0782 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0783 #define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_DRAM_RD_GRP2VC_MAP 0x0784 #define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA4_DRAM_WR_GRP2VC_MAP 0x0785 #define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA4_DRAM_RD_LAZY 0x0786 #define mmMMEA4_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA4_DRAM_WR_LAZY 0x0787 #define mmMMEA4_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA4_DRAM_RD_CAM_CNTL 0x0788 #define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA4_DRAM_WR_CAM_CNTL 0x0789 #define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA4_DRAM_PAGE_BURST 0x078a #define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_AGE 0x078b #define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_AGE 0x078c #define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_QUEUING 0x078d #define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_QUEUING 0x078e #define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_FIXED 0x078f #define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_FIXED 0x0790 #define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_URGENCY 0x0791 #define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_URGENCY 0x0792 #define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0793 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0794 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0795 #define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0796 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0797 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0798 #define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_GMI_RD_CLI2GRP_MAP0 0x0799 #define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_GMI_RD_CLI2GRP_MAP1 0x079a #define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_GMI_WR_CLI2GRP_MAP0 0x079b #define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_GMI_WR_CLI2GRP_MAP1 0x079c #define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_GMI_RD_GRP2VC_MAP 0x079d #define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA4_GMI_WR_GRP2VC_MAP 0x079e #define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA4_GMI_RD_LAZY 0x079f #define mmMMEA4_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA4_GMI_WR_LAZY 0x07a0 #define mmMMEA4_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA4_GMI_RD_CAM_CNTL 0x07a1 #define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA4_GMI_WR_CAM_CNTL 0x07a2 #define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA4_GMI_PAGE_BURST 0x07a3 #define mmMMEA4_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_AGE 0x07a4 #define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_AGE 0x07a5 #define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_QUEUING 0x07a6 #define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_QUEUING 0x07a7 #define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_FIXED 0x07a8 #define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_FIXED 0x07a9 #define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_URGENCY 0x07aa #define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_URGENCY 0x07ab #define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x07ac #define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x07ad #define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1 0x07ae #define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2 0x07af #define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3 0x07b0 #define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1 0x07b1 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2 0x07b2 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3 0x07b3 #define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR0 0x07b4 #define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR0 0x07b5 #define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR1 0x07b6 #define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR1 0x07b7 #define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA4_ADDRNORM_OFFSET_ADDR1 0x07b8 #define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR2 0x07b9 #define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR2 0x07ba #define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR3 0x07bb #define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR3 0x07bc #define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA4_ADDRNORM_OFFSET_ADDR3 0x07bd #define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR4 0x07be #define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR4 0x07bf #define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA4_ADDRNORM_BASE_ADDR5 0x07c0 #define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR5 0x07c1 #define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA4_ADDRNORM_OFFSET_ADDR5 0x07c2 #define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x07c3 #define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL 0x07c4 #define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x07c5 #define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x07c6 #define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA4_ADDRDEC_BANK_CFG 0x07c7 #define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA4_ADDRDEC_MISC_CFG 0x07c8 #define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 0x07c9 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 0x07ca #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 0x07cb #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 0x07cc #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 0x07cd #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 0x07ce #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC 0x07cf #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 0x07d0 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 0x07d1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 0x07d2 #define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x07d3 #define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 0x07d4 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 0x07d5 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 0x07d6 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 0x07d7 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 0x07d8 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 0x07d9 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC 0x07da #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 0x07db #define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 0x07dc #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 0x07dd #define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x07de #define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x07df #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x07e0 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x07e1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x07e2 #define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x07e3 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x07e4 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x07e5 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x07e6 #define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x07e7 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x07e8 #define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x07e9 #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x07ea #define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x07eb #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x07ec #define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x07ed #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x07ee #define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x07ef #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x07f0 #define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x07f1 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x07f2 #define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x07f3 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x07f4 #define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_RM_SEL_CS01 0x07f5 #define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_RM_SEL_CS23 0x07f6 #define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x07f7 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x07f8 #define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x07f9 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x07fa #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x07fb #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x07fc #define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x07fd #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x07fe #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x07ff #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0800 #define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0801 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0802 #define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0803 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0804 #define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0805 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0806 #define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0807 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0808 #define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0809 #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x080a #define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x080b #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x080c #define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x080d #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x080e #define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_RM_SEL_CS01 0x080f #define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_RM_SEL_CS23 0x0810 #define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0811 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0812 #define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0813 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0814 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0815 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0816 #define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0817 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0818 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0819 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x081a #define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x081b #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x081c #define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x081d #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x081e #define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x081f #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x0820 #define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x0821 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x0822 #define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x0823 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x0824 #define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x0825 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x0826 #define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x0827 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x0828 #define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_RM_SEL_CS01 0x0829 #define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_RM_SEL_CS23 0x082a #define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x082b #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x082c #define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x082d #define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x082e #define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA4_IO_RD_CLI2GRP_MAP0 0x0855 #define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_IO_RD_CLI2GRP_MAP1 0x0856 #define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_IO_WR_CLI2GRP_MAP0 0x0857 #define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA4_IO_WR_CLI2GRP_MAP1 0x0858 #define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA4_IO_RD_COMBINE_FLUSH 0x0859 #define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA4_IO_WR_COMBINE_FLUSH 0x085a #define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA4_IO_GROUP_BURST 0x085b #define mmMMEA4_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_AGE 0x085c #define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_AGE 0x085d #define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_QUEUING 0x085e #define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_QUEUING 0x085f #define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_FIXED 0x0860 #define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_FIXED 0x0861 #define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_URGENCY 0x0862 #define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_URGENCY 0x0863 #define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING 0x0864 #define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING 0x0865 #define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_QUANT_PRI1 0x0866 #define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_QUANT_PRI2 0x0867 #define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_IO_RD_PRI_QUANT_PRI3 0x0868 #define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_QUANT_PRI1 0x0869 #define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_QUANT_PRI2 0x086a #define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA4_IO_WR_PRI_QUANT_PRI3 0x086b #define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA4_SDP_ARB_DRAM 0x086c #define mmMMEA4_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA4_SDP_ARB_GMI 0x086d #define mmMMEA4_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA4_SDP_ARB_FINAL 0x086e #define mmMMEA4_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA4_SDP_DRAM_PRIORITY 0x086f #define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA4_SDP_GMI_PRIORITY 0x0870 #define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA4_SDP_IO_PRIORITY 0x0871 #define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA4_SDP_CREDITS 0x0872 #define mmMMEA4_SDP_CREDITS_BASE_IDX 1 #define mmMMEA4_SDP_TAG_RESERVE0 0x0873 #define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA4_SDP_TAG_RESERVE1 0x0874 #define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA4_SDP_VCC_RESERVE0 0x0875 #define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA4_SDP_VCC_RESERVE1 0x0876 #define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA4_SDP_VCD_RESERVE0 0x0877 #define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA4_SDP_VCD_RESERVE1 0x0878 #define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA4_SDP_REQ_CNTL 0x0879 #define mmMMEA4_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA4_MISC 0x087a #define mmMMEA4_MISC_BASE_IDX 1 #define mmMMEA4_LATENCY_SAMPLING 0x087b #define mmMMEA4_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA4_PERFCOUNTER_LO 0x087c #define mmMMEA4_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA4_PERFCOUNTER_HI 0x087d #define mmMMEA4_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA4_PERFCOUNTER0_CFG 0x087e #define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA4_PERFCOUNTER1_CFG 0x087f #define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA4_PERFCOUNTER_RSLT_CNTL 0x0880 #define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA4_EDC_CNT 0x0886 #define mmMMEA4_EDC_CNT_BASE_IDX 1 #define mmMMEA4_EDC_CNT2 0x0887 #define mmMMEA4_EDC_CNT2_BASE_IDX 1 #define mmMMEA4_DSM_CNTL 0x0888 #define mmMMEA4_DSM_CNTL_BASE_IDX 1 #define mmMMEA4_DSM_CNTLA 0x0889 #define mmMMEA4_DSM_CNTLA_BASE_IDX 1 #define mmMMEA4_DSM_CNTLB 0x088a #define mmMMEA4_DSM_CNTLB_BASE_IDX 1 #define mmMMEA4_DSM_CNTL2 0x088b #define mmMMEA4_DSM_CNTL2_BASE_IDX 1 #define mmMMEA4_DSM_CNTL2A 0x088c #define mmMMEA4_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA4_DSM_CNTL2B 0x088d #define mmMMEA4_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA4_CGTT_CLK_CTRL 0x088f #define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA4_EDC_MODE 0x0890 #define mmMMEA4_EDC_MODE_BASE_IDX 1 #define mmMMEA4_ERR_STATUS 0x0891 #define mmMMEA4_ERR_STATUS_BASE_IDX 1 #define mmMMEA4_MISC2 0x0892 #define mmMMEA4_MISC2_BASE_IDX 1 #define mmMMEA4_ADDRDEC_SELECT 0x0893 #define mmMMEA4_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA4_EDC_CNT3 0x0894 #define mmMMEA4_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_pctldec0 // base address: 0x6a300 #define mmPCTL0_CTRL 0x08c0 #define mmPCTL0_CTRL_BASE_IDX 1 #define mmPCTL0_MMHUB_DEEPSLEEP_IB 0x08c1 #define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x08c2 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x08c3 #define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 #define mmPCTL0_PG_IGNORE_DEEPSLEEP 0x08c4 #define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x08c5 #define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 #define mmPCTL0_SLICE0_CFG_DAGB_BUSY 0x08c6 #define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL0_SLICE0_CFG_DS_ALLOW 0x08c7 #define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x08c8 #define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL0_SLICE1_CFG_DAGB_BUSY 0x08c9 #define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL0_SLICE1_CFG_DS_ALLOW 0x08ca #define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x08cb #define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL0_SLICE2_CFG_DAGB_BUSY 0x08cc #define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL0_SLICE2_CFG_DS_ALLOW 0x08cd #define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x08ce #define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL0_SLICE3_CFG_DAGB_BUSY 0x08cf #define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL0_SLICE3_CFG_DS_ALLOW 0x08d0 #define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x08d1 #define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL0_SLICE4_CFG_DAGB_BUSY 0x08d2 #define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL0_SLICE4_CFG_DS_ALLOW 0x08d3 #define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x08d4 #define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL0_UTCL2_MISC 0x08d5 #define mmPCTL0_UTCL2_MISC_BASE_IDX 1 #define mmPCTL0_SLICE0_MISC 0x08d6 #define mmPCTL0_SLICE0_MISC_BASE_IDX 1 #define mmPCTL0_SLICE1_MISC 0x08d7 #define mmPCTL0_SLICE1_MISC_BASE_IDX 1 #define mmPCTL0_SLICE2_MISC 0x08d8 #define mmPCTL0_SLICE2_MISC_BASE_IDX 1 #define mmPCTL0_SLICE3_MISC 0x08d9 #define mmPCTL0_SLICE3_MISC_BASE_IDX 1 #define mmPCTL0_SLICE4_MISC 0x08da #define mmPCTL0_SLICE4_MISC_BASE_IDX 1 #define mmPCTL0_UTCL2_RENG_EXECUTE 0x08db #define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_SLICE0_RENG_EXECUTE 0x08dc #define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_SLICE1_RENG_EXECUTE 0x08dd #define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_SLICE2_RENG_EXECUTE 0x08de #define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_SLICE3_RENG_EXECUTE 0x08df #define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_SLICE4_RENG_EXECUTE 0x08e0 #define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL0_UTCL2_RENG_RAM_INDEX 0x08e1 #define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_UTCL2_RENG_RAM_DATA 0x08e2 #define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_SLICE0_RENG_RAM_INDEX 0x08e3 #define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_SLICE0_RENG_RAM_DATA 0x08e4 #define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_SLICE1_RENG_RAM_INDEX 0x08e5 #define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_SLICE1_RENG_RAM_DATA 0x08e6 #define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_SLICE2_RENG_RAM_INDEX 0x08e7 #define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_SLICE2_RENG_RAM_DATA 0x08e8 #define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_SLICE3_RENG_RAM_INDEX 0x08e9 #define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_SLICE3_RENG_RAM_DATA 0x08ea #define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_SLICE4_RENG_RAM_INDEX 0x08eb #define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL0_SLICE4_RENG_RAM_DATA 0x08ec #define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x08ed #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x08ee #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x08ef #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x08f0 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x08f1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f2 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08f3 #define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x08f4 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x08f5 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x08f6 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x08f7 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x08f8 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f9 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08fa #define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x08fb #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x08fc #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x08fd #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x08fe #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x08ff #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0900 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0901 #define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x0902 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x0903 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x0904 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x0905 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x0906 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0907 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0908 #define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x0909 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x090a #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x090b #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x090c #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x090d #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x090e #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x090f #define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x0910 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x0911 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x0912 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x0913 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x0914 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0915 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0916 #define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1dec // base address: 0x6a500 #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS 0x0948 #define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS 0x0949 #define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS 0x094a #define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS 0x094b #define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS 0x094c #define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS 0x094d #define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS 0x094e #define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS 0x094f #define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1pldec // base address: 0x6a580 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x0960 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x0961 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x0962 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x0963 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0964 #define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1prdec // base address: 0x6a5c0 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 0x0970 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 0x0971 #define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2dec // base address: 0x6a600 #define mmATCL2_0_ATC_L2_CNTL 0x0980 #define mmATCL2_0_ATC_L2_CNTL_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CNTL2 0x0981 #define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_DATA0 0x0984 #define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_DATA1 0x0985 #define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_DATA2 0x0986 #define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CNTL3 0x0987 #define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX 1 #define mmATCL2_0_ATC_L2_STATUS 0x0988 #define mmATCL2_0_ATC_L2_STATUS_BASE_IDX 1 #define mmATCL2_0_ATC_L2_STATUS2 0x0989 #define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX 1 #define mmATCL2_0_ATC_L2_STATUS3 0x098a #define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX 1 #define mmATCL2_0_ATC_L2_MISC_CG 0x098b #define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX 1 #define mmATCL2_0_ATC_L2_MEM_POWER_LS 0x098c #define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL 0x098d #define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 0x098e #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 0x098f #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 0x0990 #define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 0x0991 #define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 #define mmATCL2_0_ATC_L2_CNTL4 0x0992 #define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX 1 #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 0x0993 #define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2pfdec // base address: 0x6a700 #define mmVML2PF0_VM_L2_CNTL 0x09c0 #define mmVML2PF0_VM_L2_CNTL_BASE_IDX 1 #define mmVML2PF0_VM_L2_CNTL2 0x09c1 #define mmVML2PF0_VM_L2_CNTL2_BASE_IDX 1 #define mmVML2PF0_VM_L2_CNTL3 0x09c2 #define mmVML2PF0_VM_L2_CNTL3_BASE_IDX 1 #define mmVML2PF0_VM_L2_STATUS 0x09c3 #define mmVML2PF0_VM_L2_STATUS_BASE_IDX 1 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 0x09c4 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x09c5 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x09c6 #define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL 0x09c7 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 0x09c8 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x09c9 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x09ca #define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS 0x09cb #define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x09cc #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x09cd #define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x09ce #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x09cf #define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x09d1 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x09d2 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x09d3 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x09d4 #define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x09d5 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x09d6 #define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 #define mmVML2PF0_VM_L2_CNTL4 0x09d7 #define mmVML2PF0_VM_L2_CNTL4_BASE_IDX 1 #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES 0x09d8 #define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 0x09d9 #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 0x09da #define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL 0x09db #define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL 0x09de #define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2vcdec // base address: 0x6a800 #define mmVML2VC0_VM_CONTEXT0_CNTL 0x0a00 #define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_CNTL 0x0a01 #define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_CNTL 0x0a02 #define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_CNTL 0x0a03 #define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_CNTL 0x0a04 #define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_CNTL 0x0a05 #define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_CNTL 0x0a06 #define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_CNTL 0x0a07 #define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_CNTL 0x0a08 #define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_CNTL 0x0a09 #define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_CNTL 0x0a0a #define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_CNTL 0x0a0b #define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_CNTL 0x0a0c #define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_CNTL 0x0a0d #define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_CNTL 0x0a0e #define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_CNTL 0x0a0f #define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXTS_DISABLE 0x0a10 #define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM 0x0a11 #define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM 0x0a12 #define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM 0x0a13 #define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM 0x0a14 #define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM 0x0a15 #define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM 0x0a16 #define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM 0x0a17 #define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM 0x0a18 #define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM 0x0a19 #define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM 0x0a1a #define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM 0x0a1b #define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM 0x0a1c #define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM 0x0a1d #define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM 0x0a1e #define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM 0x0a1f #define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM 0x0a20 #define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM 0x0a21 #define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM 0x0a22 #define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ 0x0a23 #define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ 0x0a24 #define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ 0x0a25 #define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ 0x0a26 #define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ 0x0a27 #define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ 0x0a28 #define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ 0x0a29 #define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ 0x0a2a #define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ 0x0a2b #define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ 0x0a2c #define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ 0x0a2d #define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ 0x0a2e #define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ 0x0a2f #define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ 0x0a30 #define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ 0x0a31 #define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ 0x0a32 #define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ 0x0a33 #define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ 0x0a34 #define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK 0x0a35 #define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK 0x0a36 #define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK 0x0a37 #define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK 0x0a38 #define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK 0x0a39 #define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK 0x0a3a #define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK 0x0a3b #define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK 0x0a3c #define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK 0x0a3d #define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK 0x0a3e #define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK 0x0a3f #define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK 0x0a40 #define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK 0x0a41 #define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK 0x0a42 #define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK 0x0a43 #define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK 0x0a44 #define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK 0x0a45 #define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK 0x0a46 #define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a47 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a48 #define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a49 #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a4a #define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a4b #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a4c #define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a4d #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a4e #define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a4f #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a50 #define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a51 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a52 #define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a53 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a54 #define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a55 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a56 #define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a57 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a58 #define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a59 #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a5a #define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a5b #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a5c #define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5d #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5e #define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a5f #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a60 #define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a61 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a62 #define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a63 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a64 #define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a65 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a66 #define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a67 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a68 #define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a69 #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a6a #define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0a6b #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0a6c #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0a6d #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0a6e #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0a6f #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0a70 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0a71 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0a72 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0a73 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0a74 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0a75 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0a76 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0a77 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0a78 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0a79 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0a7a #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0a7b #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0a7c #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0a7d #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0a7e #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0a7f #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0a80 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0a81 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0a82 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0a83 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0a84 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0a85 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0a86 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0a87 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0a88 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0a89 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0a8a #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0a8b #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0a8c #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0a8d #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0a8e #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0a8f #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0a90 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0a91 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0a92 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0a93 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0a94 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0a95 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0a96 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0a97 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0a98 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0a99 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0a9a #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0a9b #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0a9c #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0a9d #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0a9e #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0a9f #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0aa0 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0aa1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0aa2 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0aa3 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0aa4 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0aa5 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0aa6 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0aa7 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0aa8 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0aa9 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0aaa #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0aab #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0aac #define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0aad #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0aae #define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0aaf #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0ab0 #define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0ab1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0ab2 #define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0ab3 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0ab4 #define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0ab5 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0ab6 #define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0ab7 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0ab8 #define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0ab9 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0aba #define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0abb #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0abc #define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0abd #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0abe #define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0abf #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0ac0 #define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0ac1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0ac2 #define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0ac3 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0ac4 #define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0ac5 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0ac6 #define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0ac7 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0ac8 #define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0ac9 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0aca #define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6ab90 #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE 0x0ae4 #define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT 0x0ae5 #define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL 0x0ae6 #define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB 0x0ae7 #define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x0ae8 #define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x0ae9 #define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x0aea #define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_FB_OFFSET 0x0aeb #define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0aec #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0aed #define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_STEERING 0x0aee #define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX 1 #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 0x0aef #define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 #define mmVMSHAREDPF0_MC_MEM_POWER_LS 0x0af0 #define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0af1 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0af2 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_APT_CNTL 0x0af3 #define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 0x0af4 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 0x0af5 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0af6 #define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 0x0af7 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 0x0af8 #define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0x0af9 #define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 #define mmMC_VM_XGMI_LFB_CNTL 0x0823 #define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 #define mmMC_VM_XGMI_LFB_SIZE 0x0824 #define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedvcdec // base address: 0x6ac00 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE 0x0b00 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP 0x0b01 #define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_AGP_TOP 0x0b02 #define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_AGP_BOT 0x0b03 #define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_AGP_BASE 0x0b04 #define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0b05 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0b06 #define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0x0b07 #define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vmsharedhvdec // base address: 0x6ac80 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 0x0b20 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 0x0b21 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 0x0b22 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 0x0b23 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 0x0b24 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 0x0b25 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 0x0b26 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 0x0b27 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 0x0b28 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 0x0b29 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 0x0b2a #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 0x0b2b #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 0x0b2c #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 0x0b2d #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 0x0b2e #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 0x0b2f #define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 0x0b30 #define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 0x0b31 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 0x0b32 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 0x0b33 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 0x0b34 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 0x0b35 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 0x0b36 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 0x0b37 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 0x0b38 #define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 0x0b39 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 0x0b3a #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 0x0b3b #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 0x0b3c #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 0x0b3d #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 0x0b3e #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 0x0b3f #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 0x0b40 #define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 0x0b41 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 0x0b42 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 0x0b43 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 0x0b44 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 0x0b45 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 0x0b46 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 0x0b47 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 0x0b48 #define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 0x0b49 #define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0b4a #define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL 0x0b4b #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 0x0b4c #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 0x0b4d #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 0x0b4e #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 0x0b4f #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 0x0b50 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 0x0b51 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 0x0b52 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 0x0b53 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 0x0b54 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 0x0b55 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 0x0b56 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 0x0b57 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 0x0b58 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 0x0b59 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 0x0b5a #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 0x0b5b #define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 0x0b5c #define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 0x0b5d #define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 0x0b5e #define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2pfcntrdec // base address: 0x6adc0 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 0x0b70 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 0x0b71 #define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2pfcntldec // base address: 0x6add0 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 0x0b74 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 0x0b75 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x0b76 #define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2pldec // base address: 0x6ae00 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 0x0b80 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 0x0b81 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 0x0b82 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 0x0b83 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 0x0b84 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 0x0b85 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 0x0b86 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 0x0b87 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0b88 #define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2prdec // base address: 0x6ae40 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO 0x0b90 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI 0x0b91 #define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec5 // base address: 0x74000 #define mmDAGB5_RDCLI0 0x3000 #define mmDAGB5_RDCLI0_BASE_IDX 1 #define mmDAGB5_RDCLI1 0x3001 #define mmDAGB5_RDCLI1_BASE_IDX 1 #define mmDAGB5_RDCLI2 0x3002 #define mmDAGB5_RDCLI2_BASE_IDX 1 #define mmDAGB5_RDCLI3 0x3003 #define mmDAGB5_RDCLI3_BASE_IDX 1 #define mmDAGB5_RDCLI4 0x3004 #define mmDAGB5_RDCLI4_BASE_IDX 1 #define mmDAGB5_RDCLI5 0x3005 #define mmDAGB5_RDCLI5_BASE_IDX 1 #define mmDAGB5_RDCLI6 0x3006 #define mmDAGB5_RDCLI6_BASE_IDX 1 #define mmDAGB5_RDCLI7 0x3007 #define mmDAGB5_RDCLI7_BASE_IDX 1 #define mmDAGB5_RDCLI8 0x3008 #define mmDAGB5_RDCLI8_BASE_IDX 1 #define mmDAGB5_RDCLI9 0x3009 #define mmDAGB5_RDCLI9_BASE_IDX 1 #define mmDAGB5_RDCLI10 0x300a #define mmDAGB5_RDCLI10_BASE_IDX 1 #define mmDAGB5_RDCLI11 0x300b #define mmDAGB5_RDCLI11_BASE_IDX 1 #define mmDAGB5_RDCLI12 0x300c #define mmDAGB5_RDCLI12_BASE_IDX 1 #define mmDAGB5_RDCLI13 0x300d #define mmDAGB5_RDCLI13_BASE_IDX 1 #define mmDAGB5_RDCLI14 0x300e #define mmDAGB5_RDCLI14_BASE_IDX 1 #define mmDAGB5_RDCLI15 0x300f #define mmDAGB5_RDCLI15_BASE_IDX 1 #define mmDAGB5_RD_CNTL 0x3010 #define mmDAGB5_RD_CNTL_BASE_IDX 1 #define mmDAGB5_RD_GMI_CNTL 0x3011 #define mmDAGB5_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB5_RD_ADDR_DAGB 0x3012 #define mmDAGB5_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x3013 #define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x3014 #define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB5_RD_CGTT_CLK_CTRL 0x3015 #define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x3016 #define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x3017 #define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x3018 #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x3019 #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x301a #define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x301b #define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB5_RD_VC0_CNTL 0x301c #define mmDAGB5_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC1_CNTL 0x301d #define mmDAGB5_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC2_CNTL 0x301e #define mmDAGB5_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC3_CNTL 0x301f #define mmDAGB5_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC4_CNTL 0x3020 #define mmDAGB5_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC5_CNTL 0x3021 #define mmDAGB5_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC6_CNTL 0x3022 #define mmDAGB5_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB5_RD_VC7_CNTL 0x3023 #define mmDAGB5_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB5_RD_CNTL_MISC 0x3024 #define mmDAGB5_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB5_RD_TLB_CREDIT 0x3025 #define mmDAGB5_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB5_RDCLI_ASK_PENDING 0x3026 #define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB5_RDCLI_GO_PENDING 0x3027 #define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB5_RDCLI_GBLSEND_PENDING 0x3028 #define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB5_RDCLI_TLB_PENDING 0x3029 #define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB5_RDCLI_OARB_PENDING 0x302a #define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB5_RDCLI_OSD_PENDING 0x302b #define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI0 0x302c #define mmDAGB5_WRCLI0_BASE_IDX 1 #define mmDAGB5_WRCLI1 0x302d #define mmDAGB5_WRCLI1_BASE_IDX 1 #define mmDAGB5_WRCLI2 0x302e #define mmDAGB5_WRCLI2_BASE_IDX 1 #define mmDAGB5_WRCLI3 0x302f #define mmDAGB5_WRCLI3_BASE_IDX 1 #define mmDAGB5_WRCLI4 0x3030 #define mmDAGB5_WRCLI4_BASE_IDX 1 #define mmDAGB5_WRCLI5 0x3031 #define mmDAGB5_WRCLI5_BASE_IDX 1 #define mmDAGB5_WRCLI6 0x3032 #define mmDAGB5_WRCLI6_BASE_IDX 1 #define mmDAGB5_WRCLI7 0x3033 #define mmDAGB5_WRCLI7_BASE_IDX 1 #define mmDAGB5_WRCLI8 0x3034 #define mmDAGB5_WRCLI8_BASE_IDX 1 #define mmDAGB5_WRCLI9 0x3035 #define mmDAGB5_WRCLI9_BASE_IDX 1 #define mmDAGB5_WRCLI10 0x3036 #define mmDAGB5_WRCLI10_BASE_IDX 1 #define mmDAGB5_WRCLI11 0x3037 #define mmDAGB5_WRCLI11_BASE_IDX 1 #define mmDAGB5_WRCLI12 0x3038 #define mmDAGB5_WRCLI12_BASE_IDX 1 #define mmDAGB5_WRCLI13 0x3039 #define mmDAGB5_WRCLI13_BASE_IDX 1 #define mmDAGB5_WRCLI14 0x303a #define mmDAGB5_WRCLI14_BASE_IDX 1 #define mmDAGB5_WRCLI15 0x303b #define mmDAGB5_WRCLI15_BASE_IDX 1 #define mmDAGB5_WR_CNTL 0x303c #define mmDAGB5_WR_CNTL_BASE_IDX 1 #define mmDAGB5_WR_GMI_CNTL 0x303d #define mmDAGB5_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB5_WR_ADDR_DAGB 0x303e #define mmDAGB5_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x303f #define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x3040 #define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB5_WR_CGTT_CLK_CTRL 0x3041 #define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x3042 #define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x3043 #define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x3044 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x3045 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x3046 #define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x3047 #define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB5_WR_DATA_DAGB 0x3048 #define mmDAGB5_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0 0x3049 #define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x304a #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1 0x304b #define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x304c #define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB5_WR_VC0_CNTL 0x304d #define mmDAGB5_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC1_CNTL 0x304e #define mmDAGB5_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC2_CNTL 0x304f #define mmDAGB5_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC3_CNTL 0x3050 #define mmDAGB5_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC4_CNTL 0x3051 #define mmDAGB5_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC5_CNTL 0x3052 #define mmDAGB5_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC6_CNTL 0x3053 #define mmDAGB5_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB5_WR_VC7_CNTL 0x3054 #define mmDAGB5_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB5_WR_CNTL_MISC 0x3055 #define mmDAGB5_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB5_WR_TLB_CREDIT 0x3056 #define mmDAGB5_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB5_WR_DATA_CREDIT 0x3057 #define mmDAGB5_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB5_WR_MISC_CREDIT 0x3058 #define mmDAGB5_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB5_WRCLI_ASK_PENDING 0x305d #define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_GO_PENDING 0x305e #define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_GBLSEND_PENDING 0x305f #define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_TLB_PENDING 0x3060 #define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_OARB_PENDING 0x3061 #define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_OSD_PENDING 0x3062 #define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_DBUS_ASK_PENDING 0x3063 #define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB5_WRCLI_DBUS_GO_PENDING 0x3064 #define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB5_DAGB_DLY 0x3065 #define mmDAGB5_DAGB_DLY_BASE_IDX 1 #define mmDAGB5_CNTL_MISC 0x3066 #define mmDAGB5_CNTL_MISC_BASE_IDX 1 #define mmDAGB5_CNTL_MISC2 0x3067 #define mmDAGB5_CNTL_MISC2_BASE_IDX 1 #define mmDAGB5_FIFO_EMPTY 0x3068 #define mmDAGB5_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB5_FIFO_FULL 0x3069 #define mmDAGB5_FIFO_FULL_BASE_IDX 1 #define mmDAGB5_WR_CREDITS_FULL 0x306a #define mmDAGB5_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB5_RD_CREDITS_FULL 0x306b #define mmDAGB5_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER_LO 0x306c #define mmDAGB5_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER_HI 0x306d #define mmDAGB5_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER0_CFG 0x306e #define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER1_CFG 0x306f #define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER2_CFG 0x3070 #define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB5_PERFCOUNTER_RSLT_CNTL 0x3071 #define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB5_RESERVE0 0x3072 #define mmDAGB5_RESERVE0_BASE_IDX 1 #define mmDAGB5_RESERVE1 0x3073 #define mmDAGB5_RESERVE1_BASE_IDX 1 #define mmDAGB5_RESERVE2 0x3074 #define mmDAGB5_RESERVE2_BASE_IDX 1 #define mmDAGB5_RESERVE3 0x3075 #define mmDAGB5_RESERVE3_BASE_IDX 1 #define mmDAGB5_RESERVE4 0x3076 #define mmDAGB5_RESERVE4_BASE_IDX 1 #define mmDAGB5_RESERVE5 0x3077 #define mmDAGB5_RESERVE5_BASE_IDX 1 #define mmDAGB5_RESERVE6 0x3078 #define mmDAGB5_RESERVE6_BASE_IDX 1 #define mmDAGB5_RESERVE7 0x3079 #define mmDAGB5_RESERVE7_BASE_IDX 1 #define mmDAGB5_RESERVE8 0x307a #define mmDAGB5_RESERVE8_BASE_IDX 1 #define mmDAGB5_RESERVE9 0x307b #define mmDAGB5_RESERVE9_BASE_IDX 1 #define mmDAGB5_RESERVE10 0x307c #define mmDAGB5_RESERVE10_BASE_IDX 1 #define mmDAGB5_RESERVE11 0x307d #define mmDAGB5_RESERVE11_BASE_IDX 1 #define mmDAGB5_RESERVE12 0x307e #define mmDAGB5_RESERVE12_BASE_IDX 1 #define mmDAGB5_RESERVE13 0x307f #define mmDAGB5_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec6 // base address: 0x74200 #define mmDAGB6_RDCLI0 0x3080 #define mmDAGB6_RDCLI0_BASE_IDX 1 #define mmDAGB6_RDCLI1 0x3081 #define mmDAGB6_RDCLI1_BASE_IDX 1 #define mmDAGB6_RDCLI2 0x3082 #define mmDAGB6_RDCLI2_BASE_IDX 1 #define mmDAGB6_RDCLI3 0x3083 #define mmDAGB6_RDCLI3_BASE_IDX 1 #define mmDAGB6_RDCLI4 0x3084 #define mmDAGB6_RDCLI4_BASE_IDX 1 #define mmDAGB6_RDCLI5 0x3085 #define mmDAGB6_RDCLI5_BASE_IDX 1 #define mmDAGB6_RDCLI6 0x3086 #define mmDAGB6_RDCLI6_BASE_IDX 1 #define mmDAGB6_RDCLI7 0x3087 #define mmDAGB6_RDCLI7_BASE_IDX 1 #define mmDAGB6_RDCLI8 0x3088 #define mmDAGB6_RDCLI8_BASE_IDX 1 #define mmDAGB6_RDCLI9 0x3089 #define mmDAGB6_RDCLI9_BASE_IDX 1 #define mmDAGB6_RDCLI10 0x308a #define mmDAGB6_RDCLI10_BASE_IDX 1 #define mmDAGB6_RDCLI11 0x308b #define mmDAGB6_RDCLI11_BASE_IDX 1 #define mmDAGB6_RDCLI12 0x308c #define mmDAGB6_RDCLI12_BASE_IDX 1 #define mmDAGB6_RDCLI13 0x308d #define mmDAGB6_RDCLI13_BASE_IDX 1 #define mmDAGB6_RDCLI14 0x308e #define mmDAGB6_RDCLI14_BASE_IDX 1 #define mmDAGB6_RDCLI15 0x308f #define mmDAGB6_RDCLI15_BASE_IDX 1 #define mmDAGB6_RD_CNTL 0x3090 #define mmDAGB6_RD_CNTL_BASE_IDX 1 #define mmDAGB6_RD_GMI_CNTL 0x3091 #define mmDAGB6_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB6_RD_ADDR_DAGB 0x3092 #define mmDAGB6_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST 0x3093 #define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 0x3094 #define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB6_RD_CGTT_CLK_CTRL 0x3095 #define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL 0x3096 #define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL 0x3097 #define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 0x3098 #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 0x3099 #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 0x309a #define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 0x309b #define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB6_RD_VC0_CNTL 0x309c #define mmDAGB6_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC1_CNTL 0x309d #define mmDAGB6_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC2_CNTL 0x309e #define mmDAGB6_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC3_CNTL 0x309f #define mmDAGB6_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC4_CNTL 0x30a0 #define mmDAGB6_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC5_CNTL 0x30a1 #define mmDAGB6_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC6_CNTL 0x30a2 #define mmDAGB6_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB6_RD_VC7_CNTL 0x30a3 #define mmDAGB6_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB6_RD_CNTL_MISC 0x30a4 #define mmDAGB6_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB6_RD_TLB_CREDIT 0x30a5 #define mmDAGB6_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB6_RDCLI_ASK_PENDING 0x30a6 #define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB6_RDCLI_GO_PENDING 0x30a7 #define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB6_RDCLI_GBLSEND_PENDING 0x30a8 #define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB6_RDCLI_TLB_PENDING 0x30a9 #define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB6_RDCLI_OARB_PENDING 0x30aa #define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB6_RDCLI_OSD_PENDING 0x30ab #define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI0 0x30ac #define mmDAGB6_WRCLI0_BASE_IDX 1 #define mmDAGB6_WRCLI1 0x30ad #define mmDAGB6_WRCLI1_BASE_IDX 1 #define mmDAGB6_WRCLI2 0x30ae #define mmDAGB6_WRCLI2_BASE_IDX 1 #define mmDAGB6_WRCLI3 0x30af #define mmDAGB6_WRCLI3_BASE_IDX 1 #define mmDAGB6_WRCLI4 0x30b0 #define mmDAGB6_WRCLI4_BASE_IDX 1 #define mmDAGB6_WRCLI5 0x30b1 #define mmDAGB6_WRCLI5_BASE_IDX 1 #define mmDAGB6_WRCLI6 0x30b2 #define mmDAGB6_WRCLI6_BASE_IDX 1 #define mmDAGB6_WRCLI7 0x30b3 #define mmDAGB6_WRCLI7_BASE_IDX 1 #define mmDAGB6_WRCLI8 0x30b4 #define mmDAGB6_WRCLI8_BASE_IDX 1 #define mmDAGB6_WRCLI9 0x30b5 #define mmDAGB6_WRCLI9_BASE_IDX 1 #define mmDAGB6_WRCLI10 0x30b6 #define mmDAGB6_WRCLI10_BASE_IDX 1 #define mmDAGB6_WRCLI11 0x30b7 #define mmDAGB6_WRCLI11_BASE_IDX 1 #define mmDAGB6_WRCLI12 0x30b8 #define mmDAGB6_WRCLI12_BASE_IDX 1 #define mmDAGB6_WRCLI13 0x30b9 #define mmDAGB6_WRCLI13_BASE_IDX 1 #define mmDAGB6_WRCLI14 0x30ba #define mmDAGB6_WRCLI14_BASE_IDX 1 #define mmDAGB6_WRCLI15 0x30bb #define mmDAGB6_WRCLI15_BASE_IDX 1 #define mmDAGB6_WR_CNTL 0x30bc #define mmDAGB6_WR_CNTL_BASE_IDX 1 #define mmDAGB6_WR_GMI_CNTL 0x30bd #define mmDAGB6_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB6_WR_ADDR_DAGB 0x30be #define mmDAGB6_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST 0x30bf #define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 0x30c0 #define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB6_WR_CGTT_CLK_CTRL 0x30c1 #define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL 0x30c2 #define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL 0x30c3 #define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 0x30c4 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 0x30c5 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 0x30c6 #define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 0x30c7 #define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB6_WR_DATA_DAGB 0x30c8 #define mmDAGB6_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0 0x30c9 #define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 0x30ca #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1 0x30cb #define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 0x30cc #define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB6_WR_VC0_CNTL 0x30cd #define mmDAGB6_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC1_CNTL 0x30ce #define mmDAGB6_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC2_CNTL 0x30cf #define mmDAGB6_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC3_CNTL 0x30d0 #define mmDAGB6_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC4_CNTL 0x30d1 #define mmDAGB6_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC5_CNTL 0x30d2 #define mmDAGB6_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC6_CNTL 0x30d3 #define mmDAGB6_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB6_WR_VC7_CNTL 0x30d4 #define mmDAGB6_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB6_WR_CNTL_MISC 0x30d5 #define mmDAGB6_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB6_WR_TLB_CREDIT 0x30d6 #define mmDAGB6_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB6_WR_DATA_CREDIT 0x30d7 #define mmDAGB6_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB6_WR_MISC_CREDIT 0x30d8 #define mmDAGB6_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB6_WRCLI_ASK_PENDING 0x30dd #define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_GO_PENDING 0x30de #define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_GBLSEND_PENDING 0x30df #define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_TLB_PENDING 0x30e0 #define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_OARB_PENDING 0x30e1 #define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_OSD_PENDING 0x30e2 #define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_DBUS_ASK_PENDING 0x30e3 #define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB6_WRCLI_DBUS_GO_PENDING 0x30e4 #define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB6_DAGB_DLY 0x30e5 #define mmDAGB6_DAGB_DLY_BASE_IDX 1 #define mmDAGB6_CNTL_MISC 0x30e6 #define mmDAGB6_CNTL_MISC_BASE_IDX 1 #define mmDAGB6_CNTL_MISC2 0x30e7 #define mmDAGB6_CNTL_MISC2_BASE_IDX 1 #define mmDAGB6_FIFO_EMPTY 0x30e8 #define mmDAGB6_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB6_FIFO_FULL 0x30e9 #define mmDAGB6_FIFO_FULL_BASE_IDX 1 #define mmDAGB6_WR_CREDITS_FULL 0x30ea #define mmDAGB6_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB6_RD_CREDITS_FULL 0x30eb #define mmDAGB6_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER_LO 0x30ec #define mmDAGB6_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER_HI 0x30ed #define mmDAGB6_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER0_CFG 0x30ee #define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER1_CFG 0x30ef #define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER2_CFG 0x30f0 #define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB6_PERFCOUNTER_RSLT_CNTL 0x30f1 #define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB6_RESERVE0 0x30f2 #define mmDAGB6_RESERVE0_BASE_IDX 1 #define mmDAGB6_RESERVE1 0x30f3 #define mmDAGB6_RESERVE1_BASE_IDX 1 #define mmDAGB6_RESERVE2 0x30f4 #define mmDAGB6_RESERVE2_BASE_IDX 1 #define mmDAGB6_RESERVE3 0x30f5 #define mmDAGB6_RESERVE3_BASE_IDX 1 #define mmDAGB6_RESERVE4 0x30f6 #define mmDAGB6_RESERVE4_BASE_IDX 1 #define mmDAGB6_RESERVE5 0x30f7 #define mmDAGB6_RESERVE5_BASE_IDX 1 #define mmDAGB6_RESERVE6 0x30f8 #define mmDAGB6_RESERVE6_BASE_IDX 1 #define mmDAGB6_RESERVE7 0x30f9 #define mmDAGB6_RESERVE7_BASE_IDX 1 #define mmDAGB6_RESERVE8 0x30fa #define mmDAGB6_RESERVE8_BASE_IDX 1 #define mmDAGB6_RESERVE9 0x30fb #define mmDAGB6_RESERVE9_BASE_IDX 1 #define mmDAGB6_RESERVE10 0x30fc #define mmDAGB6_RESERVE10_BASE_IDX 1 #define mmDAGB6_RESERVE11 0x30fd #define mmDAGB6_RESERVE11_BASE_IDX 1 #define mmDAGB6_RESERVE12 0x30fe #define mmDAGB6_RESERVE12_BASE_IDX 1 #define mmDAGB6_RESERVE13 0x30ff #define mmDAGB6_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_dagb_dagbdec7 // base address: 0x74400 #define mmDAGB7_RDCLI0 0x3100 #define mmDAGB7_RDCLI0_BASE_IDX 1 #define mmDAGB7_RDCLI1 0x3101 #define mmDAGB7_RDCLI1_BASE_IDX 1 #define mmDAGB7_RDCLI2 0x3102 #define mmDAGB7_RDCLI2_BASE_IDX 1 #define mmDAGB7_RDCLI3 0x3103 #define mmDAGB7_RDCLI3_BASE_IDX 1 #define mmDAGB7_RDCLI4 0x3104 #define mmDAGB7_RDCLI4_BASE_IDX 1 #define mmDAGB7_RDCLI5 0x3105 #define mmDAGB7_RDCLI5_BASE_IDX 1 #define mmDAGB7_RDCLI6 0x3106 #define mmDAGB7_RDCLI6_BASE_IDX 1 #define mmDAGB7_RDCLI7 0x3107 #define mmDAGB7_RDCLI7_BASE_IDX 1 #define mmDAGB7_RDCLI8 0x3108 #define mmDAGB7_RDCLI8_BASE_IDX 1 #define mmDAGB7_RDCLI9 0x3109 #define mmDAGB7_RDCLI9_BASE_IDX 1 #define mmDAGB7_RDCLI10 0x310a #define mmDAGB7_RDCLI10_BASE_IDX 1 #define mmDAGB7_RDCLI11 0x310b #define mmDAGB7_RDCLI11_BASE_IDX 1 #define mmDAGB7_RDCLI12 0x310c #define mmDAGB7_RDCLI12_BASE_IDX 1 #define mmDAGB7_RDCLI13 0x310d #define mmDAGB7_RDCLI13_BASE_IDX 1 #define mmDAGB7_RDCLI14 0x310e #define mmDAGB7_RDCLI14_BASE_IDX 1 #define mmDAGB7_RDCLI15 0x310f #define mmDAGB7_RDCLI15_BASE_IDX 1 #define mmDAGB7_RD_CNTL 0x3110 #define mmDAGB7_RD_CNTL_BASE_IDX 1 #define mmDAGB7_RD_GMI_CNTL 0x3111 #define mmDAGB7_RD_GMI_CNTL_BASE_IDX 1 #define mmDAGB7_RD_ADDR_DAGB 0x3112 #define mmDAGB7_RD_ADDR_DAGB_BASE_IDX 1 #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST 0x3113 #define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 0x3114 #define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB7_RD_CGTT_CLK_CTRL 0x3115 #define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL 0x3116 #define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL 0x3117 #define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 0x3118 #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 0x3119 #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 0x311a #define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 0x311b #define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB7_RD_VC0_CNTL 0x311c #define mmDAGB7_RD_VC0_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC1_CNTL 0x311d #define mmDAGB7_RD_VC1_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC2_CNTL 0x311e #define mmDAGB7_RD_VC2_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC3_CNTL 0x311f #define mmDAGB7_RD_VC3_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC4_CNTL 0x3120 #define mmDAGB7_RD_VC4_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC5_CNTL 0x3121 #define mmDAGB7_RD_VC5_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC6_CNTL 0x3122 #define mmDAGB7_RD_VC6_CNTL_BASE_IDX 1 #define mmDAGB7_RD_VC7_CNTL 0x3123 #define mmDAGB7_RD_VC7_CNTL_BASE_IDX 1 #define mmDAGB7_RD_CNTL_MISC 0x3124 #define mmDAGB7_RD_CNTL_MISC_BASE_IDX 1 #define mmDAGB7_RD_TLB_CREDIT 0x3125 #define mmDAGB7_RD_TLB_CREDIT_BASE_IDX 1 #define mmDAGB7_RDCLI_ASK_PENDING 0x3126 #define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB7_RDCLI_GO_PENDING 0x3127 #define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB7_RDCLI_GBLSEND_PENDING 0x3128 #define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB7_RDCLI_TLB_PENDING 0x3129 #define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB7_RDCLI_OARB_PENDING 0x312a #define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB7_RDCLI_OSD_PENDING 0x312b #define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI0 0x312c #define mmDAGB7_WRCLI0_BASE_IDX 1 #define mmDAGB7_WRCLI1 0x312d #define mmDAGB7_WRCLI1_BASE_IDX 1 #define mmDAGB7_WRCLI2 0x312e #define mmDAGB7_WRCLI2_BASE_IDX 1 #define mmDAGB7_WRCLI3 0x312f #define mmDAGB7_WRCLI3_BASE_IDX 1 #define mmDAGB7_WRCLI4 0x3130 #define mmDAGB7_WRCLI4_BASE_IDX 1 #define mmDAGB7_WRCLI5 0x3131 #define mmDAGB7_WRCLI5_BASE_IDX 1 #define mmDAGB7_WRCLI6 0x3132 #define mmDAGB7_WRCLI6_BASE_IDX 1 #define mmDAGB7_WRCLI7 0x3133 #define mmDAGB7_WRCLI7_BASE_IDX 1 #define mmDAGB7_WRCLI8 0x3134 #define mmDAGB7_WRCLI8_BASE_IDX 1 #define mmDAGB7_WRCLI9 0x3135 #define mmDAGB7_WRCLI9_BASE_IDX 1 #define mmDAGB7_WRCLI10 0x3136 #define mmDAGB7_WRCLI10_BASE_IDX 1 #define mmDAGB7_WRCLI11 0x3137 #define mmDAGB7_WRCLI11_BASE_IDX 1 #define mmDAGB7_WRCLI12 0x3138 #define mmDAGB7_WRCLI12_BASE_IDX 1 #define mmDAGB7_WRCLI13 0x3139 #define mmDAGB7_WRCLI13_BASE_IDX 1 #define mmDAGB7_WRCLI14 0x313a #define mmDAGB7_WRCLI14_BASE_IDX 1 #define mmDAGB7_WRCLI15 0x313b #define mmDAGB7_WRCLI15_BASE_IDX 1 #define mmDAGB7_WR_CNTL 0x313c #define mmDAGB7_WR_CNTL_BASE_IDX 1 #define mmDAGB7_WR_GMI_CNTL 0x313d #define mmDAGB7_WR_GMI_CNTL_BASE_IDX 1 #define mmDAGB7_WR_ADDR_DAGB 0x313e #define mmDAGB7_WR_ADDR_DAGB_BASE_IDX 1 #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST 0x313f #define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 0x3140 #define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 #define mmDAGB7_WR_CGTT_CLK_CTRL 0x3141 #define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL 0x3142 #define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL 0x3143 #define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 0x3144 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 0x3145 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 0x3146 #define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 0x3147 #define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB7_WR_DATA_DAGB 0x3148 #define mmDAGB7_WR_DATA_DAGB_BASE_IDX 1 #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0 0x3149 #define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 0x314a #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1 0x314b #define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 0x314c #define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 #define mmDAGB7_WR_VC0_CNTL 0x314d #define mmDAGB7_WR_VC0_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC1_CNTL 0x314e #define mmDAGB7_WR_VC1_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC2_CNTL 0x314f #define mmDAGB7_WR_VC2_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC3_CNTL 0x3150 #define mmDAGB7_WR_VC3_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC4_CNTL 0x3151 #define mmDAGB7_WR_VC4_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC5_CNTL 0x3152 #define mmDAGB7_WR_VC5_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC6_CNTL 0x3153 #define mmDAGB7_WR_VC6_CNTL_BASE_IDX 1 #define mmDAGB7_WR_VC7_CNTL 0x3154 #define mmDAGB7_WR_VC7_CNTL_BASE_IDX 1 #define mmDAGB7_WR_CNTL_MISC 0x3155 #define mmDAGB7_WR_CNTL_MISC_BASE_IDX 1 #define mmDAGB7_WR_TLB_CREDIT 0x3156 #define mmDAGB7_WR_TLB_CREDIT_BASE_IDX 1 #define mmDAGB7_WR_DATA_CREDIT 0x3157 #define mmDAGB7_WR_DATA_CREDIT_BASE_IDX 1 #define mmDAGB7_WR_MISC_CREDIT 0x3158 #define mmDAGB7_WR_MISC_CREDIT_BASE_IDX 1 #define mmDAGB7_WRCLI_ASK_PENDING 0x315d #define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_GO_PENDING 0x315e #define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_GBLSEND_PENDING 0x315f #define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_TLB_PENDING 0x3160 #define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_OARB_PENDING 0x3161 #define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_OSD_PENDING 0x3162 #define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_DBUS_ASK_PENDING 0x3163 #define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 #define mmDAGB7_WRCLI_DBUS_GO_PENDING 0x3164 #define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 #define mmDAGB7_DAGB_DLY 0x3165 #define mmDAGB7_DAGB_DLY_BASE_IDX 1 #define mmDAGB7_CNTL_MISC 0x3166 #define mmDAGB7_CNTL_MISC_BASE_IDX 1 #define mmDAGB7_CNTL_MISC2 0x3167 #define mmDAGB7_CNTL_MISC2_BASE_IDX 1 #define mmDAGB7_FIFO_EMPTY 0x3168 #define mmDAGB7_FIFO_EMPTY_BASE_IDX 1 #define mmDAGB7_FIFO_FULL 0x3169 #define mmDAGB7_FIFO_FULL_BASE_IDX 1 #define mmDAGB7_WR_CREDITS_FULL 0x316a #define mmDAGB7_WR_CREDITS_FULL_BASE_IDX 1 #define mmDAGB7_RD_CREDITS_FULL 0x316b #define mmDAGB7_RD_CREDITS_FULL_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER_LO 0x316c #define mmDAGB7_PERFCOUNTER_LO_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER_HI 0x316d #define mmDAGB7_PERFCOUNTER_HI_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER0_CFG 0x316e #define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER1_CFG 0x316f #define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER2_CFG 0x3170 #define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmDAGB7_PERFCOUNTER_RSLT_CNTL 0x3171 #define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmDAGB7_RESERVE0 0x3172 #define mmDAGB7_RESERVE0_BASE_IDX 1 #define mmDAGB7_RESERVE1 0x3173 #define mmDAGB7_RESERVE1_BASE_IDX 1 #define mmDAGB7_RESERVE2 0x3174 #define mmDAGB7_RESERVE2_BASE_IDX 1 #define mmDAGB7_RESERVE3 0x3175 #define mmDAGB7_RESERVE3_BASE_IDX 1 #define mmDAGB7_RESERVE4 0x3176 #define mmDAGB7_RESERVE4_BASE_IDX 1 #define mmDAGB7_RESERVE5 0x3177 #define mmDAGB7_RESERVE5_BASE_IDX 1 #define mmDAGB7_RESERVE6 0x3178 #define mmDAGB7_RESERVE6_BASE_IDX 1 #define mmDAGB7_RESERVE7 0x3179 #define mmDAGB7_RESERVE7_BASE_IDX 1 #define mmDAGB7_RESERVE8 0x317a #define mmDAGB7_RESERVE8_BASE_IDX 1 #define mmDAGB7_RESERVE9 0x317b #define mmDAGB7_RESERVE9_BASE_IDX 1 #define mmDAGB7_RESERVE10 0x317c #define mmDAGB7_RESERVE10_BASE_IDX 1 #define mmDAGB7_RESERVE11 0x317d #define mmDAGB7_RESERVE11_BASE_IDX 1 #define mmDAGB7_RESERVE12 0x317e #define mmDAGB7_RESERVE12_BASE_IDX 1 #define mmDAGB7_RESERVE13 0x317f #define mmDAGB7_RESERVE13_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec5 // base address: 0x74a00 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0 0x3280 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1 0x3281 #define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0 0x3282 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1 0x3283 #define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_DRAM_RD_GRP2VC_MAP 0x3284 #define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA5_DRAM_WR_GRP2VC_MAP 0x3285 #define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA5_DRAM_RD_LAZY 0x3286 #define mmMMEA5_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA5_DRAM_WR_LAZY 0x3287 #define mmMMEA5_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA5_DRAM_RD_CAM_CNTL 0x3288 #define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA5_DRAM_WR_CAM_CNTL 0x3289 #define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA5_DRAM_PAGE_BURST 0x328a #define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_AGE 0x328b #define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_AGE 0x328c #define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_QUEUING 0x328d #define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_QUEUING 0x328e #define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_FIXED 0x328f #define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_FIXED 0x3290 #define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_URGENCY 0x3291 #define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_URGENCY 0x3292 #define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x3293 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x3294 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x3295 #define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x3296 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x3297 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x3298 #define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_GMI_RD_CLI2GRP_MAP0 0x3299 #define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_GMI_RD_CLI2GRP_MAP1 0x329a #define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_GMI_WR_CLI2GRP_MAP0 0x329b #define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_GMI_WR_CLI2GRP_MAP1 0x329c #define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_GMI_RD_GRP2VC_MAP 0x329d #define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA5_GMI_WR_GRP2VC_MAP 0x329e #define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA5_GMI_RD_LAZY 0x329f #define mmMMEA5_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA5_GMI_WR_LAZY 0x32a0 #define mmMMEA5_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA5_GMI_RD_CAM_CNTL 0x32a1 #define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA5_GMI_WR_CAM_CNTL 0x32a2 #define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA5_GMI_PAGE_BURST 0x32a3 #define mmMMEA5_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_AGE 0x32a4 #define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_AGE 0x32a5 #define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_QUEUING 0x32a6 #define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_QUEUING 0x32a7 #define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_FIXED 0x32a8 #define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_FIXED 0x32a9 #define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_URGENCY 0x32aa #define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_URGENCY 0x32ab #define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x32ac #define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x32ad #define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1 0x32ae #define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2 0x32af #define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3 0x32b0 #define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1 0x32b1 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2 0x32b2 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3 0x32b3 #define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR0 0x32b4 #define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR0 0x32b5 #define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR1 0x32b6 #define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR1 0x32b7 #define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA5_ADDRNORM_OFFSET_ADDR1 0x32b8 #define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR2 0x32b9 #define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR2 0x32ba #define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR3 0x32bb #define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR3 0x32bc #define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA5_ADDRNORM_OFFSET_ADDR3 0x32bd #define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR4 0x32be #define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR4 0x32bf #define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA5_ADDRNORM_BASE_ADDR5 0x32c0 #define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR5 0x32c1 #define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA5_ADDRNORM_OFFSET_ADDR5 0x32c2 #define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x32c3 #define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL 0x32c4 #define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x32c5 #define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x32c6 #define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA5_ADDRDEC_BANK_CFG 0x32c7 #define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA5_ADDRDEC_MISC_CFG 0x32c8 #define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 0x32c9 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 0x32ca #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 0x32cb #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 0x32cc #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 0x32cd #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 0x32ce #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC 0x32cf #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 0x32d0 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 0x32d1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 0x32d2 #define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x32d3 #define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 0x32d4 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 0x32d5 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 0x32d6 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 0x32d7 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 0x32d8 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 0x32d9 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC 0x32da #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 0x32db #define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 0x32dc #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 0x32dd #define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x32de #define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x32df #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x32e0 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x32e1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x32e2 #define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x32e3 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x32e4 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x32e5 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x32e6 #define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x32e7 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x32e8 #define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x32e9 #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x32ea #define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x32eb #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x32ec #define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x32ed #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x32ee #define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x32ef #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x32f0 #define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x32f1 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x32f2 #define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x32f3 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x32f4 #define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_RM_SEL_CS01 0x32f5 #define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_RM_SEL_CS23 0x32f6 #define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x32f7 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x32f8 #define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x32f9 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x32fa #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x32fb #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x32fc #define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x32fd #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x32fe #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x32ff #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x3300 #define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x3301 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x3302 #define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x3303 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x3304 #define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x3305 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x3306 #define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x3307 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x3308 #define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x3309 #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x330a #define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x330b #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x330c #define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x330d #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x330e #define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_RM_SEL_CS01 0x330f #define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_RM_SEL_CS23 0x3310 #define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x3311 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x3312 #define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x3313 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x3314 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x3315 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x3316 #define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x3317 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x3318 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x3319 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x331a #define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x331b #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x331c #define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x331d #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x331e #define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x331f #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x3320 #define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x3321 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x3322 #define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x3323 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x3324 #define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x3325 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x3326 #define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x3327 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x3328 #define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_RM_SEL_CS01 0x3329 #define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_RM_SEL_CS23 0x332a #define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x332b #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x332c #define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x332d #define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x332e #define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA5_IO_RD_CLI2GRP_MAP0 0x3355 #define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_IO_RD_CLI2GRP_MAP1 0x3356 #define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_IO_WR_CLI2GRP_MAP0 0x3357 #define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA5_IO_WR_CLI2GRP_MAP1 0x3358 #define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA5_IO_RD_COMBINE_FLUSH 0x3359 #define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA5_IO_WR_COMBINE_FLUSH 0x335a #define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA5_IO_GROUP_BURST 0x335b #define mmMMEA5_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_AGE 0x335c #define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_AGE 0x335d #define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_QUEUING 0x335e #define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_QUEUING 0x335f #define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_FIXED 0x3360 #define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_FIXED 0x3361 #define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_URGENCY 0x3362 #define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_URGENCY 0x3363 #define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING 0x3364 #define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING 0x3365 #define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_QUANT_PRI1 0x3366 #define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_QUANT_PRI2 0x3367 #define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_IO_RD_PRI_QUANT_PRI3 0x3368 #define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_QUANT_PRI1 0x3369 #define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_QUANT_PRI2 0x336a #define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA5_IO_WR_PRI_QUANT_PRI3 0x336b #define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA5_SDP_ARB_DRAM 0x336c #define mmMMEA5_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA5_SDP_ARB_GMI 0x336d #define mmMMEA5_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA5_SDP_ARB_FINAL 0x336e #define mmMMEA5_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA5_SDP_DRAM_PRIORITY 0x336f #define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA5_SDP_GMI_PRIORITY 0x3370 #define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA5_SDP_IO_PRIORITY 0x3371 #define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA5_SDP_CREDITS 0x3372 #define mmMMEA5_SDP_CREDITS_BASE_IDX 1 #define mmMMEA5_SDP_TAG_RESERVE0 0x3373 #define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA5_SDP_TAG_RESERVE1 0x3374 #define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA5_SDP_VCC_RESERVE0 0x3375 #define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA5_SDP_VCC_RESERVE1 0x3376 #define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA5_SDP_VCD_RESERVE0 0x3377 #define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA5_SDP_VCD_RESERVE1 0x3378 #define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA5_SDP_REQ_CNTL 0x3379 #define mmMMEA5_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA5_MISC 0x337a #define mmMMEA5_MISC_BASE_IDX 1 #define mmMMEA5_LATENCY_SAMPLING 0x337b #define mmMMEA5_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA5_PERFCOUNTER_LO 0x337c #define mmMMEA5_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA5_PERFCOUNTER_HI 0x337d #define mmMMEA5_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA5_PERFCOUNTER0_CFG 0x337e #define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA5_PERFCOUNTER1_CFG 0x337f #define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA5_PERFCOUNTER_RSLT_CNTL 0x3380 #define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA5_EDC_CNT 0x3386 #define mmMMEA5_EDC_CNT_BASE_IDX 1 #define mmMMEA5_EDC_CNT2 0x3387 #define mmMMEA5_EDC_CNT2_BASE_IDX 1 #define mmMMEA5_DSM_CNTL 0x3388 #define mmMMEA5_DSM_CNTL_BASE_IDX 1 #define mmMMEA5_DSM_CNTLA 0x3389 #define mmMMEA5_DSM_CNTLA_BASE_IDX 1 #define mmMMEA5_DSM_CNTLB 0x338a #define mmMMEA5_DSM_CNTLB_BASE_IDX 1 #define mmMMEA5_DSM_CNTL2 0x338b #define mmMMEA5_DSM_CNTL2_BASE_IDX 1 #define mmMMEA5_DSM_CNTL2A 0x338c #define mmMMEA5_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA5_DSM_CNTL2B 0x338d #define mmMMEA5_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA5_CGTT_CLK_CTRL 0x338f #define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA5_EDC_MODE 0x3390 #define mmMMEA5_EDC_MODE_BASE_IDX 1 #define mmMMEA5_ERR_STATUS 0x3391 #define mmMMEA5_ERR_STATUS_BASE_IDX 1 #define mmMMEA5_MISC2 0x3392 #define mmMMEA5_MISC2_BASE_IDX 1 #define mmMMEA5_ADDRDEC_SELECT 0x3393 #define mmMMEA5_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA5_EDC_CNT3 0x3394 #define mmMMEA5_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec6 // base address: 0x74f00 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0 0x33c0 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1 0x33c1 #define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0 0x33c2 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1 0x33c3 #define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_DRAM_RD_GRP2VC_MAP 0x33c4 #define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA6_DRAM_WR_GRP2VC_MAP 0x33c5 #define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA6_DRAM_RD_LAZY 0x33c6 #define mmMMEA6_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA6_DRAM_WR_LAZY 0x33c7 #define mmMMEA6_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA6_DRAM_RD_CAM_CNTL 0x33c8 #define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA6_DRAM_WR_CAM_CNTL 0x33c9 #define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA6_DRAM_PAGE_BURST 0x33ca #define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_AGE 0x33cb #define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_AGE 0x33cc #define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_QUEUING 0x33cd #define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_QUEUING 0x33ce #define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_FIXED 0x33cf #define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_FIXED 0x33d0 #define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_URGENCY 0x33d1 #define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_URGENCY 0x33d2 #define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 0x33d3 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 0x33d4 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 0x33d5 #define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 0x33d6 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 0x33d7 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 0x33d8 #define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_GMI_RD_CLI2GRP_MAP0 0x33d9 #define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_GMI_RD_CLI2GRP_MAP1 0x33da #define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_GMI_WR_CLI2GRP_MAP0 0x33db #define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_GMI_WR_CLI2GRP_MAP1 0x33dc #define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_GMI_RD_GRP2VC_MAP 0x33dd #define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA6_GMI_WR_GRP2VC_MAP 0x33de #define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA6_GMI_RD_LAZY 0x33df #define mmMMEA6_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA6_GMI_WR_LAZY 0x33e0 #define mmMMEA6_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA6_GMI_RD_CAM_CNTL 0x33e1 #define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA6_GMI_WR_CAM_CNTL 0x33e2 #define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA6_GMI_PAGE_BURST 0x33e3 #define mmMMEA6_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_AGE 0x33e4 #define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_AGE 0x33e5 #define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_QUEUING 0x33e6 #define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_QUEUING 0x33e7 #define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_FIXED 0x33e8 #define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_FIXED 0x33e9 #define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_URGENCY 0x33ea #define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_URGENCY 0x33eb #define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING 0x33ec #define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING 0x33ed #define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1 0x33ee #define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2 0x33ef #define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3 0x33f0 #define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1 0x33f1 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2 0x33f2 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3 0x33f3 #define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR0 0x33f4 #define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR0 0x33f5 #define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR1 0x33f6 #define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR1 0x33f7 #define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA6_ADDRNORM_OFFSET_ADDR1 0x33f8 #define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR2 0x33f9 #define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR2 0x33fa #define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR3 0x33fb #define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR3 0x33fc #define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA6_ADDRNORM_OFFSET_ADDR3 0x33fd #define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR4 0x33fe #define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR4 0x33ff #define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA6_ADDRNORM_BASE_ADDR5 0x3400 #define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA6_ADDRNORM_LIMIT_ADDR5 0x3401 #define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA6_ADDRNORM_OFFSET_ADDR5 0x3402 #define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL 0x3403 #define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL 0x3404 #define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3405 #define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3406 #define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA6_ADDRDEC_BANK_CFG 0x3407 #define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA6_ADDRDEC_MISC_CFG 0x3408 #define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 0x3409 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 0x340a #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 0x340b #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 0x340c #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 0x340d #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 0x340e #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC 0x340f #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 0x3410 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 0x3411 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 0x3412 #define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE 0x3413 #define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 0x3414 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 0x3415 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 0x3416 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 0x3417 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 0x3418 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 0x3419 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC 0x341a #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 0x341b #define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 0x341c #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 0x341d #define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE 0x341e #define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 0x341f #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 0x3420 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 0x3421 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 0x3422 #define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 0x3423 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 0x3424 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 0x3425 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 0x3426 #define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 0x3427 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 0x3428 #define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 0x3429 #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 0x342a #define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 0x342b #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 0x342c #define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 0x342d #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 0x342e #define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 0x342f #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 0x3430 #define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 0x3431 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 0x3432 #define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 0x3433 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 0x3434 #define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_RM_SEL_CS01 0x3435 #define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_RM_SEL_CS23 0x3436 #define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 0x3437 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 0x3438 #define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 0x3439 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 0x343a #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 0x343b #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 0x343c #define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 0x343d #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 0x343e #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 0x343f #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 0x3440 #define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 0x3441 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 0x3442 #define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 0x3443 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 0x3444 #define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 0x3445 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 0x3446 #define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 0x3447 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 0x3448 #define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 0x3449 #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 0x344a #define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 0x344b #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 0x344c #define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 0x344d #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 0x344e #define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_RM_SEL_CS01 0x344f #define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_RM_SEL_CS23 0x3450 #define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 0x3451 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 0x3452 #define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 0x3453 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 0x3454 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 0x3455 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 0x3456 #define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 0x3457 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 0x3458 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 0x3459 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 0x345a #define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 0x345b #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 0x345c #define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 0x345d #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 0x345e #define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 0x345f #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 0x3460 #define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 0x3461 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 0x3462 #define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 0x3463 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 0x3464 #define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 0x3465 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 0x3466 #define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 0x3467 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 0x3468 #define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_RM_SEL_CS01 0x3469 #define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_RM_SEL_CS23 0x346a #define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 0x346b #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 0x346c #define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL 0x346d #define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL 0x346e #define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA6_IO_RD_CLI2GRP_MAP0 0x3495 #define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_IO_RD_CLI2GRP_MAP1 0x3496 #define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_IO_WR_CLI2GRP_MAP0 0x3497 #define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA6_IO_WR_CLI2GRP_MAP1 0x3498 #define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA6_IO_RD_COMBINE_FLUSH 0x3499 #define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA6_IO_WR_COMBINE_FLUSH 0x349a #define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA6_IO_GROUP_BURST 0x349b #define mmMMEA6_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_AGE 0x349c #define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_AGE 0x349d #define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_QUEUING 0x349e #define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_QUEUING 0x349f #define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_FIXED 0x34a0 #define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_FIXED 0x34a1 #define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_URGENCY 0x34a2 #define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_URGENCY 0x34a3 #define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING 0x34a4 #define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING 0x34a5 #define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_QUANT_PRI1 0x34a6 #define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_QUANT_PRI2 0x34a7 #define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_IO_RD_PRI_QUANT_PRI3 0x34a8 #define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_QUANT_PRI1 0x34a9 #define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_QUANT_PRI2 0x34aa #define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA6_IO_WR_PRI_QUANT_PRI3 0x34ab #define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA6_SDP_ARB_DRAM 0x34ac #define mmMMEA6_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA6_SDP_ARB_GMI 0x34ad #define mmMMEA6_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA6_SDP_ARB_FINAL 0x34ae #define mmMMEA6_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA6_SDP_DRAM_PRIORITY 0x34af #define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA6_SDP_GMI_PRIORITY 0x34b0 #define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA6_SDP_IO_PRIORITY 0x34b1 #define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA6_SDP_CREDITS 0x34b2 #define mmMMEA6_SDP_CREDITS_BASE_IDX 1 #define mmMMEA6_SDP_TAG_RESERVE0 0x34b3 #define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA6_SDP_TAG_RESERVE1 0x34b4 #define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA6_SDP_VCC_RESERVE0 0x34b5 #define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA6_SDP_VCC_RESERVE1 0x34b6 #define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA6_SDP_VCD_RESERVE0 0x34b7 #define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA6_SDP_VCD_RESERVE1 0x34b8 #define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA6_SDP_REQ_CNTL 0x34b9 #define mmMMEA6_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA6_MISC 0x34ba #define mmMMEA6_MISC_BASE_IDX 1 #define mmMMEA6_LATENCY_SAMPLING 0x34bb #define mmMMEA6_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA6_PERFCOUNTER_LO 0x34bc #define mmMMEA6_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA6_PERFCOUNTER_HI 0x34bd #define mmMMEA6_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA6_PERFCOUNTER0_CFG 0x34be #define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA6_PERFCOUNTER1_CFG 0x34bf #define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA6_PERFCOUNTER_RSLT_CNTL 0x34c0 #define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA6_EDC_CNT 0x34c6 #define mmMMEA6_EDC_CNT_BASE_IDX 1 #define mmMMEA6_EDC_CNT2 0x34c7 #define mmMMEA6_EDC_CNT2_BASE_IDX 1 #define mmMMEA6_DSM_CNTL 0x34c8 #define mmMMEA6_DSM_CNTL_BASE_IDX 1 #define mmMMEA6_DSM_CNTLA 0x34c9 #define mmMMEA6_DSM_CNTLA_BASE_IDX 1 #define mmMMEA6_DSM_CNTLB 0x34ca #define mmMMEA6_DSM_CNTLB_BASE_IDX 1 #define mmMMEA6_DSM_CNTL2 0x34cb #define mmMMEA6_DSM_CNTL2_BASE_IDX 1 #define mmMMEA6_DSM_CNTL2A 0x34cc #define mmMMEA6_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA6_DSM_CNTL2B 0x34cd #define mmMMEA6_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA6_CGTT_CLK_CTRL 0x34cf #define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA6_EDC_MODE 0x34d0 #define mmMMEA6_EDC_MODE_BASE_IDX 1 #define mmMMEA6_ERR_STATUS 0x34d1 #define mmMMEA6_ERR_STATUS_BASE_IDX 1 #define mmMMEA6_MISC2 0x34d2 #define mmMMEA6_MISC2_BASE_IDX 1 #define mmMMEA6_ADDRDEC_SELECT 0x34d3 #define mmMMEA6_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA6_EDC_CNT3 0x34d4 #define mmMMEA6_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_ea_mmeadec7 // base address: 0x75400 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0 0x3500 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1 0x3501 #define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0 0x3502 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1 0x3503 #define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_DRAM_RD_GRP2VC_MAP 0x3504 #define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA7_DRAM_WR_GRP2VC_MAP 0x3505 #define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA7_DRAM_RD_LAZY 0x3506 #define mmMMEA7_DRAM_RD_LAZY_BASE_IDX 1 #define mmMMEA7_DRAM_WR_LAZY 0x3507 #define mmMMEA7_DRAM_WR_LAZY_BASE_IDX 1 #define mmMMEA7_DRAM_RD_CAM_CNTL 0x3508 #define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA7_DRAM_WR_CAM_CNTL 0x3509 #define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA7_DRAM_PAGE_BURST 0x350a #define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_AGE 0x350b #define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_AGE 0x350c #define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_QUEUING 0x350d #define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_QUEUING 0x350e #define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_FIXED 0x350f #define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_FIXED 0x3510 #define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_URGENCY 0x3511 #define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_URGENCY 0x3512 #define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 0x3513 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 0x3514 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 0x3515 #define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 0x3516 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 0x3517 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 0x3518 #define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_GMI_RD_CLI2GRP_MAP0 0x3519 #define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_GMI_RD_CLI2GRP_MAP1 0x351a #define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_GMI_WR_CLI2GRP_MAP0 0x351b #define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_GMI_WR_CLI2GRP_MAP1 0x351c #define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_GMI_RD_GRP2VC_MAP 0x351d #define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA7_GMI_WR_GRP2VC_MAP 0x351e #define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX 1 #define mmMMEA7_GMI_RD_LAZY 0x351f #define mmMMEA7_GMI_RD_LAZY_BASE_IDX 1 #define mmMMEA7_GMI_WR_LAZY 0x3520 #define mmMMEA7_GMI_WR_LAZY_BASE_IDX 1 #define mmMMEA7_GMI_RD_CAM_CNTL 0x3521 #define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX 1 #define mmMMEA7_GMI_WR_CAM_CNTL 0x3522 #define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX 1 #define mmMMEA7_GMI_PAGE_BURST 0x3523 #define mmMMEA7_GMI_PAGE_BURST_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_AGE 0x3524 #define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_AGE 0x3525 #define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_QUEUING 0x3526 #define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_QUEUING 0x3527 #define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_FIXED 0x3528 #define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_FIXED 0x3529 #define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_URGENCY 0x352a #define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_URGENCY 0x352b #define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING 0x352c #define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING 0x352d #define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1 0x352e #define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2 0x352f #define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3 0x3530 #define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1 0x3531 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2 0x3532 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3 0x3533 #define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR0 0x3534 #define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR0 0x3535 #define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR1 0x3536 #define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR1 0x3537 #define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 #define mmMMEA7_ADDRNORM_OFFSET_ADDR1 0x3538 #define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR2 0x3539 #define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR2 0x353a #define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR3 0x353b #define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR3 0x353c #define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 #define mmMMEA7_ADDRNORM_OFFSET_ADDR3 0x353d #define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR4 0x353e #define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR4 0x353f #define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 #define mmMMEA7_ADDRNORM_BASE_ADDR5 0x3540 #define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX 1 #define mmMMEA7_ADDRNORM_LIMIT_ADDR5 0x3541 #define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 #define mmMMEA7_ADDRNORM_OFFSET_ADDR5 0x3542 #define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL 0x3543 #define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL 0x3544 #define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3545 #define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3546 #define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 #define mmMMEA7_ADDRDEC_BANK_CFG 0x3547 #define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX 1 #define mmMMEA7_ADDRDEC_MISC_CFG 0x3548 #define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 0x3549 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 0x354a #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 0x354b #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 0x354c #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 0x354d #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 0x354e #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC 0x354f #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 0x3550 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 0x3551 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 0x3552 #define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE 0x3553 #define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 0x3554 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 0x3555 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 0x3556 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 0x3557 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 0x3558 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 0x3559 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC 0x355a #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 0x355b #define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 0x355c #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 0x355d #define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE 0x355e #define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 0x355f #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 0x3560 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 0x3561 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 0x3562 #define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 0x3563 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 0x3564 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 0x3565 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 0x3566 #define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 0x3567 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 0x3568 #define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 0x3569 #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 0x356a #define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 0x356b #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 0x356c #define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 0x356d #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 0x356e #define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 0x356f #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 0x3570 #define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 0x3571 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 0x3572 #define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 0x3573 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 0x3574 #define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_RM_SEL_CS01 0x3575 #define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_RM_SEL_CS23 0x3576 #define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 0x3577 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 0x3578 #define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 0x3579 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 0x357a #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 0x357b #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 0x357c #define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 0x357d #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 0x357e #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 0x357f #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 0x3580 #define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 0x3581 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 0x3582 #define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 0x3583 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 0x3584 #define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 0x3585 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 0x3586 #define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 0x3587 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 0x3588 #define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 0x3589 #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 0x358a #define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 0x358b #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 0x358c #define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 0x358d #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 0x358e #define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_RM_SEL_CS01 0x358f #define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_RM_SEL_CS23 0x3590 #define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 0x3591 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 0x3592 #define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 0x3593 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 0x3594 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 0x3595 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 0x3596 #define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 0x3597 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 0x3598 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 0x3599 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 0x359a #define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 0x359b #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 0x359c #define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 0x359d #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 0x359e #define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 0x359f #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 0x35a0 #define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 0x35a1 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 0x35a2 #define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 0x35a3 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 0x35a4 #define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 0x35a5 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 0x35a6 #define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 0x35a7 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 0x35a8 #define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_RM_SEL_CS01 0x35a9 #define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_RM_SEL_CS23 0x35aa #define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 0x35ab #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 0x35ac #define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL 0x35ad #define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL 0x35ae #define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 #define mmMMEA7_IO_RD_CLI2GRP_MAP0 0x35d5 #define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_IO_RD_CLI2GRP_MAP1 0x35d6 #define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_IO_WR_CLI2GRP_MAP0 0x35d7 #define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 #define mmMMEA7_IO_WR_CLI2GRP_MAP1 0x35d8 #define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 #define mmMMEA7_IO_RD_COMBINE_FLUSH 0x35d9 #define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA7_IO_WR_COMBINE_FLUSH 0x35da #define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX 1 #define mmMMEA7_IO_GROUP_BURST 0x35db #define mmMMEA7_IO_GROUP_BURST_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_AGE 0x35dc #define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_AGE 0x35dd #define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_QUEUING 0x35de #define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_QUEUING 0x35df #define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_FIXED 0x35e0 #define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_FIXED 0x35e1 #define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_URGENCY 0x35e2 #define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_URGENCY 0x35e3 #define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING 0x35e4 #define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING 0x35e5 #define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_QUANT_PRI1 0x35e6 #define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_QUANT_PRI2 0x35e7 #define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_IO_RD_PRI_QUANT_PRI3 0x35e8 #define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_QUANT_PRI1 0x35e9 #define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_QUANT_PRI2 0x35ea #define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 #define mmMMEA7_IO_WR_PRI_QUANT_PRI3 0x35eb #define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 #define mmMMEA7_SDP_ARB_DRAM 0x35ec #define mmMMEA7_SDP_ARB_DRAM_BASE_IDX 1 #define mmMMEA7_SDP_ARB_GMI 0x35ed #define mmMMEA7_SDP_ARB_GMI_BASE_IDX 1 #define mmMMEA7_SDP_ARB_FINAL 0x35ee #define mmMMEA7_SDP_ARB_FINAL_BASE_IDX 1 #define mmMMEA7_SDP_DRAM_PRIORITY 0x35ef #define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX 1 #define mmMMEA7_SDP_GMI_PRIORITY 0x35f0 #define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX 1 #define mmMMEA7_SDP_IO_PRIORITY 0x35f1 #define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX 1 #define mmMMEA7_SDP_CREDITS 0x35f2 #define mmMMEA7_SDP_CREDITS_BASE_IDX 1 #define mmMMEA7_SDP_TAG_RESERVE0 0x35f3 #define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX 1 #define mmMMEA7_SDP_TAG_RESERVE1 0x35f4 #define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX 1 #define mmMMEA7_SDP_VCC_RESERVE0 0x35f5 #define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX 1 #define mmMMEA7_SDP_VCC_RESERVE1 0x35f6 #define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX 1 #define mmMMEA7_SDP_VCD_RESERVE0 0x35f7 #define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX 1 #define mmMMEA7_SDP_VCD_RESERVE1 0x35f8 #define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX 1 #define mmMMEA7_SDP_REQ_CNTL 0x35f9 #define mmMMEA7_SDP_REQ_CNTL_BASE_IDX 1 #define mmMMEA7_MISC 0x35fa #define mmMMEA7_MISC_BASE_IDX 1 #define mmMMEA7_LATENCY_SAMPLING 0x35fb #define mmMMEA7_LATENCY_SAMPLING_BASE_IDX 1 #define mmMMEA7_PERFCOUNTER_LO 0x35fc #define mmMMEA7_PERFCOUNTER_LO_BASE_IDX 1 #define mmMMEA7_PERFCOUNTER_HI 0x35fd #define mmMMEA7_PERFCOUNTER_HI_BASE_IDX 1 #define mmMMEA7_PERFCOUNTER0_CFG 0x35fe #define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmMMEA7_PERFCOUNTER1_CFG 0x35ff #define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmMMEA7_PERFCOUNTER_RSLT_CNTL 0x3600 #define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 #define mmMMEA7_EDC_CNT 0x3606 #define mmMMEA7_EDC_CNT_BASE_IDX 1 #define mmMMEA7_EDC_CNT2 0x3607 #define mmMMEA7_EDC_CNT2_BASE_IDX 1 #define mmMMEA7_DSM_CNTL 0x3608 #define mmMMEA7_DSM_CNTL_BASE_IDX 1 #define mmMMEA7_DSM_CNTLA 0x3609 #define mmMMEA7_DSM_CNTLA_BASE_IDX 1 #define mmMMEA7_DSM_CNTLB 0x360a #define mmMMEA7_DSM_CNTLB_BASE_IDX 1 #define mmMMEA7_DSM_CNTL2 0x360b #define mmMMEA7_DSM_CNTL2_BASE_IDX 1 #define mmMMEA7_DSM_CNTL2A 0x360c #define mmMMEA7_DSM_CNTL2A_BASE_IDX 1 #define mmMMEA7_DSM_CNTL2B 0x360d #define mmMMEA7_DSM_CNTL2B_BASE_IDX 1 #define mmMMEA7_CGTT_CLK_CTRL 0x360f #define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX 1 #define mmMMEA7_EDC_MODE 0x3610 #define mmMMEA7_EDC_MODE_BASE_IDX 1 #define mmMMEA7_ERR_STATUS 0x3611 #define mmMMEA7_ERR_STATUS_BASE_IDX 1 #define mmMMEA7_MISC2 0x3612 #define mmMMEA7_MISC2_BASE_IDX 1 #define mmMMEA7_ADDRDEC_SELECT 0x3613 #define mmMMEA7_ADDRDEC_SELECT_BASE_IDX 1 #define mmMMEA7_EDC_CNT3 0x3614 #define mmMMEA7_EDC_CNT3_BASE_IDX 1 // addressBlock: mmhub_pctldec1 // base address: 0x76300 #define mmPCTL1_CTRL 0x38c0 #define mmPCTL1_CTRL_BASE_IDX 1 #define mmPCTL1_MMHUB_DEEPSLEEP_IB 0x38c1 #define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE 0x38c2 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x38c3 #define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 #define mmPCTL1_PG_IGNORE_DEEPSLEEP 0x38c4 #define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB 0x38c5 #define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 #define mmPCTL1_SLICE0_CFG_DAGB_BUSY 0x38c6 #define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL1_SLICE0_CFG_DS_ALLOW 0x38c7 #define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB 0x38c8 #define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL1_SLICE1_CFG_DAGB_BUSY 0x38c9 #define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL1_SLICE1_CFG_DS_ALLOW 0x38ca #define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB 0x38cb #define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL1_SLICE2_CFG_DAGB_BUSY 0x38cc #define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL1_SLICE2_CFG_DS_ALLOW 0x38cd #define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB 0x38ce #define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL1_SLICE3_CFG_DAGB_BUSY 0x38cf #define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL1_SLICE3_CFG_DS_ALLOW 0x38d0 #define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB 0x38d1 #define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL1_SLICE4_CFG_DAGB_BUSY 0x38d2 #define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 #define mmPCTL1_SLICE4_CFG_DS_ALLOW 0x38d3 #define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB 0x38d4 #define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 #define mmPCTL1_UTCL2_MISC 0x38d5 #define mmPCTL1_UTCL2_MISC_BASE_IDX 1 #define mmPCTL1_SLICE0_MISC 0x38d6 #define mmPCTL1_SLICE0_MISC_BASE_IDX 1 #define mmPCTL1_SLICE1_MISC 0x38d7 #define mmPCTL1_SLICE1_MISC_BASE_IDX 1 #define mmPCTL1_SLICE2_MISC 0x38d8 #define mmPCTL1_SLICE2_MISC_BASE_IDX 1 #define mmPCTL1_SLICE3_MISC 0x38d9 #define mmPCTL1_SLICE3_MISC_BASE_IDX 1 #define mmPCTL1_SLICE4_MISC 0x38da #define mmPCTL1_SLICE4_MISC_BASE_IDX 1 #define mmPCTL1_UTCL2_RENG_EXECUTE 0x38db #define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_SLICE0_RENG_EXECUTE 0x38dc #define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_SLICE1_RENG_EXECUTE 0x38dd #define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_SLICE2_RENG_EXECUTE 0x38de #define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_SLICE3_RENG_EXECUTE 0x38df #define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_SLICE4_RENG_EXECUTE 0x38e0 #define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX 1 #define mmPCTL1_UTCL2_RENG_RAM_INDEX 0x38e1 #define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_UTCL2_RENG_RAM_DATA 0x38e2 #define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_SLICE0_RENG_RAM_INDEX 0x38e3 #define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_SLICE0_RENG_RAM_DATA 0x38e4 #define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_SLICE1_RENG_RAM_INDEX 0x38e5 #define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_SLICE1_RENG_RAM_DATA 0x38e6 #define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_SLICE2_RENG_RAM_INDEX 0x38e7 #define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_SLICE2_RENG_RAM_DATA 0x38e8 #define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_SLICE3_RENG_RAM_INDEX 0x38e9 #define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_SLICE3_RENG_RAM_DATA 0x38ea #define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_SLICE4_RENG_RAM_INDEX 0x38eb #define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 #define mmPCTL1_SLICE4_RENG_RAM_DATA 0x38ec #define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x38ed #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x38ee #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x38ef #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x38f0 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x38f1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f2 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38f3 #define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x38f4 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x38f5 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x38f6 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x38f7 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x38f8 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f9 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38fa #define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x38fb #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x38fc #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x38fd #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x38fe #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x38ff #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3900 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3901 #define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x3902 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x3903 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x3904 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x3905 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x3906 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3907 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3908 #define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x3909 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x390a #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x390b #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x390c #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x390d #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x390e #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x390f #define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x3910 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x3911 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x3912 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x3913 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x3914 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3915 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3916 #define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1dec:1 // base address: 0x76500 #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS 0x3948 #define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS 0x3949 #define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS 0x394a #define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS 0x394b #define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS 0x394c #define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS 0x394d #define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS 0x394e #define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS 0x394f #define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1pldec:1 // base address: 0x76580 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x3960 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x3961 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x3962 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x3963 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x3964 #define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_l1tlb_vml1prdec:1 // base address: 0x765c0 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 0x3970 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 0x3971 #define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2dec:1 // base address: 0x76600 #define mmATCL2_1_ATC_L2_CNTL 0x3980 #define mmATCL2_1_ATC_L2_CNTL_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CNTL2 0x3981 #define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_DATA0 0x3984 #define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_DATA1 0x3985 #define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_DATA2 0x3986 #define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CNTL3 0x3987 #define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX 1 #define mmATCL2_1_ATC_L2_STATUS 0x3988 #define mmATCL2_1_ATC_L2_STATUS_BASE_IDX 1 #define mmATCL2_1_ATC_L2_STATUS2 0x3989 #define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX 1 #define mmATCL2_1_ATC_L2_STATUS3 0x398a #define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX 1 #define mmATCL2_1_ATC_L2_MISC_CG 0x398b #define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX 1 #define mmATCL2_1_ATC_L2_MEM_POWER_LS 0x398c #define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL 0x398d #define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 0x398e #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 0x398f #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 0x3990 #define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 0x3991 #define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 #define mmATCL2_1_ATC_L2_CNTL4 0x3992 #define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX 1 #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 0x3993 #define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2pfdec:1 // base address: 0x76700 #define mmVML2PF1_VM_L2_CNTL 0x39c0 #define mmVML2PF1_VM_L2_CNTL_BASE_IDX 1 #define mmVML2PF1_VM_L2_CNTL2 0x39c1 #define mmVML2PF1_VM_L2_CNTL2_BASE_IDX 1 #define mmVML2PF1_VM_L2_CNTL3 0x39c2 #define mmVML2PF1_VM_L2_CNTL3_BASE_IDX 1 #define mmVML2PF1_VM_L2_STATUS 0x39c3 #define mmVML2PF1_VM_L2_STATUS_BASE_IDX 1 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 0x39c4 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x39c5 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x39c6 #define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL 0x39c7 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 0x39c8 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x39c9 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x39ca #define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS 0x39cb #define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x39cc #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x39cd #define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x39ce #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x39cf #define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x39d1 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x39d2 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x39d3 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x39d4 #define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x39d5 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x39d6 #define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 #define mmVML2PF1_VM_L2_CNTL4 0x39d7 #define mmVML2PF1_VM_L2_CNTL4_BASE_IDX 1 #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES 0x39d8 #define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 0x39d9 #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 0x39da #define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL 0x39db #define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL 0x39de #define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2vcdec:1 // base address: 0x76800 #define mmVML2VC1_VM_CONTEXT0_CNTL 0x3a00 #define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_CNTL 0x3a01 #define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_CNTL 0x3a02 #define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_CNTL 0x3a03 #define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_CNTL 0x3a04 #define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_CNTL 0x3a05 #define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_CNTL 0x3a06 #define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_CNTL 0x3a07 #define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_CNTL 0x3a08 #define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_CNTL 0x3a09 #define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_CNTL 0x3a0a #define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_CNTL 0x3a0b #define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_CNTL 0x3a0c #define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_CNTL 0x3a0d #define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_CNTL 0x3a0e #define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_CNTL 0x3a0f #define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXTS_DISABLE 0x3a10 #define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM 0x3a11 #define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM 0x3a12 #define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM 0x3a13 #define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM 0x3a14 #define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM 0x3a15 #define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM 0x3a16 #define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM 0x3a17 #define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM 0x3a18 #define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM 0x3a19 #define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM 0x3a1a #define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM 0x3a1b #define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM 0x3a1c #define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM 0x3a1d #define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM 0x3a1e #define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM 0x3a1f #define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM 0x3a20 #define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM 0x3a21 #define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM 0x3a22 #define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ 0x3a23 #define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ 0x3a24 #define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ 0x3a25 #define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ 0x3a26 #define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ 0x3a27 #define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ 0x3a28 #define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ 0x3a29 #define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ 0x3a2a #define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ 0x3a2b #define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ 0x3a2c #define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ 0x3a2d #define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ 0x3a2e #define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ 0x3a2f #define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ 0x3a30 #define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ 0x3a31 #define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ 0x3a32 #define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ 0x3a33 #define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ 0x3a34 #define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK 0x3a35 #define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK 0x3a36 #define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK 0x3a37 #define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK 0x3a38 #define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK 0x3a39 #define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK 0x3a3a #define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK 0x3a3b #define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK 0x3a3c #define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK 0x3a3d #define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK 0x3a3e #define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK 0x3a3f #define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK 0x3a40 #define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK 0x3a41 #define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK 0x3a42 #define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK 0x3a43 #define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK 0x3a44 #define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK 0x3a45 #define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK 0x3a46 #define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x3a47 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x3a48 #define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x3a49 #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x3a4a #define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x3a4b #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x3a4c #define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x3a4d #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x3a4e #define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x3a4f #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x3a50 #define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x3a51 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x3a52 #define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x3a53 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x3a54 #define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x3a55 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x3a56 #define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x3a57 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x3a58 #define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x3a59 #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x3a5a #define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x3a5b #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x3a5c #define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x3a5d #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x3a5e #define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x3a5f #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x3a60 #define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x3a61 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x3a62 #define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x3a63 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x3a64 #define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x3a65 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x3a66 #define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x3a67 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x3a68 #define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x3a69 #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x3a6a #define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x3a6b #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x3a6c #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x3a6d #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x3a6e #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x3a6f #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x3a70 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x3a71 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x3a72 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x3a73 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x3a74 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x3a75 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x3a76 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x3a77 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x3a78 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x3a79 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x3a7a #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x3a7b #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x3a7c #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x3a7d #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x3a7e #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x3a7f #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x3a80 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x3a81 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x3a82 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x3a83 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x3a84 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x3a85 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x3a86 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x3a87 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x3a88 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x3a89 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x3a8a #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x3a8b #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x3a8c #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x3a8d #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x3a8e #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x3a8f #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x3a90 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x3a91 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x3a92 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x3a93 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x3a94 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x3a95 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x3a96 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x3a97 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x3a98 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x3a99 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x3a9a #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x3a9b #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x3a9c #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x3a9d #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x3a9e #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x3a9f #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x3aa0 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x3aa1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x3aa2 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x3aa3 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x3aa4 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x3aa5 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x3aa6 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x3aa7 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x3aa8 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x3aa9 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x3aaa #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x3aab #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x3aac #define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x3aad #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x3aae #define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x3aaf #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x3ab0 #define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x3ab1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x3ab2 #define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x3ab3 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x3ab4 #define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x3ab5 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x3ab6 #define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x3ab7 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x3ab8 #define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x3ab9 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x3aba #define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x3abb #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x3abc #define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x3abd #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x3abe #define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x3abf #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x3ac0 #define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x3ac1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x3ac2 #define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x3ac3 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x3ac4 #define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x3ac5 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x3ac6 #define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x3ac7 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x3ac8 #define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x3ac9 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x3aca #define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 // addressBlock: mmhub_utcl2_vmsharedpfdec:1 // base address: 0x76b90 #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE 0x3ae4 #define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT 0x3ae5 #define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL 0x3ae6 #define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB 0x3ae7 #define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x3ae8 #define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x3ae9 #define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x3aea #define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_FB_OFFSET 0x3aeb #define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x3aec #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x3aed #define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_STEERING 0x3aee #define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX 1 #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 0x3aef #define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 #define mmVMSHAREDPF1_MC_MEM_POWER_LS 0x3af0 #define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x3af1 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x3af2 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_APT_CNTL 0x3af3 #define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 0x3af4 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 0x3af5 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x3af6 #define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 0x3af7 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 0x3af8 #define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 0x3af9 #define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vmsharedvcdec:1 // base address: 0x76c00 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE 0x3b00 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP 0x3b01 #define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_AGP_TOP 0x3b02 #define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_AGP_BOT 0x3b03 #define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_AGP_BASE 0x3b04 #define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x3b05 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x3b06 #define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 0x3b07 #define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vmsharedhvdec:1 // base address: 0x76c80 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 0x3b20 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 0x3b21 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 0x3b22 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 0x3b23 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 0x3b24 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 0x3b25 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 0x3b26 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 0x3b27 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 0x3b28 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 0x3b29 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 0x3b2a #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 0x3b2b #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 0x3b2c #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 0x3b2d #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 0x3b2e #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 0x3b2f #define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 0x3b30 #define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 0x3b31 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 0x3b32 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 0x3b33 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 0x3b34 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 0x3b35 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 0x3b36 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 0x3b37 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 0x3b38 #define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 0x3b39 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 0x3b3a #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 0x3b3b #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 0x3b3c #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 0x3b3d #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 0x3b3e #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 0x3b3f #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 0x3b40 #define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 0x3b41 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 0x3b42 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 0x3b43 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 0x3b44 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 0x3b45 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 0x3b46 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 0x3b47 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 0x3b48 #define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 0x3b49 #define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x3b4a #define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL 0x3b4b #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 0x3b4c #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 0x3b4d #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 0x3b4e #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 0x3b4f #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 0x3b50 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 0x3b51 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 0x3b52 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 0x3b53 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 0x3b54 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 0x3b55 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 0x3b56 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 0x3b57 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 0x3b58 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 0x3b59 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 0x3b5a #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 0x3b5b #define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 0x3b5c #define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 0x3b5d #define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 0x3b5e #define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 // base address: 0x76dc0 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 0x3b70 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 0x3b71 #define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 // addressBlock: mmhub_utcl2_atcl2pfcntldec:1 // base address: 0x76dd0 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 0x3b74 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 0x3b75 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3b76 #define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2pldec:1 // base address: 0x76e00 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 0x3b80 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 0x3b81 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 0x3b82 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 0x3b83 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 0x3b84 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 0x3b85 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 0x3b86 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 0x3b87 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3b88 #define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 // addressBlock: mmhub_utcl2_vml2prdec:1 // base address: 0x76e40 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO 0x3b90 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI 0x3b91 #define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 #endif