// SPDX-License-Identifier: MIT /* * Copyright (C) 2022 Advanced Micro Devices, Inc. * * Authors: AMD */ #ifndef _dpcs_4_2_2_OFFSET_HEADER #define _dpcs_4_2_2_OFFSET_HEADER // addressBlock: dpcssys_dpcssys_cr0_dispdec // base address: 0x0 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 #define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 #define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 // addressBlock: dpcssys_dpcssys_cr1_dispdec // base address: 0x360 #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c #define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 #define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d #define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 // addressBlock: dpcssys_dpcssys_cr2_dispdec // base address: 0x6c0 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 #define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 #define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 // addressBlock: dpcssys_dpcssys_cr3_dispdec // base address: 0xa20 #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc #define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 #define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd #define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 // addressBlock: dpcssys_dpcssys_cr4_dispdec // base address: 0xd80 #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 #define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 #define regDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 #define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 // addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec // base address: 0x0 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 // addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec // base address: 0x1b0 #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 // addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec // base address: 0x0 #define regRDPCSTX0_RDPCSTX_CNTL 0x2930 #define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 #define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 #define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA 0x2933 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 #define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 #define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 #define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_SCRATCH 0x2937 #define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_SPARE 0x2938 #define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_CNTL2 0x2939 #define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 #define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 #define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 #define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 #define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 #define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 #define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 #define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 #define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 #define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 #define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a #define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b #define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c #define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d #define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e #define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f #define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 #define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 #define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 #define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 #define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 #define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 #define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 #define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 #define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a #define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b #define regRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 #define regRDPCSTX0_RDPCS_CNTL3 0x295c #define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x295d #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x295e #define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 // addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec // base address: 0x360 #define regRDPCSTX1_RDPCSTX_CNTL 0x2a08 #define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 #define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a #define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA 0x2a0b #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c #define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d #define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e #define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f #define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_SPARE 0x2a10 #define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_CNTL2 0x2a11 #define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 #define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 #define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a #define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b #define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c #define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d #define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e #define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f #define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 #define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 #define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 #define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 #define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 #define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 #define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 #define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 #define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 #define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 #define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a #define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b #define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d #define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e #define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 #define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 #define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 #define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33 #define regRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 #define regRDPCSTX1_RDPCS_CNTL3 0x2a34 #define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2a35 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2a36 #define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 // addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec // base address: 0x6c0 #define regRDPCSTX2_RDPCSTX_CNTL 0x2ae0 #define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 #define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 #define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA 0x2ae3 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 #define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 #define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 #define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7 #define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_SPARE 0x2ae8 #define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 #define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 #define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 #define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 #define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 #define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 #define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 #define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 #define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 #define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 #define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa #define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb #define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc #define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd #define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe #define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff #define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 #define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 #define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 #define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 #define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 #define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 #define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 #define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 #define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a #define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b #define regRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 #define regRDPCSTX2_RDPCS_CNTL3 0x2b0c #define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2b0d #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2b0e #define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 // addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec // base address: 0xa20 #define regRDPCSTX3_RDPCSTX_CNTL 0x2bb8 #define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 #define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba #define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA 0x2bbb #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc #define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd #define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe #define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf #define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_SPARE 0x2bc0 #define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 #define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 #define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 #define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca #define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb #define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc #define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd #define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce #define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf #define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 #define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 #define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 #define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 #define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 #define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 #define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 #define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 #define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 #define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda #define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb #define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd #define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde #define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 #define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 #define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 #define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3 #define regRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 #define regRDPCSTX3_RDPCS_CNTL3 0x2be4 #define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2be5 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2be6 #define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 // addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec // base address: 0xd80 #define regRDPCSTX4_RDPCSTX_CNTL 0x2c90 #define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 #define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 #define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA 0x2c93 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 #define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 #define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 #define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_SCRATCH 0x2c97 #define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_SPARE 0x2c98 #define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_CNTL2 0x2c99 #define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 #define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 #define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 #define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 #define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 #define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 #define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 #define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 #define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 #define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa #define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab #define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac #define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad #define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae #define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf #define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 #define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 #define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 #define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 #define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 #define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 #define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8 #define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9 #define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba #define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2 #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0x2cbb #define regRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 #define regRDPCSTX4_RDPCS_CNTL3 0x2cbc #define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD 0x2cbd #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX 2 #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD 0x2cbe #define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_dispdec // base address: 0x0 #define regDC_GENERICA 0x2868 #define regDC_GENERICA_BASE_IDX 2 #define regDC_GENERICB 0x2869 #define regDC_GENERICB_BASE_IDX 2 #define regDCIO_CLOCK_CNTL 0x286a #define regDCIO_CLOCK_CNTL_BASE_IDX 2 #define regDC_REF_CLK_CNTL 0x286b #define regDC_REF_CLK_CNTL_BASE_IDX 2 #define regUNIPHYA_LINK_CNTL 0x286d #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define regUNIPHYB_LINK_CNTL 0x286f #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define regUNIPHYC_LINK_CNTL 0x2871 #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define regUNIPHYD_LINK_CNTL 0x2873 #define regUNIPHYD_LINK_CNTL_BASE_IDX 2 #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define regUNIPHYE_LINK_CNTL 0x2875 #define regUNIPHYE_LINK_CNTL_BASE_IDX 2 #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define regDCIO_WRCMD_DELAY 0x287e #define regDCIO_WRCMD_DELAY_BASE_IDX 2 #define regDC_PINSTRAPS 0x2880 #define regDC_PINSTRAPS_BASE_IDX 2 #define regINTERCEPT_STATE 0x2884 #define regINTERCEPT_STATE_BASE_IDX 2 #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 #define regDCIO_SOFT_RESET 0x289e #define regDCIO_SOFT_RESET_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_chip_dispdec // base address: 0x0 #define regDC_GPIO_GENERIC_MASK 0x28c8 #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 #define regDC_GPIO_GENERIC_A 0x28c9 #define regDC_GPIO_GENERIC_A_BASE_IDX 2 #define regDC_GPIO_GENERIC_EN 0x28ca #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 #define regDC_GPIO_GENERIC_Y 0x28cb #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 #define regDC_GPIO_DDC1_MASK 0x28d0 #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 #define regDC_GPIO_DDC1_A 0x28d1 #define regDC_GPIO_DDC1_A_BASE_IDX 2 #define regDC_GPIO_DDC1_EN 0x28d2 #define regDC_GPIO_DDC1_EN_BASE_IDX 2 #define regDC_GPIO_DDC1_Y 0x28d3 #define regDC_GPIO_DDC1_Y_BASE_IDX 2 #define regDC_GPIO_DDC2_MASK 0x28d4 #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 #define regDC_GPIO_DDC2_A 0x28d5 #define regDC_GPIO_DDC2_A_BASE_IDX 2 #define regDC_GPIO_DDC2_EN 0x28d6 #define regDC_GPIO_DDC2_EN_BASE_IDX 2 #define regDC_GPIO_DDC2_Y 0x28d7 #define regDC_GPIO_DDC2_Y_BASE_IDX 2 #define regDC_GPIO_DDC3_MASK 0x28d8 #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 #define regDC_GPIO_DDC3_A 0x28d9 #define regDC_GPIO_DDC3_A_BASE_IDX 2 #define regDC_GPIO_DDC3_EN 0x28da #define regDC_GPIO_DDC3_EN_BASE_IDX 2 #define regDC_GPIO_DDC3_Y 0x28db #define regDC_GPIO_DDC3_Y_BASE_IDX 2 #define regDC_GPIO_DDC4_MASK 0x28dc #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 #define regDC_GPIO_DDC4_A 0x28dd #define regDC_GPIO_DDC4_A_BASE_IDX 2 #define regDC_GPIO_DDC4_EN 0x28de #define regDC_GPIO_DDC4_EN_BASE_IDX 2 #define regDC_GPIO_DDC4_Y 0x28df #define regDC_GPIO_DDC4_Y_BASE_IDX 2 #define regDC_GPIO_DDC5_MASK 0x28e0 #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 #define regDC_GPIO_DDC5_A 0x28e1 #define regDC_GPIO_DDC5_A_BASE_IDX 2 #define regDC_GPIO_DDC5_EN 0x28e2 #define regDC_GPIO_DDC5_EN_BASE_IDX 2 #define regDC_GPIO_DDC5_Y 0x28e3 #define regDC_GPIO_DDC5_Y_BASE_IDX 2 #define regDC_GPIO_DDCVGA_MASK 0x28e8 #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 #define regDC_GPIO_DDCVGA_A 0x28e9 #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 #define regDC_GPIO_DDCVGA_EN 0x28ea #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 #define regDC_GPIO_DDCVGA_Y 0x28eb #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 #define regDC_GPIO_GENLK_MASK 0x28f0 #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 #define regDC_GPIO_GENLK_A 0x28f1 #define regDC_GPIO_GENLK_A_BASE_IDX 2 #define regDC_GPIO_GENLK_EN 0x28f2 #define regDC_GPIO_GENLK_EN_BASE_IDX 2 #define regDC_GPIO_GENLK_Y 0x28f3 #define regDC_GPIO_GENLK_Y_BASE_IDX 2 #define regDC_GPIO_HPD_MASK 0x28f4 #define regDC_GPIO_HPD_MASK_BASE_IDX 2 #define regDC_GPIO_HPD_A 0x28f5 #define regDC_GPIO_HPD_A_BASE_IDX 2 #define regDC_GPIO_HPD_EN 0x28f6 #define regDC_GPIO_HPD_EN_BASE_IDX 2 #define regDC_GPIO_HPD_Y 0x28f7 #define regDC_GPIO_HPD_Y_BASE_IDX 2 #define regDC_GPIO_PWRSEQ0_EN 0x28fa #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 #define regDC_GPIO_PAD_STRENGTH_1 0x28fc #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 #define regDC_GPIO_PAD_STRENGTH_2 0x28fd #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 #define regPHY_AUX_CNTL 0x28ff #define regPHY_AUX_CNTL_BASE_IDX 2 #define regDC_GPIO_PWRSEQ1_EN 0x2902 #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 #define regDC_GPIO_TX12_EN 0x2915 #define regDC_GPIO_TX12_EN_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_0 0x2916 #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_1 0x2917 #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_2 0x2918 #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 #define regDC_GPIO_RXEN 0x2919 #define regDC_GPIO_RXEN_BASE_IDX 2 #define regDC_GPIO_PULLUPEN 0x291a #define regDC_GPIO_PULLUPEN_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_3 0x291b #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_4 0x291c #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 #define regDC_GPIO_AUX_CTRL_5 0x291d #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 #define regAUXI2C_PAD_ALL_PWR_OK 0x291e #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec // base address: 0x360 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec // base address: 0x6c0 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec // base address: 0xa20 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 // addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec // base address: 0xd80 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 // addressBlock: dpcssys_cr0_rdpcstxcrind // base address: 0x0 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000 #define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001 #define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3 0x000e #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4 0x000f #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3 0x001a #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4 0x001b #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5 0x001c #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN 0x001f #define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN 0x0020 #define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT 0x0021 #define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN 0x0022 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6 0x002a #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0 0x002b #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1 0x002c #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2 0x002d #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3 0x002e #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4 0x002f #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 #define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN 0x0036 #define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN 0x0037 #define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN 0x0038 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c #define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL 0x0040 #define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL 0x0041 #define ixDPCSSYS_CR0_SUP_ANA_BG1 0x0042 #define ixDPCSSYS_CR0_SUP_ANA_BG2 0x0043 #define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS 0x0044 #define ixDPCSSYS_CR0_SUP_ANA_BG3 0x0045 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1 0x0046 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2 0x0047 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD 0x0048 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1 0x0049 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2 0x004a #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3 0x004b #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1 0x004c #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2 0x004d #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3 0x004e #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4 0x004f #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5 0x0050 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1 0x0051 #define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2 0x0052 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1 0x0053 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2 0x0054 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD 0x0055 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1 0x0056 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2 0x0057 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3 0x0058 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1 0x0059 #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2 0x005a #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3 0x005b #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4 0x005c #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5 0x005d #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1 0x005e #define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2 0x005f #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 #define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 #define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b #define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD 0x007c #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG 0x0081 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT 0x0082 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT 0x0086 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT 0x0087 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT 0x0088 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a #define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 #define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 #define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT 0x0093 #define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 #define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d #define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f #define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 #define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 #define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL 0x1032 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 #define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0 0x10bb #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 #define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS 0x10e0 #define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD 0x10e1 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS 0x10e2 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1 0x10e3 #define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2 0x10e4 #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC 0x10e5 #define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1 0x10e6 #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE 0x10e7 #define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 #define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK 0x10e9 #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1 0x10ea #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2 0x10eb #define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3 0x10ec #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2 0x10ed #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3 0x10ee #define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4 0x10ef #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e #define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA 0x111f #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f #define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 #define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 #define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL 0x1132 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 #define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e #define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f #define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL 0x1151 #define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR 0x1152 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 #define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT 0x1158 #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ 0x1159 #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a #define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e #define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 #define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 #define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL 0x11ae #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE 0x11b4 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0 0x11bb #define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1 0x11bc #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd #define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be #define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 #define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS 0x11e0 #define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD 0x11e1 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS 0x11e2 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1 0x11e3 #define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2 0x11e4 #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC 0x11e5 #define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1 0x11e6 #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE 0x11e7 #define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 #define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK 0x11e9 #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1 0x11ea #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2 0x11eb #define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3 0x11ec #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2 0x11ed #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3 0x11ee #define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4 0x11ef #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1 0x11f0 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2 0x11f1 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES 0x11f2 #define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL 0x11f3 #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1 0x11f4 #define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2 0x11f5 #define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ 0x11f6 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1 0x11f7 #define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2 0x11f8 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF 0x11f9 #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1 0x11fa #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2 0x11fb #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3 0x11fc #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4 0x11fd #define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC 0x11fe #define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1 0x11ff #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e #define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA 0x121f #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f #define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 #define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 #define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL 0x1232 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 #define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e #define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f #define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL 0x1251 #define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR 0x1252 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 #define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT 0x1258 #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ 0x1259 #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a #define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e #define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 #define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 #define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL 0x12ae #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE 0x12b4 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0 0x12bb #define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1 0x12bc #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd #define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be #define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 #define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS 0x12e0 #define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD 0x12e1 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS 0x12e2 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1 0x12e3 #define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2 0x12e4 #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC 0x12e5 #define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1 0x12e6 #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE 0x12e7 #define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 #define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK 0x12e9 #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1 0x12ea #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2 0x12eb #define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3 0x12ec #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2 0x12ed #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3 0x12ee #define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4 0x12ef #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1 0x12f0 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2 0x12f1 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES 0x12f2 #define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL 0x12f3 #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1 0x12f4 #define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2 0x12f5 #define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ 0x12f6 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1 0x12f7 #define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2 0x12f8 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF 0x12f9 #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1 0x12fa #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2 0x12fb #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3 0x12fc #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4 0x12fd #define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC 0x12fe #define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1 0x12ff #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d #define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f #define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 #define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 #define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL 0x1332 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 #define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0 0x13bb #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 #define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS 0x13e0 #define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD 0x13e1 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS 0x13e2 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1 0x13e3 #define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2 0x13e4 #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC 0x13e5 #define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1 0x13e6 #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE 0x13e7 #define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 #define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK 0x13e9 #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1 0x13ea #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2 0x13eb #define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3 0x13ec #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2 0x13ed #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3 0x13ee #define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4 0x13ef #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL 0x2000 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 #define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 #define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1 0x200a #define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL 0x200b #define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE 0x200c #define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE 0x200d #define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA 0x200e #define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD 0x200f #define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1 0x2011 #define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2 0x2012 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f #define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP 0x302c #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA 0x303c #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e #define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a #define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b #define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 #define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 #define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 #define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP 0x312c #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA 0x313c #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e #define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a #define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b #define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 #define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 #define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 #define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP 0x322c #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA 0x323c #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e #define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a #define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b #define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 #define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 #define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 #define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP 0x332c #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA 0x333c #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e #define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a #define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b #define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 #define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 #define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 #define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS 0x401c #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS 0x4032 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 #define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS 0x411c #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS 0x4132 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 #define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS 0x421c #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS 0x4232 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 #define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS 0x431c #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS 0x4332 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 #define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS 0x701c #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS 0x7032 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 #define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO 0x8000 #define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI 0x8001 #define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN 0x8002 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN 0x801f #define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 #define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT 0x8021 #define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN 0x8022 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 #define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN 0x8036 #define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN 0x8037 #define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c #define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL 0x8040 #define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL 0x8041 #define ixDPCSSYS_CR0_SUPX_ANA_BG1 0x8042 #define ixDPCSSYS_CR0_SUPX_ANA_BG2 0x8043 #define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 #define ixDPCSSYS_CR0_SUPX_ANA_BG3 0x8045 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1 0x8046 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2 0x8047 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD 0x8048 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1 0x8049 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2 0x804a #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3 0x804b #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1 0x804c #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2 0x804d #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3 0x804e #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4 0x804f #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5 0x8050 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1 0x8051 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2 0x8052 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1 0x8053 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2 0x8054 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD 0x8055 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1 0x8056 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2 0x8057 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3 0x8058 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1 0x8059 #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2 0x805a #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3 0x805b #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4 0x805c #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5 0x805d #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1 0x805e #define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2 0x805f #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 #define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b #define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG 0x8081 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT 0x8082 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT 0x8086 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a #define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT 0x8093 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 #define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e #define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA 0x901f #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f #define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 #define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 #define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL 0x9032 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 #define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e #define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f #define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL 0x9051 #define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR 0x9052 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 #define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT 0x9058 #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ 0x9059 #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a #define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e #define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 #define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 #define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL 0x90ae #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE 0x90b4 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0 0x90bb #define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1 0x90bc #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd #define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be #define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 #define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS 0x90e0 #define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD 0x90e1 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS 0x90e2 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1 0x90e3 #define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2 0x90e4 #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC 0x90e5 #define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1 0x90e6 #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE 0x90e7 #define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 #define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK 0x90e9 #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1 0x90ea #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2 0x90eb #define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3 0x90ec #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2 0x90ed #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3 0x90ee #define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4 0x90ef #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1 0x90f0 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2 0x90f1 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES 0x90f2 #define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL 0x90f3 #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1 0x90f4 #define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2 0x90f5 #define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ 0x90f6 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1 0x90f7 #define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2 0x90f8 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF 0x90f9 #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1 0x90fa #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2 0x90fb #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3 0x90fc #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4 0x90fd #define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC 0x90fe #define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1 0x90ff #define ixDPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 #define ixDPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA 0xe03c #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e #define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a #define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b #define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 #define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 #define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 #define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 // addressBlock: dpcssys_cr1_rdpcstxcrind // base address: 0x0 #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO 0x0000 #define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI 0x0001 #define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN 0x0002 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3 0x000e #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4 0x000f #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3 0x001a #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4 0x001b #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5 0x001c #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN 0x001f #define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN 0x0020 #define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT 0x0021 #define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN 0x0022 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6 0x002a #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0 0x002b #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1 0x002c #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2 0x002d #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3 0x002e #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4 0x002f #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 #define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN 0x0036 #define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN 0x0037 #define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN 0x0038 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c #define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL 0x0040 #define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL 0x0041 #define ixDPCSSYS_CR1_SUP_ANA_BG1 0x0042 #define ixDPCSSYS_CR1_SUP_ANA_BG2 0x0043 #define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS 0x0044 #define ixDPCSSYS_CR1_SUP_ANA_BG3 0x0045 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1 0x0046 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2 0x0047 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD 0x0048 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1 0x0049 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2 0x004a #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3 0x004b #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1 0x004c #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2 0x004d #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3 0x004e #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4 0x004f #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5 0x0050 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1 0x0051 #define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2 0x0052 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1 0x0053 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2 0x0054 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD 0x0055 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1 0x0056 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2 0x0057 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3 0x0058 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1 0x0059 #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2 0x005a #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3 0x005b #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4 0x005c #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5 0x005d #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1 0x005e #define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2 0x005f #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 #define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 #define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b #define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD 0x007c #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG 0x0081 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT 0x0082 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT 0x0086 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT 0x0087 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT 0x0088 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a #define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 #define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 #define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT 0x0093 #define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 #define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d #define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f #define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 #define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 #define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL 0x1032 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 #define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0 0x10bb #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 #define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS 0x10e0 #define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD 0x10e1 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS 0x10e2 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1 0x10e3 #define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2 0x10e4 #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC 0x10e5 #define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1 0x10e6 #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE 0x10e7 #define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 #define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK 0x10e9 #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1 0x10ea #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2 0x10eb #define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3 0x10ec #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2 0x10ed #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3 0x10ee #define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4 0x10ef #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e #define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA 0x111f #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f #define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 #define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 #define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL 0x1132 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 #define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e #define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f #define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL 0x1151 #define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR 0x1152 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 #define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT 0x1158 #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ 0x1159 #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a #define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e #define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 #define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 #define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL 0x11ae #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE 0x11b4 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0 0x11bb #define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1 0x11bc #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd #define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be #define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 #define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS 0x11e0 #define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD 0x11e1 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS 0x11e2 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1 0x11e3 #define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2 0x11e4 #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC 0x11e5 #define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1 0x11e6 #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE 0x11e7 #define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 #define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK 0x11e9 #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1 0x11ea #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2 0x11eb #define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3 0x11ec #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2 0x11ed #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3 0x11ee #define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4 0x11ef #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1 0x11f0 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2 0x11f1 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES 0x11f2 #define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL 0x11f3 #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1 0x11f4 #define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2 0x11f5 #define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ 0x11f6 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1 0x11f7 #define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2 0x11f8 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF 0x11f9 #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1 0x11fa #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2 0x11fb #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3 0x11fc #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4 0x11fd #define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC 0x11fe #define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1 0x11ff #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e #define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA 0x121f #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f #define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 #define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 #define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL 0x1232 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 #define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e #define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f #define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL 0x1251 #define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR 0x1252 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 #define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT 0x1258 #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ 0x1259 #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a #define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e #define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 #define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 #define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL 0x12ae #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE 0x12b4 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0 0x12bb #define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1 0x12bc #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd #define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be #define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 #define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS 0x12e0 #define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD 0x12e1 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS 0x12e2 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1 0x12e3 #define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2 0x12e4 #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC 0x12e5 #define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1 0x12e6 #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE 0x12e7 #define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 #define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK 0x12e9 #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1 0x12ea #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2 0x12eb #define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3 0x12ec #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2 0x12ed #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3 0x12ee #define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4 0x12ef #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1 0x12f0 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2 0x12f1 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES 0x12f2 #define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL 0x12f3 #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1 0x12f4 #define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2 0x12f5 #define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ 0x12f6 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1 0x12f7 #define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2 0x12f8 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF 0x12f9 #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1 0x12fa #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2 0x12fb #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3 0x12fc #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4 0x12fd #define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC 0x12fe #define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1 0x12ff #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d #define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f #define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 #define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 #define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL 0x1332 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 #define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0 0x13bb #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 #define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS 0x13e0 #define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD 0x13e1 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS 0x13e2 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1 0x13e3 #define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2 0x13e4 #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC 0x13e5 #define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1 0x13e6 #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE 0x13e7 #define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 #define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK 0x13e9 #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1 0x13ea #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2 0x13eb #define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3 0x13ec #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2 0x13ed #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3 0x13ee #define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4 0x13ef #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL 0x2000 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 #define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 #define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1 0x200a #define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL 0x200b #define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE 0x200c #define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE 0x200d #define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA 0x200e #define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD 0x200f #define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1 0x2011 #define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2 0x2012 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f #define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP 0x302c #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA 0x303c #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e #define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a #define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b #define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 #define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 #define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 #define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP 0x312c #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA 0x313c #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e #define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a #define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b #define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 #define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 #define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 #define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP 0x322c #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA 0x323c #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e #define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a #define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b #define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 #define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 #define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 #define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP 0x332c #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA 0x333c #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e #define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a #define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b #define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 #define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 #define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 #define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS 0x401c #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS 0x4032 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 #define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS 0x411c #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS 0x4132 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 #define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS 0x421c #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS 0x4232 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 #define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS 0x431c #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS 0x4332 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 #define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS 0x701c #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS 0x7032 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 #define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO 0x8000 #define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI 0x8001 #define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN 0x8002 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN 0x801f #define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 #define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT 0x8021 #define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN 0x8022 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 #define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN 0x8036 #define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN 0x8037 #define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c #define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL 0x8040 #define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL 0x8041 #define ixDPCSSYS_CR1_SUPX_ANA_BG1 0x8042 #define ixDPCSSYS_CR1_SUPX_ANA_BG2 0x8043 #define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 #define ixDPCSSYS_CR1_SUPX_ANA_BG3 0x8045 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1 0x8046 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2 0x8047 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD 0x8048 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1 0x8049 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2 0x804a #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3 0x804b #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1 0x804c #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2 0x804d #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3 0x804e #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4 0x804f #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5 0x8050 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1 0x8051 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2 0x8052 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1 0x8053 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2 0x8054 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD 0x8055 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1 0x8056 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2 0x8057 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3 0x8058 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1 0x8059 #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2 0x805a #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3 0x805b #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4 0x805c #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5 0x805d #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1 0x805e #define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2 0x805f #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 #define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b #define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG 0x8081 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT 0x8082 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT 0x8086 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a #define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT 0x8093 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 #define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e #define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA 0x901f #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f #define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 #define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 #define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL 0x9032 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 #define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e #define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f #define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL 0x9051 #define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR 0x9052 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 #define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT 0x9058 #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ 0x9059 #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a #define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e #define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 #define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 #define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL 0x90ae #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE 0x90b4 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0 0x90bb #define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1 0x90bc #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd #define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be #define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 #define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS 0x90e0 #define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD 0x90e1 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS 0x90e2 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1 0x90e3 #define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2 0x90e4 #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC 0x90e5 #define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1 0x90e6 #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE 0x90e7 #define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 #define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK 0x90e9 #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1 0x90ea #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2 0x90eb #define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3 0x90ec #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2 0x90ed #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3 0x90ee #define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4 0x90ef #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1 0x90f0 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2 0x90f1 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES 0x90f2 #define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL 0x90f3 #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1 0x90f4 #define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2 0x90f5 #define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ 0x90f6 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1 0x90f7 #define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2 0x90f8 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF 0x90f9 #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1 0x90fa #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2 0x90fb #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3 0x90fc #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4 0x90fd #define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC 0x90fe #define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1 0x90ff #define ixDPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 #define ixDPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA 0xe03c #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e #define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a #define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b #define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 #define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 #define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 #define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 // addressBlock: dpcssys_cr2_rdpcstxcrind // base address: 0x0 #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO 0x0000 #define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI 0x0001 #define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN 0x0002 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3 0x000e #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4 0x000f #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3 0x001a #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4 0x001b #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5 0x001c #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN 0x001f #define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN 0x0020 #define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT 0x0021 #define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN 0x0022 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6 0x002a #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0 0x002b #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1 0x002c #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2 0x002d #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3 0x002e #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4 0x002f #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 #define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN 0x0036 #define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN 0x0037 #define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN 0x0038 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c #define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL 0x0040 #define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL 0x0041 #define ixDPCSSYS_CR2_SUP_ANA_BG1 0x0042 #define ixDPCSSYS_CR2_SUP_ANA_BG2 0x0043 #define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS 0x0044 #define ixDPCSSYS_CR2_SUP_ANA_BG3 0x0045 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1 0x0046 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2 0x0047 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD 0x0048 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1 0x0049 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2 0x004a #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3 0x004b #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1 0x004c #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2 0x004d #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3 0x004e #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4 0x004f #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5 0x0050 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1 0x0051 #define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2 0x0052 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1 0x0053 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2 0x0054 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD 0x0055 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1 0x0056 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2 0x0057 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3 0x0058 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1 0x0059 #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2 0x005a #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3 0x005b #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4 0x005c #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5 0x005d #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1 0x005e #define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2 0x005f #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 #define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 #define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b #define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD 0x007c #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG 0x0081 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT 0x0082 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT 0x0086 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT 0x0087 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT 0x0088 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a #define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 #define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 #define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT 0x0093 #define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 #define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d #define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f #define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 #define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 #define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL 0x1032 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 #define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0 0x10bb #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 #define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS 0x10e0 #define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD 0x10e1 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS 0x10e2 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1 0x10e3 #define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2 0x10e4 #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC 0x10e5 #define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1 0x10e6 #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE 0x10e7 #define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 #define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK 0x10e9 #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1 0x10ea #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2 0x10eb #define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3 0x10ec #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2 0x10ed #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3 0x10ee #define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4 0x10ef #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e #define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA 0x111f #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f #define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 #define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 #define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL 0x1132 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 #define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e #define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f #define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL 0x1151 #define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR 0x1152 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 #define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT 0x1158 #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ 0x1159 #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a #define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e #define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 #define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 #define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL 0x11ae #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE 0x11b4 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0 0x11bb #define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1 0x11bc #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd #define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be #define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 #define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS 0x11e0 #define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD 0x11e1 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS 0x11e2 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1 0x11e3 #define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2 0x11e4 #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC 0x11e5 #define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1 0x11e6 #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE 0x11e7 #define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 #define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK 0x11e9 #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1 0x11ea #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2 0x11eb #define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3 0x11ec #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2 0x11ed #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3 0x11ee #define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4 0x11ef #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1 0x11f0 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2 0x11f1 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES 0x11f2 #define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL 0x11f3 #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1 0x11f4 #define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2 0x11f5 #define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ 0x11f6 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1 0x11f7 #define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2 0x11f8 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF 0x11f9 #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1 0x11fa #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2 0x11fb #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3 0x11fc #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4 0x11fd #define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC 0x11fe #define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1 0x11ff #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e #define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA 0x121f #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f #define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 #define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 #define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL 0x1232 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 #define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e #define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f #define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL 0x1251 #define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR 0x1252 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 #define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT 0x1258 #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ 0x1259 #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a #define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e #define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 #define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 #define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL 0x12ae #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE 0x12b4 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0 0x12bb #define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1 0x12bc #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd #define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be #define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 #define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS 0x12e0 #define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD 0x12e1 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS 0x12e2 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1 0x12e3 #define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2 0x12e4 #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC 0x12e5 #define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1 0x12e6 #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE 0x12e7 #define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 #define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK 0x12e9 #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1 0x12ea #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2 0x12eb #define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3 0x12ec #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2 0x12ed #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3 0x12ee #define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4 0x12ef #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1 0x12f0 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2 0x12f1 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES 0x12f2 #define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL 0x12f3 #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1 0x12f4 #define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2 0x12f5 #define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ 0x12f6 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1 0x12f7 #define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2 0x12f8 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF 0x12f9 #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1 0x12fa #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2 0x12fb #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3 0x12fc #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4 0x12fd #define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC 0x12fe #define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1 0x12ff #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d #define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f #define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 #define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 #define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL 0x1332 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 #define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0 0x13bb #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 #define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS 0x13e0 #define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD 0x13e1 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS 0x13e2 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1 0x13e3 #define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2 0x13e4 #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC 0x13e5 #define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1 0x13e6 #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE 0x13e7 #define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 #define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK 0x13e9 #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1 0x13ea #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2 0x13eb #define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3 0x13ec #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2 0x13ed #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3 0x13ee #define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4 0x13ef #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL 0x2000 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 #define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 #define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1 0x200a #define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL 0x200b #define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE 0x200c #define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE 0x200d #define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA 0x200e #define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD 0x200f #define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1 0x2011 #define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2 0x2012 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f #define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP 0x302c #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA 0x303c #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e #define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a #define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b #define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 #define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 #define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 #define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP 0x312c #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA 0x313c #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e #define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a #define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b #define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 #define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 #define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 #define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP 0x322c #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA 0x323c #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e #define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a #define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b #define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 #define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 #define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 #define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP 0x332c #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA 0x333c #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e #define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a #define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b #define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 #define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 #define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 #define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS 0x401c #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS 0x4032 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 #define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS 0x411c #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS 0x4132 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 #define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS 0x421c #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS 0x4232 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 #define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS 0x431c #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS 0x4332 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 #define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS 0x701c #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS 0x7032 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 #define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO 0x8000 #define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI 0x8001 #define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN 0x8002 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN 0x801f #define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 #define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT 0x8021 #define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN 0x8022 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 #define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN 0x8036 #define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN 0x8037 #define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c #define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL 0x8040 #define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL 0x8041 #define ixDPCSSYS_CR2_SUPX_ANA_BG1 0x8042 #define ixDPCSSYS_CR2_SUPX_ANA_BG2 0x8043 #define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 #define ixDPCSSYS_CR2_SUPX_ANA_BG3 0x8045 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1 0x8046 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2 0x8047 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD 0x8048 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1 0x8049 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2 0x804a #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3 0x804b #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1 0x804c #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2 0x804d #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3 0x804e #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4 0x804f #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5 0x8050 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1 0x8051 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2 0x8052 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1 0x8053 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2 0x8054 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD 0x8055 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1 0x8056 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2 0x8057 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3 0x8058 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1 0x8059 #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2 0x805a #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3 0x805b #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4 0x805c #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5 0x805d #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1 0x805e #define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2 0x805f #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 #define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b #define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG 0x8081 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT 0x8082 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT 0x8086 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a #define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT 0x8093 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 #define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e #define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA 0x901f #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f #define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 #define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 #define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL 0x9032 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 #define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e #define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f #define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL 0x9051 #define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR 0x9052 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 #define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT 0x9058 #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ 0x9059 #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a #define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e #define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 #define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 #define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL 0x90ae #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE 0x90b4 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0 0x90bb #define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1 0x90bc #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd #define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be #define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 #define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS 0x90e0 #define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD 0x90e1 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS 0x90e2 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1 0x90e3 #define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2 0x90e4 #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC 0x90e5 #define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1 0x90e6 #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE 0x90e7 #define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 #define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK 0x90e9 #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1 0x90ea #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2 0x90eb #define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3 0x90ec #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2 0x90ed #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3 0x90ee #define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4 0x90ef #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1 0x90f0 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2 0x90f1 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES 0x90f2 #define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL 0x90f3 #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1 0x90f4 #define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2 0x90f5 #define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ 0x90f6 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1 0x90f7 #define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2 0x90f8 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF 0x90f9 #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1 0x90fa #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2 0x90fb #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3 0x90fc #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4 0x90fd #define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC 0x90fe #define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1 0x90ff #define ixDPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 #define ixDPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA 0xe03c #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e #define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a #define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b #define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 #define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 #define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 #define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 // addressBlock: dpcssys_cr3_rdpcstxcrind // base address: 0x0 #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO 0x0000 #define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI 0x0001 #define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN 0x0002 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3 0x000e #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4 0x000f #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3 0x001a #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4 0x001b #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5 0x001c #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN 0x001f #define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN 0x0020 #define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT 0x0021 #define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN 0x0022 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6 0x002a #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0 0x002b #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1 0x002c #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2 0x002d #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3 0x002e #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4 0x002f #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 #define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN 0x0036 #define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN 0x0037 #define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN 0x0038 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c #define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL 0x0040 #define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL 0x0041 #define ixDPCSSYS_CR3_SUP_ANA_BG1 0x0042 #define ixDPCSSYS_CR3_SUP_ANA_BG2 0x0043 #define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS 0x0044 #define ixDPCSSYS_CR3_SUP_ANA_BG3 0x0045 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1 0x0046 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2 0x0047 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD 0x0048 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1 0x0049 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2 0x004a #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3 0x004b #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1 0x004c #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2 0x004d #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3 0x004e #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4 0x004f #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5 0x0050 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1 0x0051 #define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2 0x0052 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1 0x0053 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2 0x0054 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD 0x0055 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1 0x0056 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2 0x0057 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3 0x0058 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1 0x0059 #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2 0x005a #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3 0x005b #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4 0x005c #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5 0x005d #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1 0x005e #define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2 0x005f #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 #define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 #define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b #define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD 0x007c #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG 0x0081 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT 0x0082 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT 0x0086 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT 0x0087 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT 0x0088 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a #define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 #define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 #define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT 0x0093 #define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 #define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d #define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f #define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 #define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 #define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL 0x1032 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 #define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0 0x10bb #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 #define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS 0x10e0 #define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD 0x10e1 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS 0x10e2 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1 0x10e3 #define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2 0x10e4 #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC 0x10e5 #define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1 0x10e6 #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE 0x10e7 #define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 #define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK 0x10e9 #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1 0x10ea #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2 0x10eb #define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3 0x10ec #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2 0x10ed #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3 0x10ee #define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4 0x10ef #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e #define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA 0x111f #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f #define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 #define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 #define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL 0x1132 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 #define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e #define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f #define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL 0x1151 #define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR 0x1152 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 #define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT 0x1158 #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ 0x1159 #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a #define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e #define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 #define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 #define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL 0x11ae #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE 0x11b4 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0 0x11bb #define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1 0x11bc #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd #define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be #define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 #define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS 0x11e0 #define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD 0x11e1 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS 0x11e2 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1 0x11e3 #define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2 0x11e4 #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC 0x11e5 #define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1 0x11e6 #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE 0x11e7 #define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 #define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK 0x11e9 #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1 0x11ea #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2 0x11eb #define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3 0x11ec #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2 0x11ed #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3 0x11ee #define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4 0x11ef #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1 0x11f0 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2 0x11f1 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES 0x11f2 #define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL 0x11f3 #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1 0x11f4 #define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2 0x11f5 #define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ 0x11f6 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1 0x11f7 #define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2 0x11f8 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF 0x11f9 #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1 0x11fa #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2 0x11fb #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3 0x11fc #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4 0x11fd #define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC 0x11fe #define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1 0x11ff #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e #define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA 0x121f #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f #define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 #define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 #define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL 0x1232 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 #define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e #define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f #define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL 0x1251 #define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR 0x1252 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 #define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT 0x1258 #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ 0x1259 #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a #define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e #define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 #define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 #define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL 0x12ae #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE 0x12b4 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0 0x12bb #define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1 0x12bc #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd #define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be #define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 #define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS 0x12e0 #define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD 0x12e1 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS 0x12e2 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1 0x12e3 #define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2 0x12e4 #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC 0x12e5 #define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1 0x12e6 #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE 0x12e7 #define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 #define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK 0x12e9 #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1 0x12ea #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2 0x12eb #define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3 0x12ec #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2 0x12ed #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3 0x12ee #define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4 0x12ef #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1 0x12f0 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2 0x12f1 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES 0x12f2 #define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL 0x12f3 #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1 0x12f4 #define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2 0x12f5 #define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ 0x12f6 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1 0x12f7 #define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2 0x12f8 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF 0x12f9 #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1 0x12fa #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2 0x12fb #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3 0x12fc #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4 0x12fd #define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC 0x12fe #define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1 0x12ff #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d #define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f #define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 #define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 #define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL 0x1332 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 #define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0 0x13bb #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 #define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS 0x13e0 #define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD 0x13e1 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS 0x13e2 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1 0x13e3 #define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2 0x13e4 #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC 0x13e5 #define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1 0x13e6 #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE 0x13e7 #define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 #define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK 0x13e9 #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1 0x13ea #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2 0x13eb #define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3 0x13ec #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2 0x13ed #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3 0x13ee #define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4 0x13ef #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL 0x2000 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 #define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 #define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1 0x200a #define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL 0x200b #define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE 0x200c #define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE 0x200d #define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA 0x200e #define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD 0x200f #define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1 0x2011 #define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2 0x2012 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f #define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP 0x302c #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA 0x303c #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e #define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a #define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b #define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 #define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 #define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 #define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP 0x312c #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA 0x313c #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e #define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a #define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b #define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 #define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 #define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 #define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP 0x322c #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA 0x323c #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e #define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a #define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b #define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 #define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 #define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 #define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP 0x332c #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA 0x333c #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e #define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a #define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b #define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 #define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 #define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 #define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS 0x401c #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS 0x4032 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 #define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS 0x411c #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS 0x4132 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 #define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS 0x421c #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS 0x4232 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 #define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS 0x431c #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS 0x4332 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 #define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS 0x701c #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS 0x7032 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 #define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO 0x8000 #define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI 0x8001 #define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN 0x8002 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN 0x801f #define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 #define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT 0x8021 #define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN 0x8022 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 #define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN 0x8036 #define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN 0x8037 #define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c #define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL 0x8040 #define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL 0x8041 #define ixDPCSSYS_CR3_SUPX_ANA_BG1 0x8042 #define ixDPCSSYS_CR3_SUPX_ANA_BG2 0x8043 #define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 #define ixDPCSSYS_CR3_SUPX_ANA_BG3 0x8045 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1 0x8046 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2 0x8047 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD 0x8048 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1 0x8049 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2 0x804a #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3 0x804b #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1 0x804c #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2 0x804d #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3 0x804e #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4 0x804f #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5 0x8050 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1 0x8051 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2 0x8052 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1 0x8053 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2 0x8054 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD 0x8055 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1 0x8056 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2 0x8057 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3 0x8058 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1 0x8059 #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2 0x805a #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3 0x805b #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4 0x805c #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5 0x805d #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1 0x805e #define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2 0x805f #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 #define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b #define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG 0x8081 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT 0x8082 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT 0x8086 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a #define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT 0x8093 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 #define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e #define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA 0x901f #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f #define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 #define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 #define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL 0x9032 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 #define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e #define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f #define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL 0x9051 #define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR 0x9052 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 #define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT 0x9058 #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ 0x9059 #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a #define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e #define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 #define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 #define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL 0x90ae #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE 0x90b4 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0 0x90bb #define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1 0x90bc #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd #define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be #define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 #define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS 0x90e0 #define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD 0x90e1 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS 0x90e2 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1 0x90e3 #define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2 0x90e4 #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC 0x90e5 #define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1 0x90e6 #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE 0x90e7 #define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 #define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK 0x90e9 #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1 0x90ea #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2 0x90eb #define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3 0x90ec #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2 0x90ed #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3 0x90ee #define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4 0x90ef #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1 0x90f0 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2 0x90f1 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES 0x90f2 #define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL 0x90f3 #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1 0x90f4 #define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2 0x90f5 #define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ 0x90f6 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1 0x90f7 #define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2 0x90f8 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF 0x90f9 #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1 0x90fa #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2 0x90fb #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3 0x90fc #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4 0x90fd #define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC 0x90fe #define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1 0x90ff #define ixDPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 #define ixDPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA 0xe03c #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e #define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a #define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b #define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 #define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 #define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 #define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 // addressBlock: dpcssys_cr4_rdpcstxcrind // base address: 0x0 #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO 0x0000 #define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI 0x0001 #define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN 0x0002 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0 0x0007 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1 0x0008 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2 0x0009 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1 0x000a #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2 0x000b #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1 0x000c #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2 0x000d #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3 0x000e #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4 0x000f #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5 0x0010 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN 0x0011 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN 0x0012 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0 0x0013 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1 0x0014 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2 0x0015 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1 0x0016 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2 0x0017 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1 0x0018 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2 0x0019 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3 0x001a #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4 0x001b #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5 0x001c #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN 0x001d #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN 0x001e #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN 0x001f #define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN 0x0020 #define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT 0x0021 #define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN 0x0022 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0 0x0024 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1 0x0025 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2 0x0026 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3 0x0027 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4 0x0028 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5 0x0029 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6 0x002a #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0 0x002b #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1 0x002c #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2 0x002d #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3 0x002e #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4 0x002f #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5 0x0030 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6 0x0031 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN 0x0032 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x0033 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN 0x0034 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x0035 #define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN 0x0036 #define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN 0x0037 #define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN 0x0038 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN 0x0039 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN 0x003a #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN 0x003b #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN 0x003c #define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL 0x0040 #define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL 0x0041 #define ixDPCSSYS_CR4_SUP_ANA_BG1 0x0042 #define ixDPCSSYS_CR4_SUP_ANA_BG2 0x0043 #define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS 0x0044 #define ixDPCSSYS_CR4_SUP_ANA_BG3 0x0045 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1 0x0046 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2 0x0047 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD 0x0048 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1 0x0049 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2 0x004a #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3 0x004b #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1 0x004c #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2 0x004d #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3 0x004e #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4 0x004f #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5 0x0050 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1 0x0051 #define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2 0x0052 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1 0x0053 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2 0x0054 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD 0x0055 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1 0x0056 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2 0x0057 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3 0x0058 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1 0x0059 #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2 0x005a #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3 0x005b #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4 0x005c #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5 0x005d #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1 0x005e #define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2 0x005f #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x0061 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x0062 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x0063 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0064 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x0065 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0066 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0067 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x0068 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0069 #define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x006b #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x006d #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x006e #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x006f #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x0070 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x0071 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x0072 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x0073 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x0074 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x0075 #define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x0077 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 0x0078 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 0x0079 #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2 0x007a #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0 0x007b #define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD 0x007c #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG 0x0081 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT 0x0082 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL 0x0083 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL 0x0084 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL 0x0085 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT 0x0086 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT 0x0087 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT 0x0088 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0 0x0089 #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1 0x008a #define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE 0x008b #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0 0x008c #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1 0x008d #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2 0x008e #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0 0x008f #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1 0x0090 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2 0x0091 #define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT 0x0092 #define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT 0x0093 #define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT 0x0094 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x0095 #define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x0096 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN 0x1000 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0 0x1001 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1 0x1002 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2 0x1003 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3 0x1004 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4 0x1005 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT 0x1006 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN 0x1010 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0 0x1011 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1 0x1012 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2 0x1013 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT 0x1014 #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0 0x101b #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5 0x101d #define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1 0x101e #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1020 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1021 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1022 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1023 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1024 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1025 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1026 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1027 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1028 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1029 #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x102a #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x102b #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x102c #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x102d #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL 0x102e #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK 0x102f #define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1030 #define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1031 #define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL 0x1032 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1 0x1080 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK 0x1081 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0 0x1082 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1 0x1083 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0 0x1084 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1 0x1085 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1 0x1086 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0 0x1087 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1 0x1088 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2 0x1089 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3 0x108a #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4 0x108b #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5 0x108c #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6 0x108d #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x108e #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2 0x108f #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3 0x1090 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4 0x1091 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5 0x1092 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2 0x1093 #define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP 0x1094 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT 0x10a0 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x10a1 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x10a2 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 0x10a3 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 0x10a4 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 0x10a5 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 0x10a6 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 0x10a7 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5 0x10a8 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0 0x10bb #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x10c2 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x10c3 #define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2 0x10c4 #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS 0x10e0 #define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD 0x10e1 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS 0x10e2 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1 0x10e3 #define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2 0x10e4 #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC 0x10e5 #define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1 0x10e6 #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE 0x10e7 #define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL 0x10e8 #define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK 0x10e9 #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1 0x10ea #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2 0x10eb #define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3 0x10ec #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2 0x10ed #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3 0x10ee #define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4 0x10ef #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN 0x1100 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0 0x1101 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1 0x1102 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2 0x1103 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3 0x1104 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4 0x1105 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT 0x1106 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0 0x1107 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1 0x1108 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2 0x1109 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3 0x110a #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4 0x110b #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5 0x110c #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0 0x110d #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1 0x110e #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN 0x1110 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0 0x1111 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1 0x1112 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2 0x1113 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT 0x1114 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0 0x1115 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1 0x1116 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1117 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1118 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1119 #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x111a #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0 0x111b #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6 0x111c #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5 0x111d #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1 0x111e #define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA 0x111f #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1120 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1121 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1122 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1123 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1124 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1125 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1126 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1127 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1128 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1129 #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x112a #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x112b #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x112c #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x112d #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL 0x112e #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK 0x112f #define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1130 #define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1131 #define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL 0x1132 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1140 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1141 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1142 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1143 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1145 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1146 #define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1147 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1148 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1149 #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x114b #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x114c #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x114d #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x114e #define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x114f #define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1150 #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL 0x1151 #define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR 0x1152 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0 0x1153 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1 0x1154 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2 0x1155 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3 0x1156 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4 0x1157 #define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT 0x1158 #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ 0x1159 #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0 0x115a #define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1 0x115b #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1160 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1161 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1162 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1163 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1164 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1165 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1166 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1167 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1168 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1169 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x116a #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS 0x116b #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS 0x116c #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS 0x116d #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x116e #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x116f #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1170 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1171 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1172 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1173 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1174 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1175 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1176 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1177 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1178 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1179 #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET 0x117a #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x117b #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x117c #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x117d #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x117e #define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA 0x117f #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1 0x1180 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK 0x1181 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0 0x1182 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1 0x1183 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0 0x1184 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1 0x1185 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1 0x1186 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0 0x1187 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1 0x1188 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2 0x1189 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3 0x118a #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4 0x118b #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5 0x118c #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6 0x118d #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x118e #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2 0x118f #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3 0x1190 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4 0x1191 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5 0x1192 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2 0x1193 #define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP 0x1194 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL 0x1195 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL 0x1196 #define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1197 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT 0x11a0 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x11a1 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x11a2 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0 0x11a3 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1 0x11a4 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2 0x11a5 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3 0x11a6 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4 0x11a7 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5 0x11a8 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT 0x11a9 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT 0x11aa #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0 0x11ab #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1 0x11ac #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2 0x11ad #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL 0x11ae #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL 0x11af #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD 0x11b0 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL 0x11b1 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA 0x11b2 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE 0x11b3 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE 0x11b4 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL 0x11b5 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x11b6 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x11b7 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x11b8 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x11b9 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x11ba #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0 0x11bb #define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1 0x11bc #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x11bd #define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x11be #define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT 0x11bf #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1 0x11c0 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2 0x11c1 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x11c2 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x11c3 #define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2 0x11c4 #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS 0x11e0 #define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD 0x11e1 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS 0x11e2 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1 0x11e3 #define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2 0x11e4 #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC 0x11e5 #define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1 0x11e6 #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE 0x11e7 #define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL 0x11e8 #define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK 0x11e9 #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1 0x11ea #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2 0x11eb #define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3 0x11ec #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2 0x11ed #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3 0x11ee #define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4 0x11ef #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1 0x11f0 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2 0x11f1 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES 0x11f2 #define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL 0x11f3 #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1 0x11f4 #define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2 0x11f5 #define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ 0x11f6 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1 0x11f7 #define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2 0x11f8 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF 0x11f9 #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1 0x11fa #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2 0x11fb #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3 0x11fc #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4 0x11fd #define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC 0x11fe #define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1 0x11ff #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN 0x1200 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0 0x1201 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1 0x1202 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2 0x1203 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3 0x1204 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4 0x1205 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT 0x1206 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0 0x1207 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1 0x1208 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2 0x1209 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3 0x120a #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4 0x120b #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5 0x120c #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0 0x120d #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1 0x120e #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN 0x1210 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0 0x1211 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1 0x1212 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2 0x1213 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT 0x1214 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0 0x1215 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1 0x1216 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0 0x1217 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1 0x1218 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x1219 #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x121a #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0 0x121b #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6 0x121c #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5 0x121d #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1 0x121e #define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA 0x121f #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1220 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1221 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1222 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1223 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1224 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1225 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1226 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1227 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1228 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1229 #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x122a #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x122b #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x122c #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x122d #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL 0x122e #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK 0x122f #define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1230 #define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1231 #define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL 0x1232 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0 0x1240 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x1241 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1 0x1242 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2 0x1243 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x1245 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x1246 #define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x1247 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x1248 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x1249 #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x124b #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x124c #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x124d #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x124e #define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x124f #define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x1250 #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL 0x1251 #define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR 0x1252 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0 0x1253 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1 0x1254 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2 0x1255 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3 0x1256 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4 0x1257 #define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT 0x1258 #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ 0x1259 #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0 0x125a #define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1 0x125b #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0 0x1260 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1 0x1261 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2 0x1262 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3 0x1263 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4 0x1264 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5 0x1265 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6 0x1266 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7 0x1267 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8 0x1268 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9 0x1269 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x126a #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS 0x126b #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS 0x126c #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS 0x126d #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x126e #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x126f #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x1270 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x1271 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x1272 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x1273 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x1274 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x1275 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x1276 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x1277 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x1278 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x1279 #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET 0x127a #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x127b #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x127c #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x127d #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x127e #define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA 0x127f #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1 0x1280 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK 0x1281 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0 0x1282 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1 0x1283 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0 0x1284 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1 0x1285 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1 0x1286 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0 0x1287 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1 0x1288 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2 0x1289 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3 0x128a #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4 0x128b #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5 0x128c #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6 0x128d #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x128e #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2 0x128f #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3 0x1290 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4 0x1291 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5 0x1292 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2 0x1293 #define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP 0x1294 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL 0x1295 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL 0x1296 #define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x1297 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT 0x12a0 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x12a1 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x12a2 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0 0x12a3 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1 0x12a4 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2 0x12a5 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3 0x12a6 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4 0x12a7 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5 0x12a8 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT 0x12a9 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT 0x12aa #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0 0x12ab #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1 0x12ac #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2 0x12ad #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL 0x12ae #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL 0x12af #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD 0x12b0 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL 0x12b1 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA 0x12b2 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE 0x12b3 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE 0x12b4 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL 0x12b5 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x12b6 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x12b7 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x12b8 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x12b9 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x12ba #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0 0x12bb #define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1 0x12bc #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x12bd #define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x12be #define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT 0x12bf #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1 0x12c0 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2 0x12c1 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x12c2 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x12c3 #define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2 0x12c4 #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS 0x12e0 #define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD 0x12e1 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS 0x12e2 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1 0x12e3 #define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2 0x12e4 #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC 0x12e5 #define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1 0x12e6 #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE 0x12e7 #define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL 0x12e8 #define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK 0x12e9 #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1 0x12ea #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2 0x12eb #define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3 0x12ec #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2 0x12ed #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3 0x12ee #define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4 0x12ef #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1 0x12f0 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2 0x12f1 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES 0x12f2 #define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL 0x12f3 #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1 0x12f4 #define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2 0x12f5 #define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ 0x12f6 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1 0x12f7 #define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2 0x12f8 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF 0x12f9 #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1 0x12fa #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2 0x12fb #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3 0x12fc #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4 0x12fd #define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC 0x12fe #define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1 0x12ff #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN 0x1300 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0 0x1301 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1 0x1302 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2 0x1303 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3 0x1304 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4 0x1305 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT 0x1306 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN 0x1310 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0 0x1311 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1 0x1312 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2 0x1313 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT 0x1314 #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0 0x131b #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5 0x131d #define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1 0x131e #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0 0x1320 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x1321 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1 0x1322 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2 0x1323 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x1324 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x1325 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x1326 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x1327 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x1328 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x1329 #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x132a #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x132b #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x132c #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x132d #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL 0x132e #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK 0x132f #define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x1330 #define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0 0x1331 #define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL 0x1332 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1 0x1380 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK 0x1381 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0 0x1382 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1 0x1383 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0 0x1384 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1 0x1385 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1 0x1386 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0 0x1387 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1 0x1388 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2 0x1389 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3 0x138a #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4 0x138b #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5 0x138c #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6 0x138d #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x138e #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2 0x138f #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3 0x1390 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4 0x1391 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5 0x1392 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2 0x1393 #define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP 0x1394 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT 0x13a0 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x13a1 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x13a2 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0 0x13a3 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1 0x13a4 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2 0x13a5 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3 0x13a6 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4 0x13a7 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5 0x13a8 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0 0x13bb #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x13c2 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x13c3 #define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2 0x13c4 #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS 0x13e0 #define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD 0x13e1 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS 0x13e2 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1 0x13e3 #define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2 0x13e4 #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC 0x13e5 #define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1 0x13e6 #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE 0x13e7 #define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL 0x13e8 #define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK 0x13e9 #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1 0x13ea #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2 0x13eb #define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3 0x13ec #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2 0x13ed #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3 0x13ee #define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4 0x13ef #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL 0x2000 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN 0x2001 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN 0x2002 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0 0x2003 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN 0x2004 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN 0x2005 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0 0x2006 #define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND 0x2007 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1 0x2008 #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1 0x2009 #define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1 0x200a #define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL 0x200b #define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE 0x200c #define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE 0x200d #define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA 0x200e #define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD 0x200f #define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE 0x2010 #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1 0x2011 #define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2 0x2012 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0 0x2020 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0 0x2021 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0 0x2022 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1 0x2023 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1 0x2024 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1 0x2025 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2 0x2026 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2 0x2027 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2 0x2028 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3 0x2029 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3 0x202a #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3 0x202b #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4 0x202c #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4 0x202d #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4 0x202e #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5 0x202f #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5 0x2030 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5 0x2031 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6 0x2032 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6 0x2033 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6 0x2034 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7 0x2035 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7 0x2036 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7 0x2037 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG 0x2038 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN 0x2039 #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT 0x203a #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN 0x203b #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS 0x203c #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN 0x203d #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT 0x203e #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD 0x203f #define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1 0x2040 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN 0x3000 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN 0x3002 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT 0x3003 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT 0x3004 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN 0x3005 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 0x3006 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 0x3007 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3 0x3008 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN 0x3009 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 0x300a #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 0x300b #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 0x300c #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 0x300d #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT 0x300f #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK 0x3010 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM 0x3011 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR 0x3012 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR 0x3013 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR 0x3014 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER 0x3015 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1 0x3016 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2 0x3017 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN 0x3018 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3019 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x301a #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x301b #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 0x301c #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x301d #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x301e #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL 0x301f #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL 0x3020 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON 0x3021 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON 0x3022 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL 0x3023 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT 0x3024 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL 0x3025 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL 0x3026 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL 0x3027 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL 0x3028 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL 0x3029 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT 0x302a #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT 0x302b #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP 0x302c #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE 0x302d #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET 0x302e #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP 0x302f #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT 0x3030 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL 0x3031 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS 0x3032 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3033 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT 0x3034 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3035 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3036 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3037 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS 0x3038 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK 0x3039 #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS 0x303a #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS 0x303b #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA 0x303c #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG 0x303d #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS 0x303e #define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET 0x303f #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ 0x3040 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ 0x3041 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ 0x3042 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ 0x3043 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3044 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3045 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3046 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3047 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3048 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3049 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x304a #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x304b #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x304c #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK 0x304d #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2 0x304e #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x304f #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3050 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3051 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3052 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3053 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3054 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3055 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3056 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3057 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ 0x3058 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ 0x3059 #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x305a #define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x305b #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN 0x3060 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT 0x3061 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN 0x3062 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN 0x3063 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT 0x3064 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN 0x3065 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT 0x3066 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN 0x3067 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL 0x3068 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1 0x3069 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN 0x306a #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT 0x306b #define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x306c #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL 0x3080 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL 0x3081 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3082 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA 0x3083 #define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA 0x3084 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL 0x30a0 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL 0x30a1 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x30a2 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x30a3 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS 0x30a4 #define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA 0x30a5 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN 0x30c0 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN 0x30c1 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x30c2 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP 0x30c3 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x30c4 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x30c5 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x30c6 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2 0x30c7 #define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2 0x30c8 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN 0x3100 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1 0x3101 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN 0x3102 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT 0x3103 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT 0x3104 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN 0x3105 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1 0x3106 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2 0x3107 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3 0x3108 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN 0x3109 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1 0x310a #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2 0x310b #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3 0x310c #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4 0x310d #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT 0x310f #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK 0x3110 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM 0x3111 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR 0x3112 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR 0x3113 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR 0x3114 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER 0x3115 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1 0x3116 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2 0x3117 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN 0x3118 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3119 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x311a #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x311b #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1 0x311c #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x311d #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x311e #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL 0x311f #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL 0x3120 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON 0x3121 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON 0x3122 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL 0x3123 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT 0x3124 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL 0x3125 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL 0x3126 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL 0x3127 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL 0x3128 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL 0x3129 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT 0x312a #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT 0x312b #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP 0x312c #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE 0x312d #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET 0x312e #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP 0x312f #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT 0x3130 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL 0x3131 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS 0x3132 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3133 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT 0x3134 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3135 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3136 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3137 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS 0x3138 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK 0x3139 #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS 0x313a #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS 0x313b #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA 0x313c #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG 0x313d #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS 0x313e #define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET 0x313f #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ 0x3140 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ 0x3141 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ 0x3142 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ 0x3143 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3144 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3145 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3146 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3147 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3148 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3149 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x314a #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x314b #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x314c #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK 0x314d #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2 0x314e #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x314f #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3150 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3151 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3152 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3153 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3154 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3155 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3156 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3157 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ 0x3158 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ 0x3159 #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x315a #define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x315b #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN 0x3160 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT 0x3161 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN 0x3162 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN 0x3163 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT 0x3164 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN 0x3165 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT 0x3166 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN 0x3167 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL 0x3168 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1 0x3169 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN 0x316a #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT 0x316b #define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x316c #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL 0x3180 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL 0x3181 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3182 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA 0x3183 #define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA 0x3184 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL 0x31a0 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL 0x31a1 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x31a2 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x31a3 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS 0x31a4 #define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA 0x31a5 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN 0x31c0 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN 0x31c1 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x31c2 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP 0x31c3 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x31c4 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x31c5 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x31c6 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2 0x31c7 #define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2 0x31c8 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN 0x3200 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1 0x3201 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN 0x3202 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT 0x3203 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT 0x3204 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN 0x3205 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1 0x3206 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2 0x3207 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3 0x3208 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN 0x3209 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1 0x320a #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2 0x320b #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3 0x320c #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4 0x320d #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT 0x320f #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK 0x3210 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM 0x3211 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR 0x3212 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR 0x3213 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR 0x3214 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER 0x3215 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1 0x3216 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2 0x3217 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN 0x3218 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3219 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x321a #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x321b #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1 0x321c #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x321d #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x321e #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL 0x321f #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL 0x3220 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON 0x3221 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON 0x3222 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL 0x3223 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT 0x3224 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL 0x3225 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL 0x3226 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL 0x3227 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL 0x3228 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL 0x3229 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT 0x322a #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT 0x322b #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP 0x322c #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE 0x322d #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET 0x322e #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP 0x322f #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT 0x3230 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL 0x3231 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS 0x3232 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3233 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT 0x3234 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3235 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3236 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3237 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS 0x3238 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK 0x3239 #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS 0x323a #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS 0x323b #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA 0x323c #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG 0x323d #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS 0x323e #define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET 0x323f #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ 0x3240 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ 0x3241 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ 0x3242 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ 0x3243 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3244 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3245 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3246 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3247 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3248 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3249 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x324a #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x324b #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x324c #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK 0x324d #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2 0x324e #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x324f #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3250 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3251 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3252 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3253 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3254 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3255 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3256 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3257 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ 0x3258 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ 0x3259 #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x325a #define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x325b #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN 0x3260 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT 0x3261 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN 0x3262 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN 0x3263 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT 0x3264 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN 0x3265 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT 0x3266 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN 0x3267 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL 0x3268 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1 0x3269 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN 0x326a #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT 0x326b #define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x326c #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL 0x3280 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL 0x3281 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3282 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA 0x3283 #define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA 0x3284 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL 0x32a0 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL 0x32a1 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x32a2 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x32a3 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS 0x32a4 #define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA 0x32a5 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN 0x32c0 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN 0x32c1 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x32c2 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP 0x32c3 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x32c4 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x32c5 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x32c6 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2 0x32c7 #define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2 0x32c8 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN 0x3300 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1 0x3301 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN 0x3302 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT 0x3303 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT 0x3304 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN 0x3305 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1 0x3306 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2 0x3307 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3 0x3308 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN 0x3309 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1 0x330a #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2 0x330b #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3 0x330c #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4 0x330d #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT 0x330f #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK 0x3310 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM 0x3311 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR 0x3312 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR 0x3313 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR 0x3314 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER 0x3315 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1 0x3316 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2 0x3317 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN 0x3318 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0x3319 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0x331a #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0x331b #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1 0x331c #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0x331d #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0x331e #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL 0x331f #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL 0x3320 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON 0x3321 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON 0x3322 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL 0x3323 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT 0x3324 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL 0x3325 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL 0x3326 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL 0x3327 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL 0x3328 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL 0x3329 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT 0x332a #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT 0x332b #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP 0x332c #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE 0x332d #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET 0x332e #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP 0x332f #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT 0x3330 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL 0x3331 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS 0x3332 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0x3333 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT 0x3334 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL 0x3335 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0x3336 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL 0x3337 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS 0x3338 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK 0x3339 #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS 0x333a #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS 0x333b #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA 0x333c #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG 0x333d #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS 0x333e #define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET 0x333f #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ 0x3340 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ 0x3341 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ 0x3342 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ 0x3343 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ 0x3344 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0x3345 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0x3346 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0x3347 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0x3348 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0x3349 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0x334a #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0x334b #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0x334c #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK 0x334d #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2 0x334e #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0x334f #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0x3350 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0x3351 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0x3352 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0x3353 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0x3354 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0x3355 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0x3356 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0x3357 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ 0x3358 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ 0x3359 #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0x335a #define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0x335b #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN 0x3360 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT 0x3361 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN 0x3362 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN 0x3363 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT 0x3364 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN 0x3365 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT 0x3366 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN 0x3367 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL 0x3368 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1 0x3369 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN 0x336a #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT 0x336b #define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0x336c #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL 0x3380 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL 0x3381 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS 0x3382 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA 0x3383 #define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA 0x3384 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL 0x33a0 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL 0x33a1 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0x33a2 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS 0x33a3 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS 0x33a4 #define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA 0x33a5 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN 0x33c0 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN 0x33c1 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0x33c2 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP 0x33c3 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0x33c4 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0x33c5 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0x33c6 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2 0x33c7 #define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2 0x33c8 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST 0x4000 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST 0x4001 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ 0x4002 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM 0x4003 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4004 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4005 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4006 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL 0x4007 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL 0x4008 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN 0x4009 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP 0x400a #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x400b #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x400c #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x400d #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x400e #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x400f #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4010 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4011 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4012 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST 0x4013 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE 0x4014 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE 0x4015 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE 0x4016 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT 0x4017 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA 0x4018 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE 0x4019 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1 0x401a #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE 0x401b #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS 0x401c #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2 0x401d #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3 0x401e #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4 0x401f #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5 0x4020 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN 0x4021 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD 0x4022 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS 0x4023 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0 0x4024 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1 0x4025 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2 0x4026 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3 0x4027 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4 0x4028 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5 0x4029 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6 0x402a #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7 0x402b #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE 0x402c #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2 0x402d #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS 0x402e #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN 0x402f #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL 0x4030 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL 0x4031 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS 0x4032 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1 0x4033 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2 0x4034 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3 0x4035 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL 0x4036 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE 0x4037 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE 0x4038 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN 0x4039 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE 0x403a #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE 0x403b #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE 0x403c #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0 0x403d #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0 0x403e #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0 0x403f #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0 0x4040 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1 0x4041 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1 0x4042 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1 0x4043 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1 0x4044 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR 0x4045 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA 0x4046 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT 0x4047 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL 0x4048 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD 0x4049 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN 0x404a #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG 0x404b #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG 0x404c #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG 0x404d #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN 0x404e #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN 0x404f #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG 0x4050 #define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG 0x4051 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST 0x4100 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST 0x4101 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ 0x4102 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM 0x4103 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4104 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4105 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4106 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL 0x4107 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL 0x4108 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN 0x4109 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP 0x410a #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x410b #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x410c #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x410d #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x410e #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x410f #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4110 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4111 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4112 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST 0x4113 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE 0x4114 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE 0x4115 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE 0x4116 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT 0x4117 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA 0x4118 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE 0x4119 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1 0x411a #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE 0x411b #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS 0x411c #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2 0x411d #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3 0x411e #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4 0x411f #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5 0x4120 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN 0x4121 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD 0x4122 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS 0x4123 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0 0x4124 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1 0x4125 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2 0x4126 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3 0x4127 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4 0x4128 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5 0x4129 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6 0x412a #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7 0x412b #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE 0x412c #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2 0x412d #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS 0x412e #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN 0x412f #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL 0x4130 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL 0x4131 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS 0x4132 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1 0x4133 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2 0x4134 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3 0x4135 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL 0x4136 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE 0x4137 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE 0x4138 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN 0x4139 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE 0x413a #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE 0x413b #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE 0x413c #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0 0x413d #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0 0x413e #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0 0x413f #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0 0x4140 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1 0x4141 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1 0x4142 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1 0x4143 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1 0x4144 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR 0x4145 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA 0x4146 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT 0x4147 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL 0x4148 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD 0x4149 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN 0x414a #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG 0x414b #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG 0x414c #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG 0x414d #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN 0x414e #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN 0x414f #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG 0x4150 #define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG 0x4151 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST 0x4200 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST 0x4201 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ 0x4202 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM 0x4203 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4204 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4205 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4206 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL 0x4207 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL 0x4208 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN 0x4209 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP 0x420a #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x420b #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x420c #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x420d #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x420e #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x420f #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4210 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4211 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4212 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST 0x4213 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE 0x4214 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE 0x4215 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE 0x4216 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT 0x4217 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA 0x4218 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE 0x4219 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1 0x421a #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE 0x421b #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS 0x421c #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2 0x421d #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3 0x421e #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4 0x421f #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5 0x4220 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN 0x4221 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD 0x4222 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS 0x4223 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0 0x4224 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1 0x4225 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2 0x4226 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3 0x4227 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4 0x4228 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5 0x4229 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6 0x422a #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7 0x422b #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE 0x422c #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2 0x422d #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS 0x422e #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN 0x422f #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL 0x4230 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL 0x4231 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS 0x4232 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1 0x4233 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2 0x4234 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3 0x4235 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL 0x4236 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE 0x4237 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE 0x4238 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN 0x4239 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE 0x423a #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE 0x423b #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE 0x423c #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0 0x423d #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0 0x423e #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0 0x423f #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0 0x4240 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1 0x4241 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1 0x4242 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1 0x4243 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1 0x4244 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR 0x4245 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA 0x4246 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT 0x4247 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL 0x4248 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD 0x4249 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN 0x424a #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG 0x424b #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG 0x424c #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG 0x424d #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN 0x424e #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN 0x424f #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG 0x4250 #define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG 0x4251 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST 0x4300 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST 0x4301 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ 0x4302 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM 0x4303 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x4304 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x4305 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST 0x4306 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL 0x4307 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL 0x4308 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN 0x4309 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP 0x430a #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x430b #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x430c #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x430d #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x430e #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x430f #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x4310 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x4311 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST 0x4312 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST 0x4313 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE 0x4314 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE 0x4315 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE 0x4316 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT 0x4317 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA 0x4318 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE 0x4319 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1 0x431a #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE 0x431b #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS 0x431c #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2 0x431d #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3 0x431e #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4 0x431f #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5 0x4320 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN 0x4321 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD 0x4322 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS 0x4323 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0 0x4324 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1 0x4325 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2 0x4326 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3 0x4327 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4 0x4328 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5 0x4329 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6 0x432a #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7 0x432b #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE 0x432c #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2 0x432d #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS 0x432e #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN 0x432f #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL 0x4330 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL 0x4331 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS 0x4332 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1 0x4333 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2 0x4334 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3 0x4335 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL 0x4336 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE 0x4337 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE 0x4338 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN 0x4339 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE 0x433a #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE 0x433b #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE 0x433c #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0 0x433d #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0 0x433e #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0 0x433f #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0 0x4340 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1 0x4341 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1 0x4342 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1 0x4343 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1 0x4344 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR 0x4345 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA 0x4346 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT 0x4347 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL 0x4348 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD 0x4349 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN 0x434a #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG 0x434b #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG 0x434c #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG 0x434d #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN 0x434e #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN 0x434f #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG 0x4350 #define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG 0x4351 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST 0x7000 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST 0x7001 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ 0x7002 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM 0x7003 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST 0x7004 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST 0x7005 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST 0x7006 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL 0x7007 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL 0x7008 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN 0x7009 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP 0x700a #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST 0x700b #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST 0x700c #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST 0x700d #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST 0x700e #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST 0x700f #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST 0x7010 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST 0x7011 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST 0x7012 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST 0x7013 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE 0x7014 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE 0x7015 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE 0x7016 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT 0x7017 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA 0x7018 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE 0x7019 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1 0x701a #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE 0x701b #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS 0x701c #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2 0x701d #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3 0x701e #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4 0x701f #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5 0x7020 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN 0x7021 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD 0x7022 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS 0x7023 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0 0x7024 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1 0x7025 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2 0x7026 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3 0x7027 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4 0x7028 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5 0x7029 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6 0x702a #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7 0x702b #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE 0x702c #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2 0x702d #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS 0x702e #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN 0x702f #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL 0x7030 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL 0x7031 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS 0x7032 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1 0x7033 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2 0x7034 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3 0x7035 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL 0x7036 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE 0x7037 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE 0x7038 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN 0x7039 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE 0x703a #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE 0x703b #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE 0x703c #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0 0x703d #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0 0x703e #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0 0x703f #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0 0x7040 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1 0x7041 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1 0x7042 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1 0x7043 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1 0x7044 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR 0x7045 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA 0x7046 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT 0x7047 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL 0x7048 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD 0x7049 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN 0x704a #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG 0x704b #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG 0x704c #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG 0x704d #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN 0x704e #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN 0x704f #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG 0x7050 #define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG 0x7051 #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO 0x8000 #define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI 0x8001 #define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN 0x8002 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN 0x8003 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x8004 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN 0x8005 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x8006 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0 0x8007 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1 0x8008 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2 0x8009 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1 0x800a #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2 0x800b #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1 0x800c #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2 0x800d #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3 0x800e #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4 0x800f #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5 0x8010 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN 0x8011 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN 0x8012 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0 0x8013 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1 0x8014 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2 0x8015 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1 0x8016 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2 0x8017 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1 0x8018 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2 0x8019 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3 0x801a #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4 0x801b #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5 0x801c #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN 0x801d #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN 0x801e #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN 0x801f #define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN 0x8020 #define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT 0x8021 #define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN 0x8022 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0 0x8024 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1 0x8025 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2 0x8026 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3 0x8027 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4 0x8028 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5 0x8029 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6 0x802a #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0 0x802b #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1 0x802c #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2 0x802d #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3 0x802e #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4 0x802f #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5 0x8030 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6 0x8031 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN 0x8032 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN 0x8033 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN 0x8034 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN 0x8035 #define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN 0x8036 #define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN 0x8037 #define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN 0x8038 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN 0x8039 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN 0x803a #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN 0x803b #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN 0x803c #define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL 0x8040 #define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL 0x8041 #define ixDPCSSYS_CR4_SUPX_ANA_BG1 0x8042 #define ixDPCSSYS_CR4_SUPX_ANA_BG2 0x8043 #define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS 0x8044 #define ixDPCSSYS_CR4_SUPX_ANA_BG3 0x8045 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1 0x8046 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2 0x8047 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD 0x8048 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1 0x8049 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2 0x804a #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3 0x804b #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1 0x804c #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2 0x804d #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3 0x804e #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4 0x804f #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5 0x8050 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1 0x8051 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2 0x8052 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1 0x8053 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2 0x8054 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD 0x8055 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1 0x8056 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2 0x8057 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3 0x8058 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1 0x8059 #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2 0x805a #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3 0x805b #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4 0x805c #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5 0x805d #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1 0x805e #define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2 0x805f #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD 0x8061 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT 0x8062 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x8063 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8064 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS 0x8065 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8066 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8067 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL 0x8068 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8069 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE 0x806b #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD 0x806d #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT 0x806e #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE 0x806f #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK 0x8070 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS 0x8071 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE 0x8072 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2 0x8073 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL 0x8074 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT 0x8075 #define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE 0x8077 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0 0x8078 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1 0x8079 #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2 0x807a #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0 0x807b #define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD 0x807c #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG 0x8081 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT 0x8082 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL 0x8083 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL 0x8084 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL 0x8085 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT 0x8086 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT 0x8087 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT 0x8088 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0 0x8089 #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1 0x808a #define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE 0x808b #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0 0x808c #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1 0x808d #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2 0x808e #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0 0x808f #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1 0x8090 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2 0x8091 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT 0x8092 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT 0x8093 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT 0x8094 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT 0x8095 #define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT 0x8096 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN 0x9000 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0 0x9001 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1 0x9002 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2 0x9003 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3 0x9004 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4 0x9005 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT 0x9006 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0 0x9007 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1 0x9008 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2 0x9009 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3 0x900a #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4 0x900b #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5 0x900c #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0 0x900d #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1 0x900e #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0 0x900f #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN 0x9010 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0 0x9011 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1 0x9012 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2 0x9013 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT 0x9014 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0 0x9015 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1 0x9016 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0 0x9017 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1 0x9018 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 0x9019 #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 0x901a #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0 0x901b #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6 0x901c #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5 0x901d #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1 0x901e #define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA 0x901f #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0 0x9020 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S 0x9021 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1 0x9022 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2 0x9023 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 0x9024 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 0x9025 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 0x9026 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 0x9027 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 0x9028 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 0x9029 #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR 0x902a #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA 0x902b #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL 0x902c #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE 0x902d #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL 0x902e #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK 0x902f #define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR 0x9030 #define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0 0x9031 #define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL 0x9032 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0 0x9040 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S 0x9041 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1 0x9042 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2 0x9043 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 0x9045 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 0x9046 #define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 0x9047 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 0x9048 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 0x9049 #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x904a #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 0x904b #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 0x904c #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0 0x904d #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1 0x904e #define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2 0x904f #define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK 0x9050 #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL 0x9051 #define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR 0x9052 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0 0x9053 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1 0x9054 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2 0x9055 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3 0x9056 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4 0x9057 #define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT 0x9058 #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ 0x9059 #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0 0x905a #define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1 0x905b #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0 0x9060 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1 0x9061 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2 0x9062 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3 0x9063 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4 0x9064 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5 0x9065 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6 0x9066 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7 0x9067 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8 0x9068 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9 0x9069 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG 0x906a #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS 0x906b #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS 0x906c #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS 0x906d #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS 0x906e #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS 0x906f #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS 0x9070 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS 0x9071 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS 0x9072 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST 0x9073 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST 0x9074 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN 0x9075 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD 0x9076 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST 0x9077 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST 0x9078 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL 0x9079 #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET 0x907a #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1 0x907b #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2 0x907c #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3 0x907d #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR 0x907e #define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA 0x907f #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1 0x9080 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK 0x9081 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0 0x9082 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1 0x9083 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0 0x9084 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1 0x9085 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1 0x9086 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0 0x9087 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1 0x9088 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2 0x9089 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3 0x908a #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4 0x908b #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5 0x908c #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6 0x908d #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL 0x908e #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2 0x908f #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3 0x9090 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4 0x9091 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5 0x9092 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2 0x9093 #define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP 0x9094 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL 0x9095 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL 0x9096 #define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT 0x9097 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT 0x90a0 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT 0x90a1 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT 0x90a2 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0 0x90a3 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1 0x90a4 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2 0x90a5 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3 0x90a6 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4 0x90a7 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5 0x90a8 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT 0x90a9 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT 0x90aa #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0 0x90ab #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1 0x90ac #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2 0x90ad #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL 0x90ae #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL 0x90af #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD 0x90b0 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL 0x90b1 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA 0x90b2 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE 0x90b3 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE 0x90b4 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL 0x90b5 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST 0x90b6 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN 0x90b7 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN 0x90b8 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE 0x90b9 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK 0x90ba #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0 0x90bb #define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1 0x90bc #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT 0x90bd #define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT 0x90be #define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT 0x90bf #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1 0x90c0 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2 0x90c1 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT 0x90c2 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2 0x90c3 #define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2 0x90c4 #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS 0x90e0 #define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD 0x90e1 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS 0x90e2 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1 0x90e3 #define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2 0x90e4 #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC 0x90e5 #define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1 0x90e6 #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE 0x90e7 #define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL 0x90e8 #define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK 0x90e9 #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1 0x90ea #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2 0x90eb #define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3 0x90ec #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2 0x90ed #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3 0x90ee #define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4 0x90ef #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1 0x90f0 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2 0x90f1 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES 0x90f2 #define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL 0x90f3 #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1 0x90f4 #define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2 0x90f5 #define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ 0x90f6 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1 0x90f7 #define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2 0x90f8 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF 0x90f9 #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1 0x90fa #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2 0x90fb #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3 0x90fc #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4 0x90fd #define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC 0x90fe #define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1 0x90ff #define ixDPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0 0xa000 #define ixDPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0 0xc000 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN 0xe000 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1 0xe001 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN 0xe002 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT 0xe003 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT 0xe004 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN 0xe005 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1 0xe006 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2 0xe007 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3 0xe008 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN 0xe009 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1 0xe00a #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2 0xe00b #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3 0xe00c #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4 0xe00d #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT 0xe00e #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT 0xe00f #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK 0xe010 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM 0xe011 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR 0xe012 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR 0xe013 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR 0xe014 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER 0xe015 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1 0xe016 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2 0xe017 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN 0xe018 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN 0xe019 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN 0xe01a #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN 0xe01b #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1 0xe01c #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1 0xe01d #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2 0xe01e #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL 0xe01f #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL 0xe020 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON 0xe021 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON 0xe022 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL 0xe023 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT 0xe024 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL 0xe025 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL 0xe026 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL 0xe027 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL 0xe028 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL 0xe029 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT 0xe02a #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT 0xe02b #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP 0xe02c #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE 0xe02d #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET 0xe02e #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP 0xe02f #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT 0xe030 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL 0xe031 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS 0xe032 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT 0xe033 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT 0xe034 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL 0xe035 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL 0xe036 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL 0xe037 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS 0xe038 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK 0xe039 #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS 0xe03a #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS 0xe03b #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA 0xe03c #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG 0xe03d #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS 0xe03e #define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET 0xe03f #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ 0xe040 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ 0xe041 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ 0xe042 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ 0xe043 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ 0xe044 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ 0xe045 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ 0xe046 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR 0xe047 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR 0xe048 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR 0xe049 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR 0xe04a #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR 0xe04b #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR 0xe04c #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK 0xe04d #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2 0xe04e #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ 0xe04f #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR 0xe050 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ 0xe051 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ 0xe052 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR 0xe053 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR 0xe054 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ 0xe055 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR 0xe056 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ 0xe057 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ 0xe058 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ 0xe059 #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR 0xe05a #define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR 0xe05b #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN 0xe060 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT 0xe061 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN 0xe062 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN 0xe063 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT 0xe064 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN 0xe065 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT 0xe066 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN 0xe067 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL 0xe068 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1 0xe069 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN 0xe06a #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT 0xe06b #define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT 0xe06c #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL 0xe080 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL 0xe081 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS 0xe082 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA 0xe083 #define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA 0xe084 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL 0xe0a0 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL 0xe0a1 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL 0xe0a2 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS 0xe0a3 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS 0xe0a4 #define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA 0xe0a5 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN 0xe0c0 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN 0xe0c1 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1 0xe0c2 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP 0xe0c3 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1 0xe0c4 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2 0xe0c5 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3 0xe0c6 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2 0xe0c7 #define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2 0xe0c8 //TODO: verify this still applies to DCN315 //[Note] Hack. RDPCSPIPE only has 2 instances. #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6 0x2d73 #define regRDPCSPIPE0_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6 0x2e4b #define regRDPCSPIPE1_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6 0x2d73 #define regRDPCSPIPE2_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6 0x2e4b #define regRDPCSPIPE3_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6 0x2d73 #define regRDPCSPIPE4_RDPCSPIPE_PHY_CNTL6_BASE_IDX 2 #endif