// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779f0-sysc.h>

/ {
	compatible = "renesas,r8a779f0";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a55_0: cpu@0 {
			compatible = "arm,cortex-a55";
			reg = <0>;
			device_type = "cpu";
			power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	extalr_clk: extalr {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	pmu_a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc: soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a779f0-wdt",
				     "renesas,rcar-gen4-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
			status = "disabled";
		};

		pfc: pinctrl@e6050000 {
			compatible = "renesas,pfc-r8a779f0";
			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
		};

		gpio0: gpio@e6050180 {
			compatible = "renesas,gpio-r8a779f0",
				     "renesas,rcar-gen4-gpio";
			reg = <0 0xe6050180 0 0x54>;
			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pfc 0 0 21>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@e6050980 {
			compatible = "renesas,gpio-r8a779f0",
				     "renesas,rcar-gen4-gpio";
			reg = <0 0xe6050980 0 0x54>;
			interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pfc 0 32 25>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@e6051180 {
			compatible = "renesas,gpio-r8a779f0",
				     "renesas,rcar-gen4-gpio";
			reg = <0 0xe6051180 0 0x54>;
			interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pfc 0 64 17>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@e6051980 {
			compatible = "renesas,gpio-r8a779f0",
				     "renesas,rcar-gen4-gpio";
			reg = <0 0xe6051980 0 0x54>;
			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pfc 0 96 19>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a779f0-cpg-mssr";
			reg = <0 0xe6150000 0 0x4000>;
			clocks = <&extal_clk>, <&extalr_clk>;
			clock-names = "extal", "extalr";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a779f0-rst";
			reg = <0 0xe6160000 0 0x4000>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a779f0-sysc";
			reg = <0 0xe6180000 0 0x4000>;
			#power-domain-cells = <1>;
		};

		i2c0: i2c@e6500000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe6500000 0 0x40>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 518>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 518>;
			dmas = <&dmac0 0x91>, <&dmac0 0x90>,
			       <&dmac1 0x91>, <&dmac1 0x90>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@e6508000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 519>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 519>;
			dmas = <&dmac0 0x93>, <&dmac0 0x92>,
			       <&dmac1 0x93>, <&dmac1 0x92>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@e6510000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe6510000 0 0x40>;
			interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 520>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 520>;
			dmas = <&dmac0 0x95>, <&dmac0 0x94>,
			       <&dmac1 0x95>, <&dmac1 0x94>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@e66d0000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe66d0000 0 0x40>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 521>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 521>;
			dmas = <&dmac0 0x97>, <&dmac0 0x96>,
			       <&dmac1 0x97>, <&dmac1 0x96>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@e66d8000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe66d8000 0 0x40>;
			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 522>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 522>;
			dmas = <&dmac0 0x99>, <&dmac0 0x98>,
			       <&dmac1 0x99>, <&dmac1 0x98>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@e66e0000 {
			compatible = "renesas,i2c-r8a779f0",
				     "renesas,rcar-gen4-i2c";
			reg = <0 0xe66e0000 0 0x40>;
			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
			       <&dmac1 0x9b>, <&dmac1 0x9a>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scif3: serial@e6c50000 {
			compatible = "renesas,scif-r8a779f0",
				     "renesas,rcar-gen4-scif", "renesas,scif";
			reg = <0 0xe6c50000 0 64>;
			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 704>,
				 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 704>;
			status = "disabled";
		};

		dmac0: dma-controller@e7350000 {
			compatible = "renesas,dmac-r8a779f0",
				     "renesas,rcar-gen4-dmac";
			reg = <0 0xe7350000 0 0x1000>,
			      <0 0xe7300000 0 0x10000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3", "ch4",
					  "ch5", "ch6", "ch7", "ch8", "ch9",
					  "ch10", "ch11", "ch12", "ch13",
					  "ch14", "ch15";
			clocks = <&cpg CPG_MOD 709>;
			clock-names = "fck";
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 709>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		dmac1: dma-controller@e7351000 {
			compatible = "renesas,dmac-r8a779f0",
				     "renesas,rcar-gen4-dmac";
			reg = <0 0xe7351000 0 0x1000>,
			      <0 0xe7310000 0 0x10000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3", "ch4",
					  "ch5", "ch6", "ch7", "ch8", "ch9",
					  "ch10", "ch11", "ch12", "ch13",
					  "ch14", "ch15";
			clocks = <&cpg CPG_MOD 710>;
			clock-names = "fck";
			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
			resets = <&cpg 710>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		gic: interrupt-controller@f1000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1000000 0 0x20000>,
			      <0x0 0xf1060000 0 0x110000>;
			interrupts = <GIC_PPI 9
				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
	};
};