// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019, Linaro Limited */ #include #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; clock-output-names = "xo_board"; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <421>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; core4 { cpu = <&CPU4>; }; core5 { cpu = <&CPU5>; }; core6 { cpu = <&CPU6>; }; core7 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <355>; exit-latency-us = <909>; min-residency-us = <3934>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <241>; exit-latency-us = <1461>; min-residency-us = <4488>; local-timer-stop; }; }; domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; }; }; }; cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; cpu0_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <800000 9600000>; }; cpu0_opp2: opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-peak-kBps = <800000 9600000>; }; cpu0_opp3: opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-peak-kBps = <800000 12902400>; }; cpu0_opp4: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <800000 12902400>; }; cpu0_opp5: opp-672000000 { opp-hz = /bits/ 64 <672000000>; opp-peak-kBps = <800000 15974400>; }; cpu0_opp6: opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-peak-kBps = <1804000 19660800>; }; cpu0_opp7: opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-peak-kBps = <1804000 19660800>; }; cpu0_opp8: opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <1804000 22732800>; }; cpu0_opp9: opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-peak-kBps = <1804000 22732800>; }; cpu0_opp10: opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-peak-kBps = <2188000 25804800>; }; cpu0_opp11: opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-peak-kBps = <2188000 31948800>; }; cpu0_opp12: opp-1305600000 { opp-hz = /bits/ 64 <1305600000>; opp-peak-kBps = <3072000 31948800>; }; cpu0_opp13: opp-1382400000 { opp-hz = /bits/ 64 <1382400000>; opp-peak-kBps = <3072000 31948800>; }; cpu0_opp14: opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; opp-peak-kBps = <3072000 31948800>; }; cpu0_opp15: opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; opp-peak-kBps = <3072000 40550400>; }; cpu0_opp16: opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; opp-peak-kBps = <3072000 40550400>; }; cpu0_opp17: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <3072000 43008000>; }; cpu0_opp18: opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; opp-peak-kBps = <3072000 43008000>; }; }; cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; cpu4_opp1: opp-710400000 { opp-hz = /bits/ 64 <710400000>; opp-peak-kBps = <1804000 15974400>; }; cpu4_opp2: opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <2188000 19660800>; }; cpu4_opp3: opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <2188000 22732800>; }; cpu4_opp4: opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <3072000 25804800>; }; cpu4_opp5: opp-1171200000 { opp-hz = /bits/ 64 <1171200000>; opp-peak-kBps = <3072000 31948800>; }; cpu4_opp6: opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-peak-kBps = <4068000 31948800>; }; cpu4_opp7: opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-peak-kBps = <4068000 31948800>; }; cpu4_opp8: opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <4068000 40550400>; }; cpu4_opp9: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <4068000 40550400>; }; cpu4_opp10: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <4068000 43008000>; }; cpu4_opp11: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <6220000 43008000>; }; cpu4_opp12: opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; opp-peak-kBps = <6220000 49152000>; }; cpu4_opp13: opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; opp-peak-kBps = <7216000 49152000>; }; cpu4_opp14: opp-2131200000 { opp-hz = /bits/ 64 <2131200000>; opp-peak-kBps = <8368000 49152000>; }; cpu4_opp15: opp-2227200000 { opp-hz = /bits/ 64 <2227200000>; opp-peak-kBps = <8368000 51609600>; }; cpu4_opp16: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; opp-peak-kBps = <8368000 51609600>; }; cpu4_opp17: opp-2419200000 { opp-hz = /bits/ 64 <2419200000>; opp-peak-kBps = <8368000 51609600>; }; }; cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; cpu7_opp1: opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <2188000 19660800>; }; cpu7_opp2: opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <2188000 22732800>; }; cpu7_opp3: opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <3072000 25804800>; }; cpu7_opp4: opp-1171200000 { opp-hz = /bits/ 64 <1171200000>; opp-peak-kBps = <3072000 31948800>; }; cpu7_opp5: opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-peak-kBps = <4068000 31948800>; }; cpu7_opp6: opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-peak-kBps = <4068000 31948800>; }; cpu7_opp7: opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-peak-kBps = <4068000 40550400>; }; cpu7_opp8: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <4068000 40550400>; }; cpu7_opp9: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-peak-kBps = <4068000 43008000>; }; cpu7_opp10: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <6220000 43008000>; }; cpu7_opp11: opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; opp-peak-kBps = <6220000 49152000>; }; cpu7_opp12: opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; opp-peak-kBps = <7216000 49152000>; }; cpu7_opp13: opp-2131200000 { opp-hz = /bits/ 64 <2131200000>; opp-peak-kBps = <8368000 49152000>; }; cpu7_opp14: opp-2227200000 { opp-hz = /bits/ 64 <2227200000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp15: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp16: opp-2419200000 { opp-hz = /bits/ 64 <2419200000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp17: opp-2534400000 { opp-hz = /bits/ 64 <2534400000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp18: opp-2649600000 { opp-hz = /bits/ 64 <2649600000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp19: opp-2745600000 { opp-hz = /bits/ 64 <2745600000>; opp-peak-kBps = <8368000 51609600>; }; cpu7_opp20: opp-2841600000 { opp-hz = /bits/ 64 <2841600000>; opp-peak-kBps = <8368000 51609600>; }; }; firmware { scm: scm { compatible = "qcom,scm-sm8150", "qcom,scm"; #reset-cells = <1>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; }; psci { compatible = "arm,psci-1.0"; method = "smc"; CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: memory@85700000 { reg = <0x0 0x85700000 0x0 0x600000>; no-map; }; xbl_mem: memory@85d00000 { reg = <0x0 0x85d00000 0x0 0x140000>; no-map; }; aop_mem: memory@85f00000 { reg = <0x0 0x85f00000 0x0 0x20000>; no-map; }; aop_cmd_db: memory@85f20000 { compatible = "qcom,cmd-db"; reg = <0x0 0x85f20000 0x0 0x20000>; no-map; }; smem_mem: memory@86000000 { reg = <0x0 0x86000000 0x0 0x200000>; no-map; }; tz_mem: memory@86200000 { reg = <0x0 0x86200000 0x0 0x3900000>; no-map; }; rmtfs_mem: memory@89b00000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x89b00000 0x0 0x200000>; no-map; qcom,client-id = <1>; qcom,vmid = <15>; }; camera_mem: memory@8b700000 { reg = <0x0 0x8b700000 0x0 0x500000>; no-map; }; wlan_mem: memory@8bc00000 { reg = <0x0 0x8bc00000 0x0 0x180000>; no-map; }; npu_mem: memory@8bd80000 { reg = <0x0 0x8bd80000 0x0 0x80000>; no-map; }; adsp_mem: memory@8be00000 { reg = <0x0 0x8be00000 0x0 0x1a00000>; no-map; }; mpss_mem: memory@8d800000 { reg = <0x0 0x8d800000 0x0 0x9600000>; no-map; }; venus_mem: memory@96e00000 { reg = <0x0 0x96e00000 0x0 0x500000>; no-map; }; slpi_mem: memory@97300000 { reg = <0x0 0x97300000 0x0 0x1400000>; no-map; }; ipa_fw_mem: memory@98700000 { reg = <0x0 0x98700000 0x0 0x10000>; no-map; }; ipa_gsi_mem: memory@98710000 { reg = <0x0 0x98710000 0x0 0x5000>; no-map; }; gpu_mem: memory@98715000 { reg = <0x0 0x98715000 0x0 0x2000>; no-map; }; spss_mem: memory@98800000 { reg = <0x0 0x98800000 0x0 0x100000>; no-map; }; cdsp_mem: memory@98900000 { reg = <0x0 0x98900000 0x0 0x1400000>; no-map; }; qseecom_mem: memory@9e400000 { reg = <0x0 0x9e400000 0x0 0x1400000>; no-map; }; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = ; mboxes = <&apss_shared 6>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-lpass { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; mboxes = <&apss_shared 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; mboxes = <&apss_shared 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-slpi { compatible = "qcom,smp2p"; qcom,smem = <481>, <430>; interrupts = ; mboxes = <&apss_shared 26>; qcom,local-pid = <0>; qcom,remote-pid = <3>; slpi_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; slpi_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sm8150"; reg = <0x0 0x00100000 0x0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clock-names = "bi_tcxo", "sleep_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; }; gpi_dma0: dma-controller@800000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00800000 0 0x60000>; interrupts = , , , , , , , , , , , , ; dma-channels = <13>; dma-channel-mask = <0xfa>; iommus = <&apps_smmu 0x00d6 0x0>; #dma-cells = <3>; status = "disabled"; }; ethernet: ethernet@20000 { compatible = "qcom,sm8150-ethqos"; reg = <0x0 0x00020000 0x0 0x10000>, <0x0 0x00036000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; clocks = <&gcc GCC_EMAC_AXI_CLK>, <&gcc GCC_EMAC_SLV_AHB_CLK>, <&gcc GCC_EMAC_PTP_CLK>, <&gcc GCC_EMAC_RGMII_CLK>; interrupts = , ; interrupt-names = "macirq", "eth_lpi"; power-domains = <&gcc EMAC_GDSC>; resets = <&gcc GCC_EMAC_BCR>; iommus = <&apps_smmu 0x3c0 0x0>; snps,tso; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; status = "disabled"; }; qfprom: efuse@784000 { compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; gpu_speed_bin: gpu_speed_bin@133 { reg = <0x133 0x1>; bits = <5 3>; }; }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus = <&apps_smmu 0xc3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c0: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi0: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi1: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi2: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi3: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi4: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi5: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c6: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi6: spi@898000 { compatible = "qcom,geni-spi"; reg = <0 0x00898000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c7: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi7: spi@89c000 { compatible = "qcom,geni-spi"; reg = <0 0x0089c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = , , , , , , , , , , , , ; dma-channels = <13>; dma-channel-mask = <0xfa>; iommus = <&apps_smmu 0x0616 0x0>; #dma-cells = <3>; status = "disabled"; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0x603 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart9_default>; pinctrl-names = "default"; interrupts = ; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi11: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart2: serial@a90000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c16: i2c@94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00094000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi16: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi16_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; gpi_dma2: dma-controller@c00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0 0x00c00000 0 0x60000>; interrupts = , , , , , , , , , , , , ; dma-channels = <13>; dma-channel-mask = <0xfa>; iommus = <&apps_smmu 0x07b6 0x0>; #dma-cells = <3>; status = "disabled"; }; qupv3_id_2: geniqup@cc0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00cc0000 0x0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x7a3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c17: i2c@c80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi17: spi@c80000 { compatible = "qcom,geni-spi"; reg = <0 0x00c80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi17_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c18: i2c@c84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi18: spi@c84000 { compatible = "qcom,geni-spi"; reg = <0 0x00c84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi18_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c19: i2c@c88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi19: spi@c88000 { compatible = "qcom,geni-spi"; reg = <0 0x00c88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi19_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c13: i2c@c8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi13: spi@c8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00c8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c14: i2c@c90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi14: spi@c90000 { compatible = "qcom,geni-spi"; reg = <0 0x00c90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c15: i2c@c94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi15: spi@c94000 { compatible = "qcom,geni-spi"; reg = <0 0x00c94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_default>; interrupts = ; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; config_noc: interconnect@1500000 { compatible = "qcom,sm8150-config-noc"; reg = <0 0x01500000 0 0x7400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm8150-system-noc"; reg = <0 0x01620000 0 0x19400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@163a000 { compatible = "qcom,sm8150-mc-virt"; reg = <0 0x0163a000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8150-aggre1-noc"; reg = <0 0x016e0000 0 0xd080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8150-aggre2-noc"; reg = <0 0x01700000 0 0x20000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; compute_noc: interconnect@1720000 { compatible = "qcom,sm8150-compute-noc"; reg = <0 0x01720000 0 0x7000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8150-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; dma@10a2000 { compatible = "qcom,sm8150-dcc", "qcom,dcc"; reg = <0x0 0x010a2000 0x0 0x1000>, <0x0 0x010ad000 0x0 0x3000>; }; pcie0: pci@1c00000 { compatible = "qcom,pcie-sm8150"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "tbu"; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_lane>; phy-names = "pciephy"; perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "disabled"; }; pcie0_phy: phy@1c06000 { compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; pcie0_lane: phy@1c06200 { reg = <0 0x01c06200 0 0x170>, /* tx */ <0 0x01c06400 0 0x200>, /* rx */ <0 0x01c06800 0 0x1f0>, /* pcs */ <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; #phy-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; }; }; pcie1: pci@1c08000 { compatible = "qcom,pcie-sm8150"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, <0 0x40100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "tbu"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, <0x100 &apps_smmu 0x1e01 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_lane>; phy-names = "pciephy"; perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "disabled"; }; pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen"; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; pcie1_lane: phy@1c0e200 { reg = <0 0x01c0e200 0 0x170>, /* tx0 */ <0 0x01c0e400 0 0x200>, /* rx0 */ <0 0x01c0ea00 0 0x1f0>, /* pcs */ <0 0x01c0e600 0 0x170>, /* tx1 */ <0 0x01c0e800 0 0x200>, /* rx1 */ <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; #phy-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x2500>, <0 0x01d90000 0 0x8000>; reg-names = "std", "ice"; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; iommus = <&apps_smmu 0x300 0>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk", "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, <0 0>, <37500000 300000000>, <0 0>, <0 0>, <0 0>, <0 0>, <0 300000000>; status = "disabled"; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,sm8150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; clock-names = "ref", "ref_aux"; clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; status = "disabled"; ufs_mem_phy_lanes: phy@1d87400 { reg = <0 0x01d87400 0 0x16c>, <0 0x01d87600 0 0x200>, <0 0x01d87c00 0 0x200>, <0 0x01d87800 0 0x16c>, <0 0x01d87a00 0 0x200>; #phy-cells = <0>; }; }; cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; num-channels = <8>; qcom,num-ees = <2>; iommus = <&apps_smmu 0x502 0x0641>, <&apps_smmu 0x504 0x0011>, <&apps_smmu 0x506 0x0011>, <&apps_smmu 0x508 0x0011>, <&apps_smmu 0x512 0x0000>; }; crypto: crypto@1dfa000 { compatible = "qcom,sm8150-qce", "qcom,qce"; reg = <0 0x01dfa000 0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x502 0x0641>, <&apps_smmu 0x504 0x0011>, <&apps_smmu 0x506 0x0011>, <&apps_smmu 0x508 0x0011>, <&apps_smmu 0x512 0x0000>; interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "memory"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; tcsr_regs_1: syscon@1f60000 { compatible = "qcom,sm8150-tcsr", "syscon"; reg = <0x0 0x01f60000 0x0 0x20000>; }; remoteproc_slpi: remoteproc@2400000 { compatible = "qcom,sm8150-slpi-pas"; reg = <0x0 0x02400000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SM8150_LCX>, <&rpmhpd SM8150_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; label = "dsps"; qcom,remote-pid = <3>; mboxes = <&apss_shared 24>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x05a1 0x0>; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x05a2 0x0>; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x05a3 0x0>; /* note: shared-cb = <4> in downstream */ }; }; }; }; gpu: gpu@2c00000 { compatible = "qcom,adreno-640.1", "qcom,adreno"; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; iommus = <&adreno_smmu 0 0x401>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; opp-supported-hw = <0x2>; }; opp-585000000 { opp-hz = /bits/ 64 <585000000>; opp-level = ; opp-supported-hw = <0x3>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-level = ; opp-supported-hw = <0x3>; }; opp-427000000 { opp-hz = /bits/ 64 <427000000>; opp-level = ; opp-supported-hw = <0x3>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; opp-level = ; opp-supported-hw = <0x3>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; opp-supported-hw = <0x3>; }; }; }; gmu: gmu@2c6a000 { compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; reg = <0 0x02c6a000 0 0x30000>, <0 0x0b290000 0 0x10000>, <0 0x0b490000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; operating-points-v2 = <&gmu_opp_table>; status = "disabled"; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = ; }; }; }; gpucc: clock-controller@2c90000 { compatible = "qcom,sm8150-gpucc"; reg = <0 0x02c90000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; adreno_smmu: iommu@2ca0000 { compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , , , , , , , , ; clocks = <&gpucc GPU_CC_AHB_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "ahb", "bus", "iface"; power-domains = <&gpucc GPU_CX_GDSC>; }; tlmm: pinctrl@3100000 { compatible = "qcom,sm8150-pinctrl"; reg = <0x0 0x03100000 0x0 0x300000>, <0x0 0x03500000 0x0 0x300000>, <0x0 0x03900000 0x0 0x300000>, <0x0 0x03D00000 0x0 0x300000>; reg-names = "west", "east", "north", "south"; interrupts = ; gpio-ranges = <&tlmm 0 0 176>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; drive-strength = <0x02>; bias-disable; }; qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; drive-strength = <6>; bias-disable; }; qup_i2c1_default: qup-i2c1-default-state { pins = "gpio114", "gpio115"; function = "qup1"; drive-strength = <2>; bias-disable; }; qup_spi1_default: qup-spi1-default-state { pins = "gpio114", "gpio115", "gpio116", "gpio117"; function = "qup1"; drive-strength = <6>; bias-disable; }; qup_i2c2_default: qup-i2c2-default-state { pins = "gpio126", "gpio127"; function = "qup2"; drive-strength = <2>; bias-disable; }; qup_spi2_default: qup-spi2-default-state { pins = "gpio126", "gpio127", "gpio128", "gpio129"; function = "qup2"; drive-strength = <6>; bias-disable; }; qup_i2c3_default: qup-i2c3-default-state { pins = "gpio144", "gpio145"; function = "qup3"; drive-strength = <2>; bias-disable; }; qup_spi3_default: qup-spi3-default-state { pins = "gpio144", "gpio145", "gpio146", "gpio147"; function = "qup3"; drive-strength = <6>; bias-disable; }; qup_i2c4_default: qup-i2c4-default-state { pins = "gpio51", "gpio52"; function = "qup4"; drive-strength = <2>; bias-disable; }; qup_spi4_default: qup-spi4-default-state { pins = "gpio51", "gpio52", "gpio53", "gpio54"; function = "qup4"; drive-strength = <6>; bias-disable; }; qup_i2c5_default: qup-i2c5-default-state { pins = "gpio121", "gpio122"; function = "qup5"; drive-strength = <2>; bias-disable; }; qup_spi5_default: qup-spi5-default-state { pins = "gpio119", "gpio120", "gpio121", "gpio122"; function = "qup5"; drive-strength = <6>; bias-disable; }; qup_i2c6_default: qup-i2c6-default-state { pins = "gpio6", "gpio7"; function = "qup6"; drive-strength = <2>; bias-disable; }; qup_spi6_default: qup-spi6_default-state { pins = "gpio4", "gpio5", "gpio6", "gpio7"; function = "qup6"; drive-strength = <6>; bias-disable; }; qup_i2c7_default: qup-i2c7-default-state { pins = "gpio98", "gpio99"; function = "qup7"; drive-strength = <2>; bias-disable; }; qup_spi7_default: qup-spi7_default-state { pins = "gpio98", "gpio99", "gpio100", "gpio101"; function = "qup7"; drive-strength = <6>; bias-disable; }; qup_i2c8_default: qup-i2c8-default-state { pins = "gpio88", "gpio89"; function = "qup8"; drive-strength = <2>; bias-disable; }; qup_spi8_default: qup-spi8-default-state { pins = "gpio88", "gpio89", "gpio90", "gpio91"; function = "qup8"; drive-strength = <6>; bias-disable; }; qup_i2c9_default: qup-i2c9-default-state { pins = "gpio39", "gpio40"; function = "qup9"; drive-strength = <2>; bias-disable; }; qup_spi9_default: qup-spi9-default-state { pins = "gpio39", "gpio40", "gpio41", "gpio42"; function = "qup9"; drive-strength = <6>; bias-disable; }; qup_uart9_default: qup-uart9-default-state { pins = "gpio41", "gpio42"; function = "qup9"; drive-strength = <2>; bias-disable; }; qup_i2c10_default: qup-i2c10-default-state { pins = "gpio9", "gpio10"; function = "qup10"; drive-strength = <2>; bias-disable; }; qup_spi10_default: qup-spi10-default-state { pins = "gpio9", "gpio10", "gpio11", "gpio12"; function = "qup10"; drive-strength = <6>; bias-disable; }; qup_i2c11_default: qup-i2c11-default-state { pins = "gpio94", "gpio95"; function = "qup11"; drive-strength = <2>; bias-disable; }; qup_spi11_default: qup-spi11-default-state { pins = "gpio92", "gpio93", "gpio94", "gpio95"; function = "qup11"; drive-strength = <6>; bias-disable; }; qup_i2c12_default: qup-i2c12-default-state { pins = "gpio83", "gpio84"; function = "qup12"; drive-strength = <2>; bias-disable; }; qup_spi12_default: qup-spi12-default-state { pins = "gpio83", "gpio84", "gpio85", "gpio86"; function = "qup12"; drive-strength = <6>; bias-disable; }; qup_i2c13_default: qup-i2c13-default-state { pins = "gpio43", "gpio44"; function = "qup13"; drive-strength = <2>; bias-disable; }; qup_spi13_default: qup-spi13-default-state { pins = "gpio43", "gpio44", "gpio45", "gpio46"; function = "qup13"; drive-strength = <6>; bias-disable; }; qup_i2c14_default: qup-i2c14-default-state { pins = "gpio47", "gpio48"; function = "qup14"; drive-strength = <2>; bias-disable; }; qup_spi14_default: qup-spi14-default-state { pins = "gpio47", "gpio48", "gpio49", "gpio50"; function = "qup14"; drive-strength = <6>; bias-disable; }; qup_i2c15_default: qup-i2c15-default-state { pins = "gpio27", "gpio28"; function = "qup15"; drive-strength = <2>; bias-disable; }; qup_spi15_default: qup-spi15-default-state { pins = "gpio27", "gpio28", "gpio29", "gpio30"; function = "qup15"; drive-strength = <6>; bias-disable; }; qup_i2c16_default: qup-i2c16-default-state { pins = "gpio86", "gpio85"; function = "qup16"; drive-strength = <2>; bias-disable; }; qup_spi16_default: qup-spi16-default-state { pins = "gpio83", "gpio84", "gpio85", "gpio86"; function = "qup16"; drive-strength = <6>; bias-disable; }; qup_i2c17_default: qup-i2c17-default-state { pins = "gpio55", "gpio56"; function = "qup17"; drive-strength = <2>; bias-disable; }; qup_spi17_default: qup-spi17-default-state { pins = "gpio55", "gpio56", "gpio57", "gpio58"; function = "qup17"; drive-strength = <6>; bias-disable; }; qup_i2c18_default: qup-i2c18-default-state { pins = "gpio23", "gpio24"; function = "qup18"; drive-strength = <2>; bias-disable; }; qup_spi18_default: qup-spi18-default-state { pins = "gpio23", "gpio24", "gpio25", "gpio26"; function = "qup18"; drive-strength = <6>; bias-disable; }; qup_i2c19_default: qup-i2c19-default-state { pins = "gpio57", "gpio58"; function = "qup19"; drive-strength = <2>; bias-disable; }; qup_spi19_default: qup-spi19-default-state { pins = "gpio55", "gpio56", "gpio57", "gpio58"; function = "qup19"; drive-strength = <6>; bias-disable; }; pcie0_default_state: pcie0-default-state { perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; clkreq-pins { pins = "gpio36"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; }; pcie1_default_state: pcie1-default-state { perst-pins { pins = "gpio102"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; clkreq-pins { pins = "gpio103"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; wake-pins { pins = "gpio104"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; }; }; remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8150-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SM8150_CX>, <&rpmhpd SM8150_MSS>; power-domain-names = "cx", "mss"; memory-region = <&mpss_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; label = "modem"; qcom,remote-pid = <1>; mboxes = <&apss_shared 12>; }; }; stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { stm_out: endpoint { remote-endpoint = <&funnel0_in7>; }; }; }; }; funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel0_out: endpoint { remote-endpoint = <&merge_funnel_in0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; funnel0_in7: endpoint { remote-endpoint = <&stm_out>; }; }; }; }; funnel@6042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06042000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel1_out: endpoint { remote-endpoint = <&merge_funnel_in1>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@4 { reg = <4>; funnel1_in4: endpoint { remote-endpoint = <&swao_replicator_out>; }; }; }; }; funnel@6043000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06043000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel2_out: endpoint { remote-endpoint = <&merge_funnel_in2>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@2 { reg = <2>; funnel2_in2: endpoint { remote-endpoint = <&apss_merge_funnel_out>; }; }; }; }; funnel@6045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06045000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { merge_funnel_out: endpoint { remote-endpoint = <&etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; merge_funnel_in0: endpoint { remote-endpoint = <&funnel0_out>; }; }; port@1 { reg = <1>; merge_funnel_in1: endpoint { remote-endpoint = <&funnel1_out>; }; }; port@2 { reg = <2>; merge_funnel_in2: endpoint { remote-endpoint = <&funnel2_out>; }; }; }; }; replicator@6046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06046000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; replicator_out0: endpoint { remote-endpoint = <&etr_in>; }; }; port@1 { reg = <1>; replicator_out1: endpoint { remote-endpoint = <&replicator1_in>; }; }; }; in-ports { port { replicator_in0: endpoint { remote-endpoint = <&etf_out>; }; }; }; }; etf@6047000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06047000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { etf_out: endpoint { remote-endpoint = <&replicator_in0>; }; }; }; in-ports { port { etf_in: endpoint { remote-endpoint = <&merge_funnel_out>; }; }; }; }; etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; iommus = <&apps_smmu 0x05e0 0x0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,scatter-gather; in-ports { port { etr_in: endpoint { remote-endpoint = <&replicator_out0>; }; }; }; }; replicator@604a000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x0604a000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; replicator1_out: endpoint { remote-endpoint = <&swao_funnel_in>; }; }; }; in-ports { port { replicator1_in: endpoint { remote-endpoint = <&replicator_out1>; }; }; }; }; funnel@6b08000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06b08000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { swao_funnel_out: endpoint { remote-endpoint = <&swao_etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@6 { reg = <6>; swao_funnel_in: endpoint { remote-endpoint = <&replicator1_out>; }; }; }; }; etf@6b09000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06b09000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { swao_etf_out: endpoint { remote-endpoint = <&swao_replicator_in>; }; }; }; in-ports { port { swao_etf_in: endpoint { remote-endpoint = <&swao_funnel_out>; }; }; }; }; replicator@6b0a000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06b0a000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,replicator-loses-context; out-ports { port { swao_replicator_out: endpoint { remote-endpoint = <&funnel1_in4>; }; }; }; in-ports { port { swao_replicator_in: endpoint { remote-endpoint = <&swao_etf_out>; }; }; }; }; etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; cpu = <&CPU0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm0_out: endpoint { remote-endpoint = <&apss_funnel_in0>; }; }; }; }; etm@7140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07140000 0 0x1000>; cpu = <&CPU1>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm1_out: endpoint { remote-endpoint = <&apss_funnel_in1>; }; }; }; }; etm@7240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07240000 0 0x1000>; cpu = <&CPU2>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm2_out: endpoint { remote-endpoint = <&apss_funnel_in2>; }; }; }; }; etm@7340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07340000 0 0x1000>; cpu = <&CPU3>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm3_out: endpoint { remote-endpoint = <&apss_funnel_in3>; }; }; }; }; etm@7440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07440000 0 0x1000>; cpu = <&CPU4>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm4_out: endpoint { remote-endpoint = <&apss_funnel_in4>; }; }; }; }; etm@7540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07540000 0 0x1000>; cpu = <&CPU5>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm5_out: endpoint { remote-endpoint = <&apss_funnel_in5>; }; }; }; }; etm@7640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07640000 0 0x1000>; cpu = <&CPU6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm6_out: endpoint { remote-endpoint = <&apss_funnel_in6>; }; }; }; }; etm@7740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07740000 0 0x1000>; cpu = <&CPU7>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm7_out: endpoint { remote-endpoint = <&apss_funnel_in7>; }; }; }; }; funnel@7800000 { /* APSS Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07800000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_funnel_out: endpoint { remote-endpoint = <&apss_merge_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel_in0: endpoint { remote-endpoint = <&etm0_out>; }; }; port@1 { reg = <1>; apss_funnel_in1: endpoint { remote-endpoint = <&etm1_out>; }; }; port@2 { reg = <2>; apss_funnel_in2: endpoint { remote-endpoint = <&etm2_out>; }; }; port@3 { reg = <3>; apss_funnel_in3: endpoint { remote-endpoint = <&etm3_out>; }; }; port@4 { reg = <4>; apss_funnel_in4: endpoint { remote-endpoint = <&etm4_out>; }; }; port@5 { reg = <5>; apss_funnel_in5: endpoint { remote-endpoint = <&etm5_out>; }; }; port@6 { reg = <6>; apss_funnel_in6: endpoint { remote-endpoint = <&etm6_out>; }; }; port@7 { reg = <7>; apss_funnel_in7: endpoint { remote-endpoint = <&etm7_out>; }; }; }; }; funnel@7810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07810000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_merge_funnel_out: endpoint { remote-endpoint = <&funnel2_in2>; }; }; }; in-ports { port { apss_merge_funnel_in: endpoint { remote-endpoint = <&apss_funnel_out>; }; }; }; }; remoteproc_cdsp: remoteproc@8300000 { compatible = "qcom,sm8150-cdsp-pas"; reg = <0x0 0x08300000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SM8150_CX>; memory-region = <&cdsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; label = "cdsp"; qcom,remote-pid = <5>; mboxes = <&apss_shared 4>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x1001 0x0460>; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x1002 0x0460>; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1003 0x0460>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1004 0x0460>; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1005 0x0460>; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x1006 0x0460>; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x1007 0x0460>; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x1008 0x0460>; }; /* note: secure cb9 in downstream */ }; }; }; usb_1_hsphy: phy@88e2000 { compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; usb_2_hsphy: phy@88e3000 { compatible = "qcom,sm8150-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; usb_1_qmpphy: phy@88e9000 { compatible = "qcom,sm8150-qmp-usb3-phy"; reg = <0 0x088e9000 0 0x18c>, <0 0x088e8000 0 0x10>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux", "ref_clk_src", "ref", "com_aux"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; usb_1_ssphy: phy@88e9200 { reg = <0 0x088e9200 0 0x200>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x218>, <0 0x088e9600 0 0x200>, <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; }; usb_2_qmpphy: phy@88eb000 { compatible = "qcom,sm8150-qmp-usb3-uni-phy"; reg = <0 0x088eb000 0 0x200>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; clock-names = "aux", "ref_clk_src", "ref", "com_aux"; resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; usb_2_ssphy: phy@88eb200 { reg = <0 0x088eb200 0 0x200>, <0 0x088eb400 0 0x200>, <0 0x088eb800 0 0x800>, <0 0x088eb600 0 0x200>; #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_uni_phy_pipe_clk_src"; }; }; sdhc_2: mmc@8804000 { compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x6a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd 0>; operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-50000000 { opp-hz = /bits/ 64 <50000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; dc_noc: interconnect@9160000 { compatible = "qcom,sm8150-dc-noc"; reg = <0 0x09160000 0 0x3200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9680000 { compatible = "qcom,sm8150-gem-noc"; reg = <0 0x09680000 0 0x3e200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; usb_1: usb@a6f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; usb_2: usb@a8f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB30_SEC_BCR>; interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_2_hsphy>, <&usb_2_ssphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; camnoc_virt: interconnect@ac00000 { compatible = "qcom,sm8150-camnoc-virt"; reg = <0 0x0ac00000 0 0x1000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mdss: display-subsystem@ae00000 { compatible = "qcom,sm8150-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "bus", "nrt_bus", "core"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; iommus = <&apps_smmu 0x800 0x420>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8150-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SM8150_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-171428571 { opp-hz = /bits/ 64 <171428571>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-460000000 { opp-hz = /bits/ 64 <460000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8150_MMCX>; phys = <&mdss_dsi0_phy>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; mdss_dsi0_out: endpoint { }; }; }; dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { opp-hz = /bits/ 64 <187500000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-358000000 { opp-hz = /bits/ 64 <358000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94900 0 0x260>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; mdss_dsi1: dsi@ae96000 { compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8150_MMCX>; phys = <&mdss_dsi1_phy>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; mdss_dsi1_out: endpoint { }; }; }; }; mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, <0 0x0ae96900 0 0x260>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; }; dispcc: clock-controller@af00000 { compatible = "qcom,sm8150-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, <0>, <0>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SM8150_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; aoss_qmp: power-management@c300000 { compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = ; mboxes = <&apss_shared 0>; #clock-cells = <0>; }; sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0 0x0c3f0000 0 0x400>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; interrupts = , ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x0001100>, <0x0 0x0c600000 0x0 0x2000000>, <0x0 0x0e600000 0x0 0x0100000>, <0x0 0x0e700000 0x0 0x00a0000>, <0x0 0x0c40a000 0x0 0x0026000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; apps_smmu: iommu@15000000 { compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,sm8150-adsp-pas"; reg = <0x0 0x17300000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SM8150_CX>; memory-region = <&adsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; label = "lpass"; qcom,remote-pid = <2>; mboxes = <&apss_shared 8>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1b23 0x0>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1b24 0x0>; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1b25 0x0>; }; }; }; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; }; apss_shared: mailbox@17c00000 { compatible = "qcom,sm8150-apss-shared", "qcom,sdm845-apss-shared"; reg = <0x0 0x17c00000 0x0 0x1000>; #mbox-cells = <1>; }; watchdog@17c10000 { compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = ; }; timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; frame@17c21000 { frame-number = <0>; interrupts = , ; reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = ; reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = ; reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = ; reg = <0x17c26000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = ; reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = ; reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = ; reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@18200000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, <0x0 0x18210000 0x0 0x10000>, <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; rpmhpd: power-controller { compatible = "qcom,sm8150-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = ; }; rpmhpd_opp_min_svs: opp2 { opp-level = ; }; rpmhpd_opp_low_svs: opp3 { opp-level = ; }; rpmhpd_opp_svs: opp4 { opp-level = ; }; rpmhpd_opp_svs_l1: opp5 { opp-level = ; }; rpmhpd_opp_svs_l2: opp6 { opp-level = <224>; }; rpmhpd_opp_nom: opp7 { opp-level = ; }; rpmhpd_opp_nom_l1: opp8 { opp-level = ; }; rpmhpd_opp_nom_l2: opp9 { opp-level = ; }; rpmhpd_opp_turbo: opp10 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp11 { opp-level = ; }; }; }; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; osm_l3: interconnect@18321000 { compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; reg = <0 0x18321000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18323000 { compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, <0 0x18327800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; #clock-cells = <1>; }; lmh_cluster1: lmh@18350800 { compatible = "qcom,sm8150-lmh"; reg = <0 0x18350800 0 0x400>; interrupts = ; cpus = <&CPU4>; qcom,lmh-temp-arm-millicelsius = <60000>; qcom,lmh-temp-low-millicelsius = <84500>; qcom,lmh-temp-high-millicelsius = <85000>; interrupt-controller; #interrupt-cells = <1>; }; lmh_cluster0: lmh@18358800 { compatible = "qcom,sm8150-lmh"; reg = <0 0x18358800 0 0x400>; interrupts = ; cpus = <&CPU0>; qcom,lmh-temp-arm-millicelsius = <60000>; qcom,lmh-temp-low-millicelsius = <84500>; qcom,lmh-temp-high-millicelsius = <85000>; interrupt-controller; #interrupt-cells = <1>; }; wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; reg = <0 0x18800000 0 0x800000>; reg-names = "membase"; memory-region = <&wlan_mem>; clock-names = "cxo_ref_clk_pin", "qdss"; clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; interrupts = , , , , , , , , , , , ; iommus = <&apps_smmu 0x0640 0x1>; status = "disabled"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 1>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu0_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu0_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 2>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu1_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu1_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 3>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu2_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu2_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 4>; trips { cpu3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu3_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu3_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 7>; trips { cpu4_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 8>; trips { cpu5_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 9>; trips { cpu6_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 10>; trips { cpu7_top_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_top_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_top_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 11>; trips { cpu4_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 12>; trips { cpu5_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 13>; trips { cpu6_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 14>; trips { cpu7_bottom_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_bottom_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_bottom_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; aoss0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 0>; trips { aoss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; cluster0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 5>; trips { cluster0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster0_crit: cluster0_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cluster1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 6>; trips { cluster1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster1_crit: cluster1_crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens0 15>; trips { gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; aoss1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 0>; trips { aoss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; wlan-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 1>; trips { wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; video-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 2>; trips { video_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; mem-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 3>; trips { mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; q6-hvx-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 4>; trips { q6_hvx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; camera-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 5>; trips { camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; compute-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 6>; trips { compute_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; modem-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 7>; trips { modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; npu-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 8>; trips { npu_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; modem-vec-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 9>; trips { modem_vec_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; modem-scl-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 10>; trips { modem_scl_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens1 11>; trips { gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; }; };