# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. QCM2290 TLMM block maintainers: - Shawn Guo <shawn.guo@linaro.org> description: Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC. properties: compatible: const: qcom,qcm2290-tlmm reg: maxItems: 1 interrupts: true interrupt-controller: true "#interrupt-cells": true gpio-controller: true "#gpio-cells": true gpio-ranges: true wakeup-parent: true patternProperties: "-state$": oneOf: - $ref: "#/$defs/qcom-qcm2290-tlmm-state" - patternProperties: "-pins$": $ref: "#/$defs/qcom-qcm2290-tlmm-state" additionalProperties: false $defs: qcom-qcm2290-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state properties: pins: description: List of gpio pins affected by the properties specified in this subnode. items: oneOf: - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$" - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] minItems: 1 maxItems: 36 function: description: Specify the alternative function to be configured for the specified pins. enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec, cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1, pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11, pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist, pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3, pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write, ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1 ] bias-pull-down: true bias-pull-up: true bias-disable: true drive-strength: true output-high: true output-low: true required: - pins additionalProperties: false allOf: - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# required: - compatible - reg additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> tlmm: pinctrl@500000 { compatible = "qcom,qcm2290-tlmm"; reg = <0x500000 0x300000>; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 127>; sdc2_on_state: sdc2-on-state { clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; };