# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT7530 and MT7531 Ethernet Switches maintainers: - Arınç ÜNAL - Landen Chao - DENG Qingfang - Sean Wang - Daniel Golle description: | There are three versions of MT7530, standalone, in a multi-chip module and built-into a SoC. MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's memory map rather than using MDIO. The switch got an internally connected 10G CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs. MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs and the switch registers are directly mapped into SoC's memory map rather than using MDIO. The DSA driver currently doesn't support MT7620 variants. There is only the standalone version of MT7531. Port 5 on MT7530 has got various ways of configuration: - Port 5 can be used as a CPU port. - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore, the gmac of the SoC which is wired to port 5 can connect to the PHY. This is usually used for connecting the wan port directly to the CPU to achieve 2 Gbps routing in total. The driver looks up the reg on the ethernet-phy node, which the phy-handle property on the gmac node refers to, to mux the specified phy. The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the compatible string and the reg must be 1. So, for now, only gmac1 of a MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. Check out example 5. - For the multi-chip module MT7530, in case of an external phy wired to gmac1 of the SoC, port 5 must not be enabled. In case of muxing PHY 0 or 4, the external phy must not be enabled. For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. Check out example 6. - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. For the multi-chip module MT7530, the external phy must be wired TX to TX to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired this way. For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. Check out example 7. properties: compatible: oneOf: - description: Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC const: mediatek,mt7530 - description: Standalone MT7531 const: mediatek,mt7531 - description: Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs const: mediatek,mt7621 - description: Built-in switch of the MT7988 SoC const: mediatek,mt7988-switch reg: maxItems: 1 core-supply: description: Phandle to the regulator node necessary for the core power. "#gpio-cells": const: 2 gpio-controller: type: boolean description: | If defined, LED controller of the MT7530 switch will run on GPIO mode. There are 15 controllable pins. port 0 LED 0..2 as GPIO 0..2 port 1 LED 0..2 as GPIO 3..5 port 2 LED 0..2 as GPIO 6..8 port 3 LED 0..2 as GPIO 9..11 port 4 LED 0..2 as GPIO 12..14 "#interrupt-cells": const: 1 interrupt-controller: true interrupts: maxItems: 1 io-supply: description: | Phandle to the regulator node necessary for the I/O power. See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for details for the regulator setup on these boards. mediatek,mcm: type: boolean description: Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 switch is a part of the multi-chip module. reset-gpios: description: | GPIO to reset the switch. Use this if mediatek,mcm is not used. This property is optional because some boards share the reset line with other components which makes it impossible to probe the switch if the reset line is used. maxItems: 1 reset-names: const: mcm resets: description: Phandle pointing to the system reset controller with line index for the ethsys. maxItems: 1 patternProperties: "^(ethernet-)?ports$": type: object patternProperties: "^(ethernet-)?port@[0-9]+$": type: object properties: reg: description: Port address described must be 5 or 6 for CPU port and from 0 to 5 for user ports. allOf: - if: required: [ ethernet ] then: properties: reg: enum: - 5 - 6 required: - compatible - reg $defs: mt7530-dsa-port: patternProperties: "^(ethernet-)?ports$": patternProperties: "^(ethernet-)?port@[0-9]+$": if: required: [ ethernet ] then: if: properties: reg: const: 5 then: properties: phy-mode: enum: - gmii - mii - rgmii else: properties: phy-mode: enum: - rgmii - trgmii mt7531-dsa-port: patternProperties: "^(ethernet-)?ports$": patternProperties: "^(ethernet-)?port@[0-9]+$": if: required: [ ethernet ] then: if: properties: reg: const: 5 then: properties: phy-mode: enum: - 1000base-x - 2500base-x - rgmii - sgmii else: properties: phy-mode: enum: - 1000base-x - 2500base-x - sgmii allOf: - $ref: dsa.yaml#/$defs/ethernet-ports - if: required: - mediatek,mcm then: properties: reset-gpios: false required: - resets - reset-names - dependencies: interrupt-controller: [ interrupts ] - if: properties: compatible: const: mediatek,mt7530 then: $ref: "#/$defs/mt7530-dsa-port" required: - core-supply - io-supply - if: properties: compatible: const: mediatek,mt7531 then: $ref: "#/$defs/mt7531-dsa-port" properties: gpio-controller: false mediatek,mcm: false - if: properties: compatible: const: mediatek,mt7621 then: $ref: "#/$defs/mt7530-dsa-port" required: - mediatek,mcm - if: properties: compatible: const: mediatek,mt7988-switch then: $ref: "#/$defs/mt7530-dsa-port" properties: gpio-controller: false mediatek,mcm: false reset-names: false unevaluatedProperties: false examples: # Example 1: Standalone MT7530 - | #include mdio { #address-cells = <1>; #size-cells = <0>; switch@1f { compatible = "mediatek,mt7530"; reg = <0x1f>; reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "rgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; # Example 2: MT7530 in MT7623AI SoC - | #include mdio { #address-cells = <1>; #size-cells = <0>; switch@1f { compatible = "mediatek,mt7530"; reg = <0x1f>; mediatek,mcm; resets = <ðsys MT2701_ETHSYS_MCM_RST>; reset-names = "mcm"; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; # Example 3: Standalone MT7531 - | #include #include mdio { #address-cells = <1>; #size-cells = <0>; switch@0 { compatible = "mediatek,mt7531"; reg = <0>; reset-gpios = <&pio 54 0>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&pio>; interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; }; }; }; # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs - | #include #include mdio { #address-cells = <1>; #size-cells = <0>; switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 - | #include #include ethernet { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rgmii2_pins>; mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "rgmii"; phy-handle = <&example5_ethphy4>; }; mdio { #address-cells = <1>; #size-cells = <0>; /* MT7530's phy4 */ example5_ethphy4: ethernet-phy@4 { reg = <4>; }; switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; /* Commented out, phy4 is connected to gmac1. port@4 { reg = <4>; label = "wan"; }; */ port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; }; # Example 6: MT7621: mux external phy to SoC's gmac1 - | #include #include ethernet { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rgmii2_pins>; mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "rgmii"; phy-handle = <&example6_ethphy7>; }; mdio { #address-cells = <1>; #size-cells = <0>; /* External PHY */ example6_ethphy7: ethernet-phy@7 { reg = <7>; phy-mode = "rgmii"; }; switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; }; # Example 7: MT7621: mux external phy to MT7530's port 5 - | #include #include ethernet { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rgmii2_pins>; mdio { #address-cells = <1>; #size-cells = <0>; /* External PHY */ example7_ethphy7: ethernet-phy@7 { reg = <7>; phy-mode = "rgmii"; }; switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@5 { reg = <5>; label = "extphy"; phy-mode = "rgmii-txid"; phy-handle = <&example7_ethphy7>; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; }; }; }; };