# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: mediatek display DSC controller maintainers: - Chun-Kuang Hu - Philipp Zabel description: | The DSC standard is a specification of the algorithms used for compressing and decompressing image display streams, including the specification of the syntax and semantics of the compressed video bit stream. DSC is designed for real-time systems with real-time compression, transmission, decompression and Display. properties: compatible: oneOf: - items: - const: mediatek,mt8195-disp-dsc reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: DSC Wrapper Clock power-domains: description: A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. mediatek,gce-client-reg: description: The register of client driver can be configured by gce with 4 arguments defined in this property, such as phandle of gce, subsys id, register offset and size. Each subsys id is mapping to a base address of display function blocks register which is defined in the gce header include/dt-bindings/gce/-gce.h. $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 required: - compatible - reg - interrupts - power-domains - clocks additionalProperties: false examples: - | dsc0: disp_dsc_wrap@1c009000 { compatible = "mediatek,mt8195-disp-dsc"; reg = <0 0x1c009000 0 0x1000>; interrupts = ; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; };