Lines Matching +full:0 +full:- +full:100
1 // SPDX-License-Identifier: GPL-2.0+
16 * The test contains a pre-built table of instructions, operands and
40 100,
46 100,
47 -200,
48 -100
52 100,
58 100,
59 -200,
60 -100
64 100,
70 100,
71 -200,
72 -100
76 100,
78 100
84 -100
88 100,
90 100
96 -100
100 100,
102 200 + ~100
118 0x10000000,
119 0x10000000,
120 0x1000000
124 0x80000000,
125 0x80000000,
126 0x40000000
130 -20,
132 -4
136 0x8000,
137 0x200,
138 0x40
145 int ret = 0; in cpu_post_test_three()
149 for (i = 0; i < cpu_post_three_size && ret == 0; i++) in cpu_post_test_three()
153 for (reg = 0; reg < 32 && ret == 0; reg++) in cpu_post_test_three()
155 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_three()
161 ASM_STW(stk, 1, -4), in cpu_post_test_three()
162 ASM_ADDI(stk, 1, -24), in cpu_post_test_three()
167 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
172 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
177 ASM_LWZ(stk, 1, -4), in cpu_post_test_three()
182 ASM_STW(stk, 1, -4), in cpu_post_test_three()
183 ASM_ADDI(stk, 1, -24), in cpu_post_test_three()
188 ASM_STW(reg2, stk, 0), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
193 ASM_LWZ(reg2, stk, 0), in cpu_post_test_three()
198 ASM_LWZ(stk, 1, -4), in cpu_post_test_three()
204 if (ret == 0) in cpu_post_test_three()
206 cr = 0; in cpu_post_test_three()
207 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
209 ret = res == test->res && cr == 0 ? 0 : -1; in cpu_post_test_three()
211 if (ret != 0) in cpu_post_test_three()
217 if (ret == 0) in cpu_post_test_three()
219 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); in cpu_post_test_three()
221 ret = res == test->res && in cpu_post_test_three()
222 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; in cpu_post_test_three()
224 if (ret != 0) in cpu_post_test_three()