u-boot/include/w83c553f.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
9 /* from the winbond data sheet -
10  The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
81 #define W83C553F_DMA1	CONFIG_SYS_ISA_IO + 0x000	/* channel 0 - 3 */
82 #define W83C553F_DMA2	CONFIG_SYS_ISA_IO + 0x0C0	/* channel 4 - 7 */
86 #define W83C553F_CS_COM_DACKAL	(1<<7)	/* DACK# assert level */
89 #define W83C553F_CS_COM_CGE	(1<<2)	/* channel group enable */
91 #define W83C553F_CS_STAT_CH0REQ	(1<<4)	/* channel 0 (4) DREQ status */
92 #define W83C553F_CS_STAT_CH1REQ	(1<<5)	/* channel 1 (5) DREQ status */
93 #define W83C553F_CS_STAT_CH2REQ	(1<<6)	/* channel 2 (6) DREQ status */
94 #define W83C553F_CS_STAT_CH3REQ	(1<<7)	/* channel 3 (7) DREQ status */
96 #define W83C553F_CS_STAT_CH0TC	(1<<0)	/* channel 0 (4) TC status */
97 #define W83C553F_CS_STAT_CH1TC	(1<<1)	/* channel 1 (5) TC status */
98 #define W83C553F_CS_STAT_CH2TC	(1<<2)	/* channel 2 (6) TC status */
99 #define W83C553F_CS_STAT_CH3TC	(1<<3)	/* channel 3 (7) TC status */
103 #define W83C553F_MODE_TM_DEMAND	(0<<6)	/* transfer mode - demand */
104 #define W83C553F_MODE_TM_SINGLE	(1<<6)	/* transfer mode - single */
105 #define W83C553F_MODE_TM_BLOCK	(2<<6)	/* transfer mode - block */
106 #define W83C553F_MODE_TM_CASCADE	(3<<6)	/* transfer mode - cascade */
109 #define W83C553F_MODE_TT_VERIFY	(0<<2)	/* transfer type - verify */
110 #define W83C553F_MODE_TT_WRITE	(1<<2)	/* transfer type - write */
111 #define W83C553F_MODE_TT_READ	(2<<2)	/* transfer type - read */
112 #define W83C553F_MODE_TT_ILLEGAL	(3<<2)	/* transfer type - illegal */
113 #define W83C553F_MODE_CH0SEL	(0<<0)	/* channel 0 (4) select */
114 #define W83C553F_MODE_CH1SEL	(1<<0)	/* channel 1 (5) select */
115 #define W83C553F_MODE_CH2SEL	(2<<0)	/* channel 2 (6) select */
116 #define W83C553F_MODE_CH3SEL	(3<<0)	/* channel 3 (7) select */
120 #define W83C553F_REQ_CHSERREQ	(1<<2)	/* channel service request */
121 #define W83C553F_REQ_CH0SEL	(0<<0)	/* channel 0 (4) select */
122 #define W83C553F_REQ_CH1SEL	(1<<0)	/* channel 1 (5) select */
123 #define W83C553F_REQ_CH2SEL	(2<<0)	/* channel 2 (6) select */
124 #define W83C553F_REQ_CH3SEL	(3<<0)	/* channel 3 (7) select */
128 #define W83C553F_WSMB_CHMASKSEL	(1<<2)	/* channel mask select */
129 #define W83C553F_WSMB_CH0SEL	(0<<0)	/* channel 0 (4) select */
130 #define W83C553F_WSMB_CH1SEL	(1<<0)	/* channel 1 (5) select */
131 #define W83C553F_WSMB_CH2SEL	(2<<0)	/* channel 2 (6) select */
132 #define W83C553F_WSMB_CH3SEL	(3<<0)	/* channel 3 (7) select */
136 #define W83C553F_RWAMB_CH0MASK	(1<<0)	/* channel 0 (4) mask */
137 #define W83C553F_RWAMB_CH1MASK	(1<<1)	/* channel 1 (5) mask */
138 #define W83C553F_RWAMB_CH2MASK	(1<<2)	/* channel 2 (6) mask */
139 #define W83C553F_RWAMB_CH3MASK	(1<<3)	/* channel 3 (7) mask */