Lines Matching +full:srp +full:- +full:disable
1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Dante Su <dantesu@faraday-tech.com>
16 } hccr; /* 0x00 - 0x0f: hccr */
19 } hcor; /* 0x10 - 0x33: hcor */
50 uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
51 uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
54 uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
55 uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
60 uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
81 #define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */
82 #define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */
85 #define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */
86 #define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */
87 #define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */
88 #define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */
95 #define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */
96 #define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */
97 #define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */
98 #define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */
99 #define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */
100 #define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */
101 #define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */
102 #define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */
103 #define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */
106 #define OTGISR_APRM (1 << 12) /* Mini-A plug removed */
107 #define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */
108 #define OTGISR_OVD (1 << 10) /* over-current detected */
111 #define OTGISR_BSESSEND (1 << 6) /* B-device Session End */
112 #define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */
113 #define OTGISR_ASRP (1 << 4) /* A-device SRP detected */
114 #define OTGISR_BSRP (1 << 0) /* B-device SRP complete */
117 #define OTGIER_APRM (1 << 12) /* Mini-A plug removed */
118 #define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */
119 #define OTGIER_OVD (1 << 10) /* over-current detected */
122 #define OTGIER_BSESSEND (1 << 6) /* B-device Session End */
123 #define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */
124 #define OTGIER_ASRP (1 << 4) /* A-device SRP detected */
125 #define OTGIER_BSRP (1 << 0) /* B-device SRP complete */
134 #define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */
135 #define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */
142 #define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */
150 #define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */
167 #define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
175 #define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */
176 #define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */
177 #define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */
178 #define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */
198 /* Group Interrupt Mask(Disable) Register */
199 #define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */
200 #define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */
201 #define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */
204 /* Group Interrupt Mask(Disable) Register 0 (CX) */
208 #define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
209 #define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
210 #define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
213 /* Group Interrupt Mask(Disable) Register 1 (FIFO) */
221 /* Group Interrupt Mask(Disable) Register 2 (Device) */
226 #define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
227 #define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
244 #define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */
245 #define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */
246 #define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */
259 #define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */
260 #define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */
267 /* Receive Zero-Length-Packet Register */
268 #define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
270 /* Transfer Zero-Length-Packet Register */
271 #define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
274 #define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
277 #define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */
279 /* Transaction Number for High-Bandwidth EP(ISOC) */
291 ((fifo) & 3) << (((ep) - 1) << 3 + 0)
293 ((fifo) & 3) << (((ep) - 1) << 3 + 4)
300 #define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
304 ((fifo) & 3) << (((ep) - 5) << 3 + 0)
306 ((fifo) & 3) << (((ep) - 5) << 3 + 4)
313 #define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */
323 #define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
346 #define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */