Lines Matching +full:3 +full:- +full:point
1 /* SPDX-License-Identifier: GPL-2.0+ */
18 /* offsets for the non-ehci registers in the FSL SOC USB controller */
21 #define PORT_PTS_MSK (3 << 30)
24 #define PORT_PTS_SERIAL (3 << 30)
26 #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
35 #define CM_HOST (3 << 0)
38 #define SLOM (1 << 3)
45 #define LSF_EN (1 << 3)
58 #define CLKIN_SEL_SYS_CLK2 (3 << 11)
71 #define CTRL_OTG_TERMINATION (0x1<<3)
122 #define GC_PPP (1 << 3) /* Port Power Polarity */
128 #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
129 #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
134 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
135 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
136 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
137 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
138 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
139 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
174 u32 id; /* 0x000 - Identification register */
175 u32 hwgeneral; /* 0x004 - General hardware parameters */
176 u32 hwhost; /* 0x008 - Host hardware parameters */
177 u32 hwdevice; /* 0x00C - Device hardware parameters */
178 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
179 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
181 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
182 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
183 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
184 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
185 u32 sbuscfg; /* 0x090 - System Bus Interface Control */
186 u32 sbusstatus; /* 0x094 - System Bus Interface Status */
187 u32 sbusmode; /* 0x098 - System Bus Interface Mode */
188 u32 genconfig; /* 0x09C - USB Core Configuration */
189 u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
191 u8 caplength; /* 0x100 - Capability Register Length */
193 u16 hciversion; /* 0x102 - Host Interface Version */
194 u32 hcsparams; /* 0x104 - Host Structural Parameters */
195 u32 hccparams; /* 0x108 - Host Capability Parameters */
197 u32 dciversion; /* 0x120 - Device Interface Version */
198 u32 dciparams; /* 0x124 - Device Controller Params */
200 u32 usbcmd; /* 0x140 - USB Command */
201 u32 usbsts; /* 0x144 - USB Status */
202 u32 usbintr; /* 0x148 - USB Interrupt Enable */
203 u32 frindex; /* 0x14C - USB Frame Index */
205 u32 perlistbase; /* 0x154 - Periodic List Base
206 - USB Device Address */
207 u32 ep_list_addr; /* 0x158 - Next Asynchronous List
208 - End Point Address */
210 u32 burstsize; /* 0x160 - Programmable Burst Size */
213 u32 txfilltuning; /* 0x164 - Host TT Transmit
214 pre-buffer packet tuning */
216 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
218 u32 config_flag; /* 0x180 - Configured Flag Register */
219 u32 portsc; /* 0x184 - Port status/control */
221 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
222 u32 usbmode; /* 0x1a8 - USB Device Mode */
223 u32 epsetupstat; /* 0x1ac - End Point Setup Status */
224 u32 epprime; /* 0x1b0 - End Point Init Status */
225 u32 epflush; /* 0x1b4 - End Point De-initlialize */
226 u32 epstatus; /* 0x1b8 - End Point Status */
227 u32 epcomplete; /* 0x1bc - End Point Complete */
228 u32 epctrl0; /* 0x1c0 - End Point Control 0 */
229 u32 epctrl1; /* 0x1c4 - End Point Control 1 */
230 u32 epctrl2; /* 0x1c8 - End Point Control 2 */
231 u32 epctrl3; /* 0x1cc - End Point Control 3 */
232 u32 epctrl4; /* 0x1d0 - End Point Control 4 */
233 u32 epctrl5; /* 0x1d4 - End Point Control 5 */
235 u32 usbgenctrl; /* 0x200 - USB General Control */
236 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
238 u32 snoop1; /* 0x400 - Snoop 1 */
239 u32 snoop2; /* 0x404 - Snoop 2 */
240 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
241 u32 prictrl; /* 0x40c - Priority Control */
242 u32 sictrl; /* 0x410 - System Interface Control */
244 u32 control; /* 0x500 - Control */
261 #define MXC_EHCI_MODE_SERIAL (3 << 30)
267 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
280 /* Board-specific initialization */