Lines Matching +full:0 +full:x410
13 #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */
16 #define FSL_SKIP_PCI 0x100
19 #define FSL_SOC_USB_ULPIVP 0x170
20 #define FSL_SOC_USB_PORTSC1 0x184
22 #define PORT_PTS_UTMI (0 << 30)
32 #define CM_IDLE (0 << 0)
33 #define CM_RESERVED (1 << 0)
34 #define CM_DEVICE (2 << 0)
35 #define CM_HOST (3 << 0)
37 #define USBMODE_RESERVED_2 (0 << 2)
42 #define ULPI_INT_EN (1 << 0)
48 #define REFSEL_12MHZ (0 << 6)
53 #define PHY_CLK_SEL_UTMI (0 << 10)
55 #define CLKIN_SEL_USB_CLK (0 << 11)
59 #define RESERVED_18 (0 << 13)
60 #define RESERVED_17 (0 << 14)
61 #define RESERVED_16 (0 << 15)
65 #define FSL_SOC_USB_PORTSC2 0x188
68 #define FSL_SOC_USB_OTGSC 0x1a4
69 #define CTRL_VBUS_DISCHARGE (0x1<<0)
70 #define CTRL_VBUS_CHARGE (0x1<<1)
71 #define CTRL_OTG_TERMINATION (0x1<<3)
72 #define CTRL_DATA_PULSING (0x1<<4)
73 #define CTRL_ID_PULL_EN (0x1<<5)
74 #define HA_DATA_PULSE (0x1<<6)
75 #define HA_BA (0x1<<7)
76 #define STS_USB_ID (0x1<<8)
77 #define STS_A_VBUS_VALID (0x1<<9)
78 #define STS_A_SESSION_VALID (0x1<<10)
79 #define STS_B_SESSION_VALID (0x1<<11)
80 #define STS_B_SESSION_END (0x1<<12)
81 #define STS_1MS_TOGGLE (0x1<<13)
82 #define STS_DATA_PULSING (0x1<<14)
83 #define INTSTS_USB_ID (0x1<<16)
84 #define INTSTS_A_VBUS_VALID (0x1<<17)
85 #define INTSTS_A_SESSION_VALID (0x1<<18)
86 #define INTSTS_B_SESSION_VALID (0x1<<19)
87 #define INTSTS_B_SESSION_END (0x1<<20)
88 #define INTSTS_1MS (0x1<<21)
89 #define INTSTS_DATA_PULSING (0x1<<22)
90 #define INTR_USB_ID_EN (0x1<<24)
91 #define INTR_A_VBUS_VALID_EN (0x1<<25)
92 #define INTR_A_SESSION_VALID_EN (0x1<<26)
93 #define INTR_B_SESSION_VALID_EN (0x1<<27)
94 #define INTR_B_SESSION_END_EN (0x1<<28)
95 #define INTR_1MS_TIMER_EN (0x1<<29)
96 #define INTR_DATA_PULSING_EN (0x1<<30)
97 #define INTSTS_MASK (0x00ff0000)
117 #define FSL_SOC_USB_USBMODE 0x1a8
119 #define USBGENCTRL 0x200 /* NOTE: big endian */
127 #define ISIPHYCTRL 0x204 /* NOTE: big endian */
132 #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
134 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
135 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
136 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
137 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
138 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
139 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
140 #define SNOOP_SIZE_2GB 0x1e
143 #define MPC83XX_SCCR_USB_MASK 0x00f00000
144 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
145 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
146 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
153 #define CONFIG_SYS_FSL_USB2_ADDR 0
160 #define CONFIG_SYS_FSL_USB2_ADDR 0
174 u32 id; /* 0x000 - Identification register */
175 u32 hwgeneral; /* 0x004 - General hardware parameters */
176 u32 hwhost; /* 0x008 - Host hardware parameters */
177 u32 hwdevice; /* 0x00C - Device hardware parameters */
178 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
179 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
180 u8 res1[0x68];
181 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
182 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
183 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
184 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
185 u32 sbuscfg; /* 0x090 - System Bus Interface Control */
186 u32 sbusstatus; /* 0x094 - System Bus Interface Status */
187 u32 sbusmode; /* 0x098 - System Bus Interface Mode */
188 u32 genconfig; /* 0x09C - USB Core Configuration */
189 u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */
190 u8 res2[0x5c];
191 u8 caplength; /* 0x100 - Capability Register Length */
192 u8 res3[0x1];
193 u16 hciversion; /* 0x102 - Host Interface Version */
194 u32 hcsparams; /* 0x104 - Host Structural Parameters */
195 u32 hccparams; /* 0x108 - Host Capability Parameters */
196 u8 res4[0x14];
197 u32 dciversion; /* 0x120 - Device Interface Version */
198 u32 dciparams; /* 0x124 - Device Controller Params */
199 u8 res5[0x18];
200 u32 usbcmd; /* 0x140 - USB Command */
201 u32 usbsts; /* 0x144 - USB Status */
202 u32 usbintr; /* 0x148 - USB Interrupt Enable */
203 u32 frindex; /* 0x14C - USB Frame Index */
204 u8 res6[0x4];
205 u32 perlistbase; /* 0x154 - Periodic List Base
207 u32 ep_list_addr; /* 0x158 - Next Asynchronous List
209 u8 res7[0x4];
210 u32 burstsize; /* 0x160 - Programmable Burst Size */
213 u32 txfilltuning; /* 0x164 - Host TT Transmit
215 u8 res8[0x8];
216 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
217 u8 res9[0xc];
218 u32 config_flag; /* 0x180 - Configured Flag Register */
219 u32 portsc; /* 0x184 - Port status/control */
220 u8 res10[0x1C];
221 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
222 u32 usbmode; /* 0x1a8 - USB Device Mode */
223 u32 epsetupstat; /* 0x1ac - End Point Setup Status */
224 u32 epprime; /* 0x1b0 - End Point Init Status */
225 u32 epflush; /* 0x1b4 - End Point De-initlialize */
226 u32 epstatus; /* 0x1b8 - End Point Status */
227 u32 epcomplete; /* 0x1bc - End Point Complete */
228 u32 epctrl0; /* 0x1c0 - End Point Control 0 */
229 u32 epctrl1; /* 0x1c4 - End Point Control 1 */
230 u32 epctrl2; /* 0x1c8 - End Point Control 2 */
231 u32 epctrl3; /* 0x1cc - End Point Control 3 */
232 u32 epctrl4; /* 0x1d0 - End Point Control 4 */
233 u32 epctrl5; /* 0x1d4 - End Point Control 5 */
234 u8 res11[0x28];
235 u32 usbgenctrl; /* 0x200 - USB General Control */
236 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
237 u8 res12[0x1F8];
238 u32 snoop1; /* 0x400 - Snoop 1 */
239 u32 snoop2; /* 0x404 - Snoop 2 */
240 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
241 u32 prictrl; /* 0x40c - Priority Control */
242 u32 sictrl; /* 0x410 - System Interface Control */
243 u8 res13[0xEC];
244 u32 control; /* 0x500 - Control */
245 u8 res14[0xafc];
255 #define MXC_EHCI_UTMI_8BIT (0 << 28)
258 #define MXC_EHCI_MODE_UTMI (0 << 30)
264 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
265 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
266 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
267 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
268 #define MXC_EHCI_INTERFACE_MASK (0xf)