Lines Matching refs:u32
216 u32 tr64; /* Tx/Rx 64-byte Frame Counter */
217 u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */
218 u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */
219 u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */
220 u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */
221 u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */
222 u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
224 u32 rbyt; /* Receive Byte Counter */
225 u32 rpkt; /* Receive Packet Counter */
226 u32 rfcs; /* Receive FCS Error Counter */
227 u32 rmca; /* Receive Multicast Packet (Counter) */
228 u32 rbca; /* Receive Broadcast Packet */
229 u32 rxcf; /* Receive Control Frame Packet */
230 u32 rxpf; /* Receive Pause Frame Packet */
231 u32 rxuo; /* Receive Unknown OP Code */
232 u32 raln; /* Receive Alignment Error */
233 u32 rflr; /* Receive Frame Length Error */
234 u32 rcde; /* Receive Code Error */
235 u32 rcse; /* Receive Carrier Sense Error */
236 u32 rund; /* Receive Undersize Packet */
237 u32 rovr; /* Receive Oversize Packet */
238 u32 rfrg; /* Receive Fragments */
239 u32 rjbr; /* Receive Jabber */
240 u32 rdrp; /* Receive Drop */
242 u32 tbyt; /* Transmit Byte Counter */
243 u32 tpkt; /* Transmit Packet */
244 u32 tmca; /* Transmit Multicast Packet */
245 u32 tbca; /* Transmit Broadcast Packet */
246 u32 txpf; /* Transmit Pause Control Frame */
247 u32 tdfr; /* Transmit Deferral Packet */
248 u32 tedf; /* Transmit Excessive Deferral Packet */
249 u32 tscl; /* Transmit Single Collision Packet */
251 u32 tmcl; /* Transmit Multiple Collision Packet */
252 u32 tlcl; /* Transmit Late Collision Packet */
253 u32 txcl; /* Transmit Excessive Collision Packet */
254 u32 tncl; /* Transmit Total Collision */
256 u32 res2;
258 u32 tdrp; /* Transmit Drop Frame */
259 u32 tjbr; /* Transmit Jabber Frame */
260 u32 tfcs; /* Transmit FCS Error */
261 u32 txcf; /* Transmit Control Frame */
262 u32 tovr; /* Transmit Oversize Frame */
263 u32 tund; /* Transmit Undersize Frame */
264 u32 tfrg; /* Transmit Fragments Frame */
266 u32 car1; /* Carry Register One */
267 u32 car2; /* Carry Register Two */
268 u32 cam1; /* Carry Register One Mask */
269 u32 cam2; /* Carry Register Two Mask */
273 u32 iaddr0; /* Individual Address Register 0 */
274 u32 iaddr1; /* Individual Address Register 1 */
275 u32 iaddr2; /* Individual Address Register 2 */
276 u32 iaddr3; /* Individual Address Register 3 */
277 u32 iaddr4; /* Individual Address Register 4 */
278 u32 iaddr5; /* Individual Address Register 5 */
279 u32 iaddr6; /* Individual Address Register 6 */
280 u32 iaddr7; /* Individual Address Register 7 */
281 u32 res1[24];
282 u32 gaddr0; /* Group Address Register 0 */
283 u32 gaddr1; /* Group Address Register 1 */
284 u32 gaddr2; /* Group Address Register 2 */
285 u32 gaddr3; /* Group Address Register 3 */
286 u32 gaddr4; /* Group Address Register 4 */
287 u32 gaddr5; /* Group Address Register 5 */
288 u32 gaddr6; /* Group Address Register 6 */
289 u32 gaddr7; /* Group Address Register 7 */
290 u32 res2[24];
295 u32 res000[4];
297 u32 ievent; /* Interrupt Event */
298 u32 imask; /* Interrupt Mask */
299 u32 edis; /* Error Disabled */
300 u32 res01c;
301 u32 ecntrl; /* Ethernet Control */
302 u32 minflr; /* Minimum Frame Length */
303 u32 ptv; /* Pause Time Value */
304 u32 dmactrl; /* DMA Control */
305 u32 tbipa; /* TBI PHY Address */
307 u32 res034[3];
308 u32 res040[48];
311 u32 tctrl; /* Transmit Control */
312 u32 tstat; /* Transmit Status */
313 u32 res108;
314 u32 tbdlen; /* Tx BD Data Length */
315 u32 res110[5];
316 u32 ctbptr; /* Current TxBD Pointer */
317 u32 res128[23];
318 u32 tbptr; /* TxBD Pointer */
319 u32 res188[30];
321 u32 res200;
322 u32 tbase; /* TxBD Base Address */
323 u32 res208[42];
324 u32 ostbd; /* Out of Sequence TxBD */
325 u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
326 u32 res2b8[18];
329 u32 rctrl; /* Receive Control */
330 u32 rstat; /* Receive Status */
331 u32 res308;
332 u32 rbdlen; /* RxBD Data Length */
333 u32 res310[4];
334 u32 res320;
335 u32 crbptr; /* Current Receive Buffer Pointer */
336 u32 res328[6];
337 u32 mrblr; /* Maximum Receive Buffer Length */
338 u32 res344[16];
339 u32 rbptr; /* RxBD Pointer */
340 u32 res388[30];
342 u32 res400;
343 u32 rbase; /* RxBD Base Address */
344 u32 res408[62];
347 u32 maccfg1; /* MAC Configuration #1 */
348 u32 maccfg2; /* MAC Configuration #2 */
349 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
350 u32 hafdup; /* Half-duplex */
351 u32 maxfrm; /* Maximum Frame */
352 u32 res514;
353 u32 res518;
355 u32 res51c;
357 u32 resmdio[6];
359 u32 res538;
361 u32 ifstat; /* Interface Status */
362 u32 macstnaddr1; /* Station Address, part 1 */
363 u32 macstnaddr2; /* Station Address, part 2 */
364 u32 res548[46];
367 u32 res600[32];
371 u32 res740[48];
376 u32 res900[128];
379 u32 resb00[62];
380 u32 attr; /* Default Attribute Register */
381 u32 attreli; /* Default Attribute Extract Length and Index */
384 u32 resc00[256];
406 u32 flags;
423 u32 flags;