Lines Matching defs:dwcddr21mctl
14 struct dwcddr21mctl { struct
15 unsigned int ccr; /* Controller Configuration */
16 unsigned int dcr; /* DRAM Configuration */
17 unsigned int iocr; /* I/O Configuration */
18 unsigned int csr; /* Controller Status */
19 unsigned int drr; /* DRAM refresh */
20 unsigned int tpr0; /* SDRAM Timing Parameters 0 */
21 unsigned int tpr1; /* SDRAM Timing Parameters 1 */
22 unsigned int tpr2; /* SDRAM Timing Parameters 2 */
23 unsigned int gdllcr; /* Global DLL Control */
24 unsigned int dllcr[10]; /* DLL Control */
25 unsigned int rslr[4]; /* Rank System Lantency */
26 unsigned int rdgr[4]; /* Rank DQS Gating */
27 unsigned int dqtr[9]; /* DQ Timing */
28 unsigned int dqstr; /* DQS Timing */
29 unsigned int dqsbtr; /* DQS_b Timing */
30 unsigned int odtcr; /* ODT Configuration */
31 unsigned int dtr[2]; /* Data Training */
32 unsigned int dtar; /* Data Training Address */
33 unsigned int rsved[82]; /* Reserved */
34 unsigned int mr; /* Mode Register */
35 unsigned int emr; /* Extended Mode Register */
36 unsigned int emr2; /* Extended Mode Register 2 */
37 unsigned int emr3; /* Extended Mode Register 3 */
38 unsigned int hpcr[32]; /* Host Port Configurarion */
39 unsigned int pqcr[8]; /* Priority Queue Configuration */
40 unsigned int mmgcr; /* Memory Manager General Config */