Lines Matching +full:0 +full:x240
10 #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
11 #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
12 #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
14 #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
16 #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
17 #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
18 #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
19 #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
21 #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
22 #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
23 #define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
25 #define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
26 #define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
28 #define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
29 #define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
30 #define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
31 #define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
32 #define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
33 #define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
34 #define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
35 #define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
36 #define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
37 #define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
39 #define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
40 #define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
41 #define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
43 #define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
44 #define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240)