Lines Matching refs:CLASS_CSR_BASE_ADDR
15 #define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
16 #define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
17 #define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
19 #define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
30 #define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
32 #define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
35 #define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
37 #define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
43 #define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
45 #define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
47 #define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
48 #define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
49 #define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
51 #define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
52 #define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
53 #define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
54 #define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
55 #define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
56 #define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
57 #define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
58 #define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
59 #define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
60 #define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
62 #define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
66 #define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
67 #define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
73 #define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
77 #define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
78 #define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
79 #define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
80 #define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
81 #define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
82 #define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
83 #define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
84 #define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
86 #define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
90 #define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
92 #define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
93 #define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
94 #define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
95 #define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
96 #define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
97 #define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
98 #define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
99 #define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
100 #define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
101 #define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
102 #define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
103 #define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
105 #define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
106 #define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
108 #define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
109 #define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
111 #define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
113 #define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
114 #define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
115 #define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
116 #define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
117 #define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
118 #define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
120 #define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
121 #define CLASS_AXI_CTRL (CLASS_CSR_BASE_ADDR + 0x2d0)