Lines Matching +full:0 +full:xd0
10 #define FLASH_CMD_CFI 0x98
11 #define FLASH_CMD_READ_ID 0x90
12 #define FLASH_CMD_RESET 0xff
13 #define FLASH_CMD_BLOCK_ERASE 0x20
14 #define FLASH_CMD_ERASE_CONFIRM 0xD0
15 #define FLASH_CMD_WRITE 0x40
16 #define FLASH_CMD_PROTECT 0x60
17 #define FLASH_CMD_SETUP 0x60
18 #define FLASH_CMD_SET_CR_CONFIRM 0x03
19 #define FLASH_CMD_PROTECT_SET 0x01
20 #define FLASH_CMD_PROTECT_CLEAR 0xD0
21 #define FLASH_CMD_CLEAR_STATUS 0x50
22 #define FLASH_CMD_READ_STATUS 0x70
23 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
24 #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
25 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
27 #define FLASH_STATUS_DONE 0x80
28 #define FLASH_STATUS_ESS 0x40
29 #define FLASH_STATUS_ECLBS 0x20
30 #define FLASH_STATUS_PSLBS 0x10
31 #define FLASH_STATUS_VPENS 0x08
32 #define FLASH_STATUS_PSS 0x04
33 #define FLASH_STATUS_DPS 0x02
34 #define FLASH_STATUS_R 0x01
35 #define FLASH_STATUS_PROTECT 0x01
37 #define AMD_CMD_RESET 0xF0
38 #define AMD_CMD_WRITE 0xA0
39 #define AMD_CMD_ERASE_START 0x80
40 #define AMD_CMD_ERASE_SECTOR 0x30
41 #define AMD_CMD_UNLOCK_START 0xAA
42 #define AMD_CMD_UNLOCK_ACK 0x55
43 #define AMD_CMD_WRITE_TO_BUFFER 0x25
44 #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
45 #define AMD_CMD_SET_PPB_ENTRY 0xC0
46 #define AMD_CMD_SET_PPB_EXIT_BC1 0x90
47 #define AMD_CMD_SET_PPB_EXIT_BC2 0x00
48 #define AMD_CMD_PPB_UNLOCK_BC1 0x80
49 #define AMD_CMD_PPB_UNLOCK_BC2 0x30
50 #define AMD_CMD_PPB_LOCK_BC1 0xA0
51 #define AMD_CMD_PPB_LOCK_BC2 0x00
53 #define AMD_STATUS_TOGGLE 0x40
54 #define AMD_STATUS_ERROR 0x20
56 #define ATM_CMD_UNLOCK_SECT 0x70
57 #define ATM_CMD_SOFTLOCK_START 0x80
58 #define ATM_CMD_LOCK_SECT 0x40
60 #define FLASH_CONTINUATION_CODE 0x7F
62 #define FLASH_OFFSET_MANUFACTURER_ID 0x00
63 #define FLASH_OFFSET_DEVICE_ID 0x01
64 #define FLASH_OFFSET_LOWER_SW_BITS 0x0C
65 #define FLASH_OFFSET_DEVICE_ID2 0x0E
66 #define FLASH_OFFSET_DEVICE_ID3 0x0F
67 #define FLASH_OFFSET_CFI 0x55
68 #define FLASH_OFFSET_CFI_ALT 0x555
69 #define FLASH_OFFSET_CFI_RESP 0x10
70 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
72 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
73 #define FLASH_OFFSET_WTOUT 0x1F
74 #define FLASH_OFFSET_WBTOUT 0x20
75 #define FLASH_OFFSET_ETOUT 0x21
76 #define FLASH_OFFSET_CETOUT 0x22
77 #define FLASH_OFFSET_WMAX_TOUT 0x23
78 #define FLASH_OFFSET_WBMAX_TOUT 0x24
79 #define FLASH_OFFSET_EMAX_TOUT 0x25
80 #define FLASH_OFFSET_CEMAX_TOUT 0x26
81 #define FLASH_OFFSET_SIZE 0x27
82 #define FLASH_OFFSET_INTERFACE 0x28
83 #define FLASH_OFFSET_BUFFER_SIZE 0x2A
84 #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
85 #define FLASH_OFFSET_ERASE_REGIONS 0x2D
86 #define FLASH_OFFSET_PROTECT 0x02
87 #define FLASH_OFFSET_USER_PROTECTION 0x85
88 #define FLASH_OFFSET_INTEL_PROTECTION 0x81
90 #define CFI_CMDSET_NONE 0