u-boot/include/mpc8xx.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * (C) Copyright 2000-2004
17 /*-----------------------------------------------------------------------
23 /*-----------------------------------------------------------------------
24  * SYPCR - System Protection Control Register				11-9
34 /*-----------------------------------------------------------------------
35  * SIUMCR - SIU Module Configuration Register				11-6
48 #define SIUMCR_DBGC01	0x00200000	/* - " -				*/
49 #define SIUMCR_DBGC10	0x00400000	/* - " -				*/
50 #define SIUMCR_DBGC11	0x00600000	/* - " -				*/
52 #define SIUMCR_DBPC01	0x00080000	/* - " -				*/
53 #define SIUMCR_DBPC10	0x00100000	/* - " -				*/
54 #define SIUMCR_DBPC11	0x00180000	/* - " -				*/
57 #define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
62 #define SIUMCR_MLRC01	0x00000400	/* - " -				*/
63 #define SIUMCR_MLRC10	0x00000800	/* - " -				*/
64 #define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
72 /*-----------------------------------------------------------------------
73  * TBSCR - Time Base Status and Control Register			11-26
92 /*-----------------------------------------------------------------------
93  * PISCR - Periodic Interrupt Status and Control Register		11-31
103 /*-----------------------------------------------------------------------
104  * RSR - Reset Status Register						 5-4
111 #define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
117 /*-----------------------------------------------------------------------
123 /*-----------------------------------------------------------------------
124  * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
155 /*-----------------------------------------------------------------------
156  * SCCR - System Clock and reset Control Register			15-27
204 /*-----------------------------------------------------------------------
205  * BR - Memory Controler: Base Register					16-9
221 /*-----------------------------------------------------------------------
222  * OR - Memory Controler: Option Register				16-11
232 #define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
233 #define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
236 #define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
237 #define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
238 #define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
239 #define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
240 #define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
241 #define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
242 #define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
243 #define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
244 #define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
245 #define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
246 #define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
247 #define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
248 #define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
249 #define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
250 #define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
251 #define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
254 #define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
257 /*-----------------------------------------------------------------------
258  * MPTPR - Memory Periodic Timer Prescaler Register			16-17
268 /*-----------------------------------------------------------------------
269  * MCR - Memory Command Register
272 #define MCR_OP_READ	0x40000000	/* READ	 command			*/
287 /*-----------------------------------------------------------------------
288  * Machine A Mode Register						16-13
315 #define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
316 #define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
317 #define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
318 #define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
319 #define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
320 #define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
321 #define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
322 #define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
323 #define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
324 #define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
325 #define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
326 #define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
327 #define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
328 #define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
329 #define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
330 #define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
331 #define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
367 /*-----------------------------------------------------------------------
368  * Machine B Mode Register						16-13
395 #define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
396 #define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
397 #define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
398 #define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
399 #define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
400 #define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
401 #define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
402 #define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
403 #define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
404 #define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
405 #define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
406 #define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
407 #define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
408 #define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
409 #define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
410 #define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
411 #define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
447 /*-----------------------------------------------------------------------
448  * Timer Global Configuration Register					18-8
468 /*-----------------------------------------------------------------------
469  * Timer Mode Register							18-9
474 #define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
475 #define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
476 #define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
477 #define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
489 /*-----------------------------------------------------------------------
495 #define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
496 #define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
497 #define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
498 #define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
510 /*-----------------------------------------------------------------------
511  * SPI Controller Registers						31-10
514 #define SPI_MME			0x20	/* Multi-Master Error			*/
522 /*-----------------------------------------------------------------------
523  * PCMCIA Interface General Control Register				17-12
531 #define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
545 /*-----------------------------------------------------------------------