Lines Matching +full:ouput +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2000-2004
17 /*-----------------------------------------------------------------------
23 /*-----------------------------------------------------------------------
24 * SYPCR - System Protection Control Register 11-9
34 /*-----------------------------------------------------------------------
35 * SIUMCR - SIU Module Configuration Register 11-6
48 #define SIUMCR_DBGC01 0x00200000 /* - " - */
49 #define SIUMCR_DBGC10 0x00400000 /* - " - */
50 #define SIUMCR_DBGC11 0x00600000 /* - " - */
52 #define SIUMCR_DBPC01 0x00080000 /* - " - */
53 #define SIUMCR_DBPC10 0x00100000 /* - " - */
54 #define SIUMCR_DBPC11 0x00180000 /* - " - */
57 #define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */
62 #define SIUMCR_MLRC01 0x00000400 /* - " - */
63 #define SIUMCR_MLRC10 0x00000800 /* - " - */
64 #define SIUMCR_MLRC11 0x00000C00 /* - " - */
72 /*-----------------------------------------------------------------------
73 * TBSCR - Time Base Status and Control Register 11-26
92 /*-----------------------------------------------------------------------
93 * PISCR - Periodic Interrupt Status and Control Register 11-31
103 /*-----------------------------------------------------------------------
104 * RSR - Reset Status Register 5-4
111 #define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */
117 /*-----------------------------------------------------------------------
123 /*-----------------------------------------------------------------------
124 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
155 /*-----------------------------------------------------------------------
156 * SCCR - System Clock and reset Control Register 15-27
204 /*-----------------------------------------------------------------------
205 * BR - Memory Controler: Base Register 16-9
221 /*-----------------------------------------------------------------------
222 * OR - Memory Controler: Option Register 16-11
257 /*-----------------------------------------------------------------------
258 * MPTPR - Memory Periodic Timer Prescaler Register 16-17
268 /*-----------------------------------------------------------------------
269 * MCR - Memory Command Register
287 /*-----------------------------------------------------------------------
288 * Machine A Mode Register 16-13
314 #define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */
367 /*-----------------------------------------------------------------------
368 * Machine B Mode Register 16-13
394 #define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
447 /*-----------------------------------------------------------------------
448 * Timer Global Configuration Register 18-8
468 /*-----------------------------------------------------------------------
469 * Timer Mode Register 18-9
475 #define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
476 #define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
489 /*-----------------------------------------------------------------------
495 #define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */
496 #define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */
497 #define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */
498 #define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */
510 /*-----------------------------------------------------------------------
511 * SPI Controller Registers 31-10
514 #define SPI_MME 0x20 /* Multi-Master Error */
522 /*-----------------------------------------------------------------------
523 * PCMCIA Interface General Control Register 17-12
531 #define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
545 /*-----------------------------------------------------------------------