Lines Matching full:6
21 #define ICHRG3 (1 << 6)
45 #define VO_2_77V 6
50 #define VGEN 6
59 #define SWMODE_PWM_AUTO 6
86 #define VSD_1_8 (0 << 6)
87 #define VSD_2_0 (1 << 6)
88 #define VSD_2_6 (2 << 6)
89 #define VSD_2_7 (3 << 6)
90 #define VSD_2_8 (4 << 6)
91 #define VSD_2_9 (5 << 6)
92 #define VSD_3_0 (6 << 6)
93 #define VSD_3_15 (7 << 6)
94 #define VSD_MASK (7 << 6)
100 #define VGEN2_1_2 (0 << 6)
101 #define VGEN2_1_5 (1 << 6)
102 #define VGEN2_1_6 (2 << 6)
103 #define VGEN2_1_8 (3 << 6)
104 #define VGEN2_2_7 (4 << 6)
105 #define VGEN2_2_8 (5 << 6)
106 #define VGEN2_3_0 (6 << 6)
107 #define VGEN2_3_15 (7 << 6)
108 #define VGEN2_MASK (7 << 6)
146 #define VCAMEN (1 << 6)
178 #define SWx_0_750V 6