Lines Matching +full:level +full:- +full:detect
1 /* SPDX-License-Identifier: GPL-2.0+ */
39 #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
116 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
135 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
160 #define UART_EFR_SCD 0x20 /* Special character detect */
178 #define UART_TI752_TLR 7 /* I/O: trigger level register */
222 * The Intel XScale on-chip UARTs define these bits
237 * Intel MID on-chip HSU (High Speed UART) defined bits
259 #define UART_RFL 0x03 /* Receiver FIFO level */
260 #define UART_TFL 0x04 /* Transmitter FIFO level */
268 #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
269 #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
270 #define UART_FCL 0x06 /* Flow Control Level Lower */
271 #define UART_FCH 0x07 /* Flow Control Level Higher */
277 #define UART_NMR 0x0D /* Nine-bit Mode Register */
293 * These definitions are for the RSA-DV II/S card, from
295 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
298 #define UART_RSA_BASE (-8)
305 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
354 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
361 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
383 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
384 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */