include/linux/serial_reg.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
43 #define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
116 #define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
120 #define UART_MCR_RTS		0x02 /* RTS complement */
126 #define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
142 #define UART_MSR_DCTS		0x01 /* Delta CTS */
158 #define UART_EFR_CTS		0x80 /* CTS flow control */
159 #define UART_EFR_RTS		0x40 /* RTS flow control */
200 #define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
210 #define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
222  * The Intel XScale on-chip UARTs define these bits
237  * Intel MID on-chip HSU (High Speed UART) defined bits
277 #define UART_NMR	0x0D	/* Nine-bit Mode Register */
293  * These definitions are for the RSA-DV II/S card, from
295  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
298 #define UART_RSA_BASE (-8)
302 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
304 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
354 #define UART_OMAP_WER		0x17	/* Wake-up enable register */
361 #define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
383 #define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
384 #define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */