Lines Matching +full:half +full:- +full:length
1 /* SPDX-License-Identifier: GPL-2.0+ */
91 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
116 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
222 * The Intel XScale on-chip UARTs define these bits
237 * Intel MID on-chip HSU (High Speed UART) defined bits
252 #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
277 #define UART_NMR 0x0D /* Nine-bit Mode Register */
293 * These definitions are for the RSA-DV II/S card, from
295 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
298 #define UART_RSA_BASE (-8)
309 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
310 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
318 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
321 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
349 #define UART_OMAP_EBLR 0x12 /* BOF length register */
354 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
361 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
377 #define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */
383 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
384 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */