linux/mtd/spi-nor.h

1 // SPDX-License-Identifier: GPL-2.0
23 #define SNOR_MFR_ST		CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON		CFI_MFR_MICRON /* ST Micro <--> Micron */
37  * requires a 4-byte (32-bit) address.
42 #define SPINOR_OP_RDSR		0x05	/* Read status register */
43 #define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
44 #define SPINOR_OP_RDSR2		0x3f	/* Read status register 2 */
46 #define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
47 #define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
48 #define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
60 #define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
61 #define SPINOR_OP_RDSFDP	0x5a	/* Read SFDP */
62 #define SPINOR_OP_RDCR		0x35	/* Read configuration register */
63 #define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
65 #define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
69 #define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
70 #define SPINOR_OP_READ_FAST_4B	0x0c	/* Read data bytes (high frequency) */
71 #define SPINOR_OP_READ_1_1_2_4B	0x3c	/* Read data bytes (Dual Output SPI) */
72 #define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
73 #define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
74 #define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
82 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
95 #define SPINOR_OP_SST_RDNVCR	0xB5	/* Read nonvolatile configuration register */
102 #define SPINOR_OP_XRDSR		0xd7	/* Read status register */
108 #define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
109 #define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
116 #define SPINOR_OP_BRRD		0x16	/* Bank register read */
117 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
118 #define SPINOR_OP_EX4B_CYPRESS	0xB8	/* Exit 4-byte mode */
119 #define SPINOR_OP_RDAR		0x65	/* Read any register */
128 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
130 #define SPINOR_OP_MICRON_RDNVCR 0xB5   /* Read nonvolatile configuration register */
135 #define SR_WEL			BIT(1)	/* Write enable latch */
138 #define SR_BP1			BIT(3)	/* Block protect 1 */
153 #define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
156 #define FSR_PT_ERR		BIT(1)	/* Protection error bit */
159 #define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */
163 #define SR2_QUAD_EN_BIT1	BIT(1)
195 	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
196 	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
197 	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
198 	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
199 	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
200 	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
201 	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
206 	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
207 	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
208 	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
209 	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
251 	SNOR_F_HAS_SR_TB	= BIT(1),
260  * struct flash_info - Forward declaration of a structure used internally by
269  * struct spi_nor - Structure for defining a the SPI NOR layer
271  * @lock:		the lock for the read/write/erase/lock/unlock operations
273  * @info:		spi-nor part JDEC MFR id and other info
277  * @read_opcode:	the read opcode
278  * @read_dummy:		the dummy needed by the read operation
280  * @bank_read_cmd:	Bank read cmd
284  * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
285  * @read_proto:		the SPI protocol for read operations
290  *			read/write/erase/lock/unlock operations
292  *			read/write/erase/lock/unlock operations
293  * @read_reg:		[DRIVER-SPECIFIC] read out the register
294  * @write_reg:		[DRIVER-SPECIFIC] write data to the register
295  * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
296  * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
297  * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
299  *			spi-nor will send the erase opcode via write_reg()
300  * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
301  * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
302  * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
303  * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
335 	ssize_t (*read)(struct spi_nor *nor, loff_t from,  member
359 	mtd_set_of_node(&nor->mtd, np);  in spi_nor_set_flash_node()
365 	return mtd_get_of_node(&nor->mtd);  in spi_nor_get_flash_node()
369  * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
378  *(Fast) Read capabilities.
381  * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
382  * (Slow) Read.
386 #define SNOR_HWCAPS_READ_FAST		BIT(1)
410  * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
411  * legacy SPI 1-1-1 protocol.
430  * spi_nor_scan() - scan the SPI NOR