Lines Matching +full:0 +full:x1c
17 unsigned int mem_cfg; /* 0x0000 */
18 unsigned char res1[0xc];
19 unsigned int burst_len; /* 0x0010 */
20 unsigned char res2[0xc];
21 unsigned int mem_reset; /* 0x0020 */
22 unsigned char res3[0xc];
23 unsigned int int_err_stat; /* 0x0030 */
24 unsigned char res4[0xc];
25 unsigned int int_err_mask; /* 0x0040 */
26 unsigned char res5[0xc];
27 unsigned int int_err_ack; /* 0x0050 */
28 unsigned char res6[0xc];
29 unsigned int ecc_err_stat; /* 0x0060 */
30 unsigned char res7[0xc];
31 unsigned int manufact_id; /* 0x0070 */
32 unsigned char res8[0xc];
33 unsigned int device_id; /* 0x0080 */
34 unsigned char res9[0xc];
35 unsigned int data_buf_size; /* 0x0090 */
36 unsigned char res10[0xc];
37 unsigned int boot_buf_size; /* 0x00A0 */
38 unsigned char res11[0xc];
39 unsigned int buf_amount; /* 0x00B0 */
40 unsigned char res12[0xc];
41 unsigned int tech; /* 0x00C0 */
42 unsigned char res13[0xc];
43 unsigned int fba; /* 0x00D0 */
44 unsigned char res14[0xc];
45 unsigned int fpa; /* 0x00E0 */
46 unsigned char res15[0xc];
47 unsigned int fsa; /* 0x00F0 */
48 unsigned char res16[0x3c];
49 unsigned int sync_mode; /* 0x0130 */
50 unsigned char res17[0xc];
51 unsigned int trans_spare; /* 0x0140 */
52 unsigned char res18[0x3c];
53 unsigned int err_page_addr; /* 0x0180 */
54 unsigned char res19[0x1c];
55 unsigned int int_pin_en; /* 0x01A0 */
56 unsigned char res20[0x1c];
57 unsigned int acc_clock; /* 0x01C0 */
58 unsigned char res21[0x1c];
59 unsigned int err_blk_addr; /* 0x01E0 */
60 unsigned char res22[0xc];
61 unsigned int flash_ver_id; /* 0x01F0 */
62 unsigned char res23[0x6c];
63 unsigned int watchdog_cnt_low; /* 0x0260 */
64 unsigned char res24[0xc];
65 unsigned int watchdog_cnt_hi; /* 0x0270 */
66 unsigned char res25[0xc];
67 unsigned int sync_write; /* 0x0280 */
68 unsigned char res26[0x1c];
69 unsigned int cold_reset; /* 0x02A0 */
70 unsigned char res27[0xc];
71 unsigned int ddp_device; /* 0x02B0 */
72 unsigned char res28[0xc];
73 unsigned int multi_plane; /* 0x02C0 */
74 unsigned char res29[0x1c];
75 unsigned int trans_mode; /* 0x02E0 */
76 unsigned char res30[0x1c];
77 unsigned int ecc_err_stat2; /* 0x0300 */
78 unsigned char res31[0xc];
79 unsigned int ecc_err_stat3; /* 0x0310 */
80 unsigned char res32[0xc];
81 unsigned int ecc_err_stat4; /* 0x0320 */
82 unsigned char res33[0x1c];
83 unsigned int dev_page_size; /* 0x0340 */
84 unsigned char res34[0x4c];
85 unsigned int int_mon_status; /* 0x0390 */
89 #define ONENAND_MEM_RESET_HOT 0x3
90 #define ONENAND_MEM_RESET_COLD 0x2
91 #define ONENAND_MEM_RESET_WARM 0x1
93 #define INT_ERR_ALL 0x3fff
107 #define LD_FAIL_ECC_ERR (1 << 0)
109 #define TSRF (1 << 0)