linux/mtd/rawnand.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8  *	Contains standard defines and IDs for NAND flash devices
29 /* Get the flash and manufacturer id and lookup if the type is supported. */
35 /* Scan and identify a NAND device */
39  * and override command or ECC setup according to flash type.
45 /* Free resources held by the NAND device */
77  * Standard NAND flash commands
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE		-1
132 #define NAND_DATA_IFACE_CHECK_ONLY	-1
159 /* Enable Hardware ECC before syndrome is read back from flash */
163  * Enable generic NAND 'page erased' check. This check is only done when
164  * ecc.correct() returns -EBADMSG.
166  * pages and you want to rely on the default implementation.
171  * If your controller already sends the required NAND commands when
194  * Chip requires ready check on read (for auto-incremented sequential read).
203 /* Device is one of 'new' xD cards that expose fake nand command set */
206 /* Device behaves just like nand, but is readonly */
225 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
226 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
227 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
230 /* This option skips the bbt scan during initialization. */
234  * (e.g. because it needs them DMA-coherent).
240  * Autodetect nand buswidth with readid/onfi.
252 /* Options set by nand scan */
253 /* bbt has already been read */
255 /* Nand scan has allocated controller struct */
279 /* Vendor-specific feature address (Micron) */
489 …* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared am…
492  * @wq:			wait queue to sleep on if a NAND operation is in
502  * struct nand_ecc_step_info - ECC step information of ECC engine
514  * struct nand_ecc_caps - capability of ECC engine
540  * struct nand_ecc_ctrl - Control structure for ECC
558  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
561  *		If -EBADMSG is returned the input buffers should be left
565  *			controller and always return contiguous in-band and
566  *			out-of-band data even if they're not stored
567  *			contiguously on the NAND chip (e.g.
568  *			NAND_ECC_HW_SYNDROME interleaves in-band and
569  *			out-of-band data).
573  *			in-band and out-of-band data. ECC controller is
576  *			NAND_ECC_HW_SYNDROME interleaves in-band and
577  *			out-of-band data).
580  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
633 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);  in nand_standard_page_accessors()
637  * struct nand_buffers - buffer structure for read/write
639  * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
653  * struct nand_sdr_timings - SDR NAND chip timings
655  * This struct defines the timing requirements of a SDR NAND chip.
656  * These information can be found in every NAND datasheets and the timings
674  * @tCHZ_max: CE# high to output hi-Z
683  * @tIR_min: Output hi-Z to RE# low
690  * @tRHZ_max: RE# high to output hi-Z
745  * enum nand_data_interface_type - NAND interface timing type
753  * struct nand_data_interface - NAND interface timing
765  * nand_get_sdr_timings - get SDR timing from data interface
771 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
772 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
774 	return &conf->timings.sdr;  in nand_get_sdr_timings()
778  * struct nand_chip - NAND Private Flash Chip Data
781  *			flash device
783  *			flash device.
787  * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
802  * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
804  * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
805  *			setting the read-retry mode. Mostly needed for MLC NAND.
809  * @hwcontrol:		platform-specific hardware control structure
814  * @state:		[INTERN] the current state of the NAND device
820  * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
843  *			      the NAND chip is not ONFI compliant.
846  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
861  * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
862  * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
867  * @bbt:		[INTERN] bad block table pointer
868  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
877  * @write_page:		[REPLACEABLE] High-level page write function
955 	uint8_t *bbt;  member
971 	return &chip->mtd;  in nand_to_mtd()
976 	return chip->priv;  in nand_get_controller_data()
981 	chip->priv = priv;  in nand_set_controller_data()
985  * NAND Flash Manufacturer ID Codes
1002 /* The maximum expected count of bytes in the NAND ID sequence */
1006  * A helper for defining older NAND chips where the second ID byte fully
1008  * size). All these chips have 512 bytes NAND page size.
1030 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1031 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1034  * struct nand_flash_dev - NAND Flash Device ID Structure
1035  * @name: a human-readable name of the NAND chip
1042  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1043  *            well as the eraseblock size) is determined from the extended NAND
1057  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1085  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1113  * struct platform_nand_chip - chip level device structure
1120  * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
1121  * @part_probe_types:	NULL-terminated array of probe types
1138  * struct platform_nand_ctrl - controller level device structure
1151  * All fields are optional and depend on the hardware driver requirements
1167  * struct platform_nand_data - container structure for platform-specific data
1180 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;  in onfi_feature()
1186 	if (!chip->onfi_version)  in onfi_get_async_timing_mode()
1188 	return le16_to_cpu(chip->onfi_params.async_timing_mode);  in onfi_get_async_timing_mode()
1194 	if (!chip->onfi_version)  in onfi_get_sync_timing_mode()
1196 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);  in onfi_get_sync_timing_mode()
1221  * Check if it is a SLC nand.
1222  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1227 	return chip->bits_per_cell == 1;  in nand_is_slc()
1231  * Check if the opcode's address should be sent only on the lower 8 bits
1251 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)  in jedec_feature()
1255 /* Standard NAND functions from nand_base.c */
1281 /* Reset and initialize a NAND device */